48 results about "Very large scale integrated circuits" patented technology

The invention discloses a VLSI circuit layout optimization method and system based on deep learning in the technical field of integrated circuits, and the method comprises the steps: abstracting a large-scale integrated circuit into a hypergraph structure, receiving the hypergraph structure, generating a node embedding matrix through a hypergraph neural network, and optimizing a segmentation loss function through unsupervised training, obtaining a probability distribution matrix, determining segmented subsets based on the probability distribution matrix, mapping each subset to a physical layout unit, generating a physical region layout of the chip according to an area equilibrium constraint and a time sequence constraint, performing constraint feedback on a physical layout result, and dynamically adjusting parameters of the segmentation loss function. The method can be used for circuit layout of a super-large-scale integrated circuit, and an optimization method and means are provided for providing a high-quality VLSI circuit layout scheme.

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The invention relates to a power network structure weakness detection method based on multi-diagonal-block matrix decomposition, and belongs to the technical field of super-large-scale integrated circuits. According to the method, an original large-scale sparse matrix is converted into a band edge diagonal block structure and divided into a plurality of sub-matrixes capable of being solved independently by constructing a layering and blocking strategy for eliminating tree drive, and redundancy of full-matrix calculation is avoided. Meanwhile, a local approximate inverse algorithm of column norm truncation is designed, and target elements are calculated on the premise that a preset error threshold value is met. According to the method, the parallel computing architecture of the multi-core processor is fully utilized, the computing complexity is reduced by 2-3 orders of magnitude, the computing efficiency is effectively improved, the memory occupation is remarkably reduced, and a high-precision and high-efficiency solution is provided for detecting the weakness of the power network structure of the super-large-scale integrated circuit.

The invention discloses a production process of spherical alumina powder with high purity and low uranium content, which comprises the following steps: by taking angular alumina with the uranium content of 50-100ppb as a raw material, sequentially carrying out flame melting spheroidization, gradient pickling, hydrothermal strengthening uranium removal, wet grading coarse grain removal, low-temperature drying and airflow depolymerization to finally obtain the finished product spherical alumina powder with the uranium content of less than 30ppb. Through a multi-stage uranium removal system including incoming material management and control, gradient pickling, hydrothermal coupling and particle size optimization, the traditional single pickling efficiency bottleneck is broken through, and deep dissolution of lattice uranium and effective removal of coarse-grain uranium enrichment nuclei are achieved; the morphology and the specific surface are locked through whole-process low-temperature hydrothermal and low-shear drying, so that the powder is ensured to be used as a filler in resin sealing materials of high-integration integrated circuits, large-scale integrated circuits and super-large-scale integrated circuits, and the powder has the comprehensive performance of high filling, low thermal resistance and zero alpha-ray soft errors; and the limit requirements of node packaging materials of 3nm and below are met.

The invention relates to the technical field of very large scale integrated circuit design verification, and discloses a hierarchical cross-clock domain signal verification method, device and equipment and a medium. According to the method, on the basis of the physical layout information file corresponding to each functional module, the target functional module to be verified is dynamically, intelligently and accurately determined from the plurality of functional modules. And performing cross-clock domain signal verification on the previous level of the target function module by extracting the target sign-off abstract model of the target function module, and performing cross-clock domain signal verification on the top system of the whole chip by analogy. As clock domain crossing signal verification does not need to be carried out on all functional modules, the efficiency of chip verification can be improved, clock domain crossing signal verification, module level focusing functional module internal logic integrity verification and top layer enhanced module crossing asynchronous path analysis are carried out on the chip layer by layer through the target sign-off abstract model, and the chip verification efficiency is improved. Therefore, the accuracy of chip verification can be improved.

The invention relates to fluorine-free polyimide containing hydrophobic groups and a preparation method thereof, and belongs to the field of novel high-performance polyimide materials. The fluorine-free polyimide containing the hydrophobic group has a repeating unit structure shown in a general formula (I) and is obtained by polymerizing a fluorine-free diamine monomer containing the hydrophobic group and having a structure shown in a general formula (II) with specific diamine and dianhydride monomers. The fluorine-free polyimide containing the hydrophobic group has relatively low water absorption rate, has a low dielectric constant and a low loss factor at high frequency, has excellent solubility and thermal stability, can meet the performance requirements of a high-frequency and high-speed circuit on a substrate material, and has a wide application prospect. The material can be used as an excellent fluoride-free insulating base material in the fields of super-large-scale integrated circuits, photosensitive polyamideimide and the like.

The application provides a high-strength calcium-aluminum-silicon glass-ceramics and a preparation method thereof, and belongs to the field of electronic ceramic materials. The material composition is as follows: CaO is 15-25wt%, Al2O3 is 10-15wt%, SiO2 is 50-65wt%, and ZnO+BaO is 10wt%. The high-strength calcium-aluminum-silicon glass-ceramics provided by the application has the main crystal phase of wollastonite CaSiO3, the secondary crystal phase of barium feldspar BaAl2Si2O8 and quartz SiO2. By adjusting the Zn / Ba ratio, the bending strength 193MPa and the Young's modulus 79GPa are improved, the thermal expansion coefficient 5.11ppm / ℃ is improved, and the reliability of the ultra-large scale integrated circuit package is improved. In addition, the preparation method provided by the application has the advantages of low cost, simple process and the like, is beneficial to industrialized production, and has potential application value for the ultra-large scale integrated circuit package substrate.

The present disclosure relates to a method, system, storage medium and electronic device for very large scale integrated circuit; the method for very large scale integrated circuit obtains timing information TNS of the entire netlist of the very large scale integrated circuit; all nodes are sorted according to the topology structure of the integrated circuit, and nodes with the same serial number are placed in the same queue; all sorted nodes are traversed in reverse according to the number of queues; the size reduction preprocessing is performed on all nodes in the same queue, and the slack change value of the output pin of the current node and the next level node is obtained; the slack change value of the output pin of the current node and the next level node is checked, the current node with the slack change value of the output pin meeting the requirements is subjected to size reduction processing; the timing information of the current node and the next level node is updated, the timing information new_TNS of the entire netlist is reobtained; the timing information new_TNS and TNS are compared, and the area power consumption in the physical optimization of the very large scale integrated circuit is optimized according to the comparison result. The problem of excessive area power consumption in the physical optimization design process under the condition of unchanged timing can be solved.

The application provides a high-dimensional multi-objective evolutionary method based on an improved dominance criterion, which is used for optimizing the wiring design of a very large scale integrated circuit physical design and comprises the following steps: step one, convergence of a non-dominated solution set is ensured according to a defined convergence index, and an adaptive parameter based on a genetic algorithm niche is combined to control the diversity of the solution set, the radius target and the line length target of the wiring design are optimized by minimizing MOP, and the dominance criterion is improved; step two, a convergence index and a diversity index are designed, the two indexes jointly constitute a dynamic fitness function, and individuals with better convergence and diversity are adaptively reserved to perform MaOEA-IDR environment selection; and step three, an adaptive t distribution crossover operator is provided, which can balance the global search capability of a Cauchy operator and the local exploration capability of a Gaussian operator in a high-dimensional space, and the ASDX adaptive distribution crossover operator is adaptively adjusted. t The application can effectively solve the wiring problem of the very large scale integrated circuit physical design.

The invention discloses a large language model softmax function hardware acceleration circuit and method, and belongs to the field of neural network hardware acceleration of super-large scale integrated circuits. An input sequence is divided into a plurality of data blocks which are processed in parallel, and three-stage pipeline division is adopted, so that average single calculation delay is shortened to G clock cycles, the calculation parallelism is improved, the calculation speed of a softmax function is improved, and the reasoning delay is reduced; and a sparse mask strategy of sparse threshold comparison is introduced, the sparsity of data is fully utilized, the problems of high calculation complexity and high calculation delay of the softmax function and the data access bottleneck of the softmax function are solved, the calculation cost is remarkably reduced, and the calculation efficiency is improved. In addition, a softmax function hardware circuit adaptive to software optimization is constructed, calculation delay and memory access pressure are reduced through the hardware circuit, and data processing efficiency is improved.

The present invention discloses a wiring layering method, system and storage medium for a very large scale integrated circuit, comprising: obtaining an artificial configuration file, establishing a wire net frame of the wire net; calculating feasible solutions and weights for allocating the wire net to each layer; iteratively calculating the number of wire nets N under the current k wiring layering schemes; m The i-th feasible solution is assigned to any optional layer L m The wiring weight w i (N m , L), update the feasible solution s of each network layer during iteration i (N1,…,N m ), and the feasible solution weight w i (N1,…,N m ), the feasible solution corresponding to the feasible solution weight with the smallest value is used as the optimal layering scheme of the network cable. The wiring layering scheme of the present invention can not only make the wiring meet the constraint conditions, but also can efficiently obtain the optimal wiring layering scheme.

The invention discloses a virtual filling method for chemical mechanical polishing based on neural network gradient feedback, and belongs to the field of semiconductors and CMOS (complementary metal oxide semiconductor) super-large-scale integrated circuits. The method is divided into three stages of layout data processing, neural network prediction and optimization solution and virtual filling insertion, an input GDS layout is divided into uniform windows, a fillable area is determined according to pattern information in the windows, the window density and the upper and lower limits of the window density are extracted, window data is converted into a nonlinear optimization problem, and the optimization problem is solved. The flatness loss of the layout after CMP is predicted by calling a neural network to serve as an optimization target, meanwhile, the input density of each window is iterated according to gradient information provided by the neural network, and finally, a virtually filled layout file is output. According to the method, the interpretability of a prediction result is enhanced in the calculation process, and the problems of low efficiency and suboptimal solution of a traditional optimization algorithm in the aspect of large-scale optimization are solved.

The invention provides a synthesis method of a high-purity hafnium-zirconium metal complex precursor, and belongs to the technical field of high-dielectric-constant materials for super-large-scale integrated circuits. According to the method, hafnium tetrachloride or zirconium tetrachloride is used as a metal source and sequentially reacts with dialkylamine, n-butyllithium and an alkyl magnesium halide Grignard reagent through a one-pot method in a high-purity inert atmosphere, an intermediate does not need to be separated, and a target precursor is obtained after filtration, washing and rectification. The method is simple and convenient in process operation, mild in reaction condition and low in energy consumption; the raw materials are wide in source and low in price, the product yield reaches 82%-88%, and the metal purity is stabilized to be 6N; when the precursor is used for preparing a hafnium oxide / zirconium thin film through atomic layer deposition (ALD), the thickness of the thin film reaches 14.3 nm under 100 cycles, the non-uniformity is smaller than or equal to 0.90%, the requirement of a gate dielectric layer of a super-large-scale integrated circuit for a high-purity and high-efficiency precursor can be met, and the precursor is suitable for industrial amplification production.

The invention relates to the technical field of super-large-scale integrated circuit manufacturing in the semiconductor industry, and particularly provides a low-temperature polycrystalline silicon thin film transistor, a display panel and a preparation method. The method aims at solving the problems that in the prior art, an optimization method for interface defects is still high in process complexity, cost is increased or the effect is limited. Therefore, the invention provides a preparation method of a low-temperature polycrystalline silicon thin film transistor, which comprises the following steps of: forming an amorphous silicon layer on a substrate; forming a silicon oxide layer on the amorphous silicon layer; laser annealing is carried out, so that the amorphous silicon layer is converted into a polycrystalline silicon layer, the polycrystalline silicon layer is used for forming a channel region and an electrode contact region of the low-temperature polycrystalline silicon thin film transistor, and the thickness of the silicon oxide layer is configured to be capable of inhibiting the height of protrusions formed when the amorphous silicon layer is converted into the polycrystalline silicon layer. According to the method, the protruding height of the polycrystalline silicon layer is reduced, the interface defects of polycrystalline silicon and GI are optimized, and the problems of residual images and the like caused by accumulation of the interface defects are solved.

The present invention discloses a test device for an integrated circuit, comprising five parts: a driving motherboard, a main control board, a digital core board, an analog signal board, and a driving module. The driving motherboard comprises various interfaces, a secondary power generation module, a detection module, and a CPLD logic bonding module. The digital core board is used for online configuration of test codes. The analog signal board is used for providing analog signals required by the device. The driving module is used for driving and amplifying the output signals of the digital core board. The present invention can generate test vectors with a maximum frequency of 20 MHz, a minimum programming step length of 25 ns, a programming resolution of 25 ns, and a signal high-level voltage of up to 6 V, meeting the testing requirements of more devices and more functions. The present invention can generate analog signals with a maximum frequency of 1 MHz and a peak value of up to 20 V, meeting the testing requirements of more devices and more functions. The present invention can generate 256 test signals, meeting the testing requirements of ultra-large-scale integrated circuits. Utilizing a modular design, each functional module can be disassembled and replaced, facilitating maintenance and replacement.

The application discloses a congestion prediction method for a super large scale integrated circuit, constructs a neural network model based on a U-Net structure, takes output of an EDA tool, a cell distribution feature map calculated quickly, a rectangular region line density (RUDY) of a wiring resource demand index and a pinRUDY as model input, and obtains a congestion hotspot map of global wiring, so that a long time-consuming problem of accurate prediction of integrated circuit congestion can be solved, and the result quality and execution efficiency of a layout and wiring tool are improved. Based on the application, the time for calculating congestion distribution of a single chip is about 0.0065s, which is improved by 6 orders of magnitude compared with EDA; compared with a congestion map output by the EDA tool, the SSIM index is about 0.7935 (nrmse=0.0045), and the prediction accuracy is more than 80%.

To solve the critical technological challenge of reliably manufacturing high aspect ratio features, which is essential for next-generation ultra-large-scale and extreme large-scale integration in semiconductor devices.SOLUTION: The present disclosure describes a feedback loop that can be used to maintain a substantially constant sheath voltage and thereby generate a single-energy IEDF on the substrate surface. Therefore, the system described herein ultimately enables precise control over the shape of the IEDF and the profile of the features formed on the substrate surface.SELECTED DRAWING: Figure 1B

The data processing method provided by the present invention sets a plurality of nodes, and the plurality of nodes are provided with a hierarchy, divided into root nodes, branch nodes and leaf nodes, forming a two-dimensional space point index tree structure; the plurality of nodes store node information in whole or in part; the node information includes: information and a list of the region boundary box corresponding to the node, the list stores the number of basic graphic elements, the basic graphic element number, the layer information to which it belongs, and the adjacent layer information. The data structure generation method provided by the present invention can generate a file of the data structure of the data processing method of the present invention, and has corresponding advantages. The query method of the present invention is used to check the connection relationship between the basic graphic elements in the layout file. The data structure obtained based on the data structure generation method of the present invention has corresponding advantages, can greatly improve the inspection speed, and is conducive to further improving the design level of ultra-large-scale integrated circuits.

The present disclosure relates to a method, system, storage medium and electronic device for very large scale integrated circuit. The method for very large scale integrated circuit comprises the following steps: obtaining timing information TNS of the entire netlist of the integrated circuit; obtaining the worst timing path through each end node in the netlist; scanning all cell nodes in the worst timing path, and obtaining the number of worst timing paths of each cell node; obtaining the slack value of the worst output pin of the cell node for each cell node on the worst timing path; performing downsize estimation processing on the cell node, and obtaining the downsize estimation score of the cell node based on the number of worst timing paths of the cell node and the slack value of the worst output pin; arranging the downsize estimation scores of the cell nodes in descending order, selecting the first N cell nodes for downsize processing, and calculating the timing information new_TNS of the netlist; and optimizing the area power consumption in the physical optimization of the integrated circuit according to the timing information new_TNS and the timing information TNS of the entire netlist. The problem of excessive area power consumption in the physical optimization design process under the condition of unchanged timing can be solved.

The application discloses an anti-radiation three-mode redundant latch, and belongs to the field of anti-radiation design of special integrated circuits. The application designs a novel main-stage latch and a novel redundant voting circuit, which comprises a first transistor-stage voting circuit, a second transistor-stage voting circuit and a protection gate circuit. The application reinforces the main-stage latch and the voting circuit from the circuit structure, enhances the resistance of the main-stage latch to SNU and DNU, reduces the influence of SNU of the voting circuit itself on the output result, and enhances the stability of the three-mode redundant system. The total number of MOS tubes of the redundant voting circuit of the application is only 30% of the total number of MOS tubes of the full three-mode redundant voting circuit, effectively reduces the area cost of the three-mode redundant system, and is more suitable for the anti-radiation design of super large scale integrated circuits.

The invention relates to the field of computer equipment based on a specific calculation model, can be used for designing neuromorphic processor equipment, and can also be used for the fields of central and graphics processor equipment and the like. The pipelined multiplier may be part of an arithmetic coprocessor of a neuromorphic VLSI (very large scale integrated circuit) processor core, intended to perform a multiplication operation on two binary operands, or a combined multiplication-addition operation (MAC operation) on three operands. The two primary operands are integers in the range from-32768 to 32767, 16 bits long, represented in additional codes. The third additional operand of the MAC operation and the operand of the operation result are 32-bit integers presented in additional codes. The pipelined multiplier includes the use of the claimed invention, capable of quickly performing a large number of multiplications or combined multiply-add operations in a pipelined operation mode, i.e., in each operation cycle, receiving a new set of operand values at the input and generating a new result at the output based on the old set of operand values.

A computer implemented method includes determining a noise adjustment value for a specific subnet of a very large scale integrated (VLSI) circuit. A K factor for the specific subnet is determined based on the noise adjustment value of the specific subnet. The K factor is constant such that a timing of the specific subnet including the K factor is equal to the noise adjustment value of the specific subnet. The K factor for the specific subnet is stored in a design architecture.

The invention provides low-expansion zinc-aluminum-silicon microcrystalline glass and a preparation method thereof, and belongs to the field of electronic ceramic materials. The material is prepared from the following components in percentage by weight: 15 to 25 percent of ZnO, 23 to 25 percent of Al2O3, 37 to 45 percent of SiO2, 10 to 15 percent of B2O3, 0 to 3 percent of MgO and 0 to 5 percent of K2O. The main crystalline phase of the zinc-aluminum-silicon microcrystalline glass provided by the invention is zinc-aluminum spinel ZnAl2O4, and the zinc-aluminum-silicon microcrystalline glass has the thermal expansion coefficient of 4.47-5.28 ppm / DEG C, the bending strength of 130-155 MPa, the Young modulus of 73-83 GPa, the dielectric constant of 5.24-6.91 and the dielectric loss of 2.3-2.9 * 10 <-3 >. The preparation method provided by the invention is low in cost, simple in process, beneficial to industrial production and suitable for a super-large-scale integrated circuit packaging substrate.

The application discloses a kind of molecular dynamics simulation methods of Cu interconnect dielectric material.It is established interconnect dielectric material SiCOH molecular dynamics model using melting-cooling method according to molecular dynamics theory, the feasibility of model is verified using structure and dielectric property, on this basis, the optimal performance combination of interconnect dielectric material is obtained by calculating electric, thermal, mechanical properties and fracture mechanics properties with adjacent interconnect structure, and the result is fed back to adjust to guide material design.The application establishes the simulation model of dielectric material SiCOH performance by molecular dynamics simulation, obtains the optimal performance parameter combination for packaging structure and product, reduces the cost of test and production trial and error, so as to guide the design of high-performance, high-reliability very large scale integrated circuit post-process interconnect material and structure.

The present application relates to a constrained multi-objective evolutionary method based on multi-stage search. Different search strategies are adopted in three stages of the method. In order to make the population quickly cross the large infeasible region and approach the Pareto front, the method does not consider the constraint condition in the first stage, and a convergence index is used to guide the population search; a set of uniformly distributed weight vectors is used to maintain the diversity of the population in the second stage, and an improved epsilon constraint processing strategy is proposed to retain high-quality solutions in the infeasible region; and the constraint priority principle is adopted in the third stage to concentrate the search preference in the feasible region to ensure the feasibility of the final solution set.

The embodiment of the invention provides a defect detection method for a super-large-scale integrated circuit, computer equipment and a storage medium. The method comprises the steps that a to-be-tested super-large-scale integrated circuit is divided into a plurality of basic function areas, and each basic function area is used for achieving a corresponding basic function; analyzing a logic tree of a test sample, and selecting at least one target basic function area associated with the logic tree of the test sample from the plurality of basic function areas; arranging and combining the selected target basic functional areas based on the logic tree of the test sample to obtain a to-be-tested functional area combination; and testing the functional region combination to be tested by using the test sample to determine the logic defects among the target basic functional regions in the functional region combination to be tested, and the method can be used for detecting the logic defects in the super-large-scale integrated circuit.

The invention relates to a via hole pitch parameter calculation method, computer equipment, a medium and a product. The calculation method comprises the following steps of: obtaining netlist structure information in the design of the super-large-scale integrated circuit, and filtering disconnected parts of a line net and parts where no current passes actually; starting from an input pin of each line network, searching for interconnection lines and via holes in contact with the line network, marking an initial node, recording the position of a contact point, and recursively searching for the associated interconnection lines or via holes until returning to an output pin of the line network; according to the central point positions of the interconnection lines and the via holes and the metal layer where the interconnection lines are located, the relative connection relation between the interconnection lines and the via holes is determined, and a tree-shaped network structure is constructed; constructing a virtual interconnection line; and performing bidirectional traversal on any intermediate node of the tree network structure, traversing all nodes in the path upwards and downwards along the tree network structure, and calculating the sum of the distances among all via hole nodes in the traversal path to obtain the via hole pitch.

This invention discloses a deep learning-based VLSI circuit layout optimization method and system in the field of integrated circuit technology. The method includes the following steps: abstracting a large-scale integrated circuit into a hypergraph structure; receiving the hypergraph structure; generating a node embedding matrix using a hypergraph neural network; optimizing the segmentation loss function through unsupervised training to obtain a probability distribution matrix; determining the segmented subsets based on the probability distribution matrix; mapping each subset to a physical layout unit; generating the physical region layout of the chip according to area balance constraints and timing constraints; providing constraint feedback on the physical layout results; and dynamically adjusting the parameters of the segmentation loss function until all physical constraints are met. This invention can be used for the layout of very large-scale integrated circuits, providing an optimization method and means for providing high-quality VLSI circuit layout solutions.

The invention relates to a local density sensing buffer insertion method, and belongs to the field of super-large-scale integrated circuits. The method comprises the following steps: uniformly dividing a physical design area of a chip into a plurality of rectangular grids, traversing and calculating local layout density values of all the grids, and forming a digital density map; based on the digital density map, high-density areas are identified by adopting a density-based clustering algorithm, and each identified high-density area is marked as a density obstacle; aiming at a target line network, generating an interconnection tree capable of avoiding all density obstacles, and generating a series of buffer insertion candidate points on a path of the interconnection tree; an improved dynamic programming algorithm is adopted, searching is carried out in a candidate point set formed by buffer insertion candidate points, and a final buffer insertion position and type are determined by taking a signal time sequence and local density cost caused by buffer insertion as optimization targets together. According to the method, the whole-process density perception optimization from global planning to local decision is realized.

The present invention proposes a fully analog vector-matrix multiplication in-memory computing circuit and its application, belonging to the field of in-memory computing technology in semiconductors and CMOS ultra-large-scale integrated circuits. The circuit includes an input circuit, an array, an output clamping circuit, and an analog shift-and-add unit. The input circuit samples and holds the analog input, and then inputs it into the array. The array uses resistive devices to store weights in the form of conductance. According to Kirchhoff's law and Ohm's law, the analog input and conductance are multiplied to complete the vector-matrix multiplication of the input and the weight. The output clamping circuit clamps the array output point to zero level and converts the calculation result in current form into voltage form for output. The analog shift-and-add unit circuit is used to shift and add the calculation results of each column to complete the carry calculation. Unlike traditional in-memory computing circuits that work in a mixed digital-analog computing mode, the present invention works completely in the analog domain, and the area and power consumption problems of the in-memory computing circuit are effectively improved.