27 results about "Very large scale integrated circuits" patented technology

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The invention discloses a production process of spherical alumina powder with high purity and low uranium content, which comprises the following steps: by taking angular alumina with the uranium content of 50-100ppb as a raw material, sequentially carrying out flame melting spheroidization, gradient pickling, hydrothermal strengthening uranium removal, wet grading coarse grain removal, low-temperature drying and airflow depolymerization to finally obtain the finished product spherical alumina powder with the uranium content of less than 30ppb. Through a multi-stage uranium removal system including incoming material management and control, gradient pickling, hydrothermal coupling and particle size optimization, the traditional single pickling efficiency bottleneck is broken through, and deep dissolution of lattice uranium and effective removal of coarse-grain uranium enrichment nuclei are achieved; the morphology and the specific surface are locked through whole-process low-temperature hydrothermal and low-shear drying, so that the powder is ensured to be used as a filler in resin sealing materials of high-integration integrated circuits, large-scale integrated circuits and super-large-scale integrated circuits, and the powder has the comprehensive performance of high filling, low thermal resistance and zero alpha-ray soft errors; and the limit requirements of node packaging materials of 3nm and below are met.

The invention relates to the technical field of very large scale integrated circuit design verification, and discloses a hierarchical cross-clock domain signal verification method, device and equipment and a medium. According to the method, on the basis of the physical layout information file corresponding to each functional module, the target functional module to be verified is dynamically, intelligently and accurately determined from the plurality of functional modules. And performing cross-clock domain signal verification on the previous level of the target function module by extracting the target sign-off abstract model of the target function module, and performing cross-clock domain signal verification on the top system of the whole chip by analogy. As clock domain crossing signal verification does not need to be carried out on all functional modules, the efficiency of chip verification can be improved, clock domain crossing signal verification, module level focusing functional module internal logic integrity verification and top layer enhanced module crossing asynchronous path analysis are carried out on the chip layer by layer through the target sign-off abstract model, and the chip verification efficiency is improved. Therefore, the accuracy of chip verification can be improved.

The invention relates to fluorine-free polyimide containing hydrophobic groups and a preparation method thereof, and belongs to the field of novel high-performance polyimide materials. The fluorine-free polyimide containing the hydrophobic group has a repeating unit structure shown in a general formula (I) and is obtained by polymerizing a fluorine-free diamine monomer containing the hydrophobic group and having a structure shown in a general formula (II) with specific diamine and dianhydride monomers. The fluorine-free polyimide containing the hydrophobic group has relatively low water absorption rate, has a low dielectric constant and a low loss factor at high frequency, has excellent solubility and thermal stability, can meet the performance requirements of a high-frequency and high-speed circuit on a substrate material, and has a wide application prospect. The material can be used as an excellent fluoride-free insulating base material in the fields of super-large-scale integrated circuits, photosensitive polyamideimide and the like.

The application provides a high-strength calcium-aluminum-silicon glass-ceramics and a preparation method thereof, and belongs to the field of electronic ceramic materials. The material composition is as follows: CaO is 15-25wt%, Al2O3 is 10-15wt%, SiO2 is 50-65wt%, and ZnO+BaO is 10wt%. The high-strength calcium-aluminum-silicon glass-ceramics provided by the application has the main crystal phase of wollastonite CaSiO3, the secondary crystal phase of barium feldspar BaAl2Si2O8 and quartz SiO2. By adjusting the Zn / Ba ratio, the bending strength 193MPa and the Young's modulus 79GPa are improved, the thermal expansion coefficient 5.11ppm / ℃ is improved, and the reliability of the ultra-large scale integrated circuit package is improved. In addition, the preparation method provided by the application has the advantages of low cost, simple process and the like, is beneficial to industrialized production, and has potential application value for the ultra-large scale integrated circuit package substrate.

The present disclosure relates to a method, system, storage medium and electronic device for very large scale integrated circuit; the method for very large scale integrated circuit obtains timing information TNS of the entire netlist of the very large scale integrated circuit; all nodes are sorted according to the topology structure of the integrated circuit, and nodes with the same serial number are placed in the same queue; all sorted nodes are traversed in reverse according to the number of queues; the size reduction preprocessing is performed on all nodes in the same queue, and the slack change value of the output pin of the current node and the next level node is obtained; the slack change value of the output pin of the current node and the next level node is checked, the current node with the slack change value of the output pin meeting the requirements is subjected to size reduction processing; the timing information of the current node and the next level node is updated, the timing information new_TNS of the entire netlist is reobtained; the timing information new_TNS and TNS are compared, and the area power consumption in the physical optimization of the very large scale integrated circuit is optimized according to the comparison result. The problem of excessive area power consumption in the physical optimization design process under the condition of unchanged timing can be solved.

The application provides a high-dimensional multi-objective evolutionary method based on an improved dominance criterion, which is used for optimizing the wiring design of a very large scale integrated circuit physical design and comprises the following steps: step one, convergence of a non-dominated solution set is ensured according to a defined convergence index, and an adaptive parameter based on a genetic algorithm niche is combined to control the diversity of the solution set, the radius target and the line length target of the wiring design are optimized by minimizing MOP, and the dominance criterion is improved; step two, a convergence index and a diversity index are designed, the two indexes jointly constitute a dynamic fitness function, and individuals with better convergence and diversity are adaptively reserved to perform MaOEA-IDR environment selection; and step three, an adaptive t distribution crossover operator is provided, which can balance the global search capability of a Cauchy operator and the local exploration capability of a Gaussian operator in a high-dimensional space, and the ASDX adaptive distribution crossover operator is adaptively adjusted. t The application can effectively solve the wiring problem of the very large scale integrated circuit physical design.

The invention provides a synthesis method of a high-purity hafnium-zirconium metal complex precursor, and belongs to the technical field of high-dielectric-constant materials for super-large-scale integrated circuits. According to the method, hafnium tetrachloride or zirconium tetrachloride is used as a metal source and sequentially reacts with dialkylamine, n-butyllithium and an alkyl magnesium halide Grignard reagent through a one-pot method in a high-purity inert atmosphere, an intermediate does not need to be separated, and a target precursor is obtained after filtration, washing and rectification. The method is simple and convenient in process operation, mild in reaction condition and low in energy consumption; the raw materials are wide in source and low in price, the product yield reaches 82%-88%, and the metal purity is stabilized to be 6N; when the precursor is used for preparing a hafnium oxide / zirconium thin film through atomic layer deposition (ALD), the thickness of the thin film reaches 14.3 nm under 100 cycles, the non-uniformity is smaller than or equal to 0.90%, the requirement of a gate dielectric layer of a super-large-scale integrated circuit for a high-purity and high-efficiency precursor can be met, and the precursor is suitable for industrial amplification production.

The invention relates to the technical field of super-large-scale integrated circuit manufacturing in the semiconductor industry, and particularly provides a low-temperature polycrystalline silicon thin film transistor, a display panel and a preparation method. The method aims at solving the problems that in the prior art, an optimization method for interface defects is still high in process complexity, cost is increased or the effect is limited. Therefore, the invention provides a preparation method of a low-temperature polycrystalline silicon thin film transistor, which comprises the following steps of: forming an amorphous silicon layer on a substrate; forming a silicon oxide layer on the amorphous silicon layer; laser annealing is carried out, so that the amorphous silicon layer is converted into a polycrystalline silicon layer, the polycrystalline silicon layer is used for forming a channel region and an electrode contact region of the low-temperature polycrystalline silicon thin film transistor, and the thickness of the silicon oxide layer is configured to be capable of inhibiting the height of protrusions formed when the amorphous silicon layer is converted into the polycrystalline silicon layer. According to the method, the protruding height of the polycrystalline silicon layer is reduced, the interface defects of polycrystalline silicon and GI are optimized, and the problems of residual images and the like caused by accumulation of the interface defects are solved.

The present disclosure relates to a method, system, storage medium and electronic device for very large scale integrated circuit. The method for very large scale integrated circuit comprises the following steps: obtaining timing information TNS of the entire netlist of the integrated circuit; obtaining the worst timing path through each end node in the netlist; scanning all cell nodes in the worst timing path, and obtaining the number of worst timing paths of each cell node; obtaining the slack value of the worst output pin of the cell node for each cell node on the worst timing path; performing downsize estimation processing on the cell node, and obtaining the downsize estimation score of the cell node based on the number of worst timing paths of the cell node and the slack value of the worst output pin; arranging the downsize estimation scores of the cell nodes in descending order, selecting the first N cell nodes for downsize processing, and calculating the timing information new_TNS of the netlist; and optimizing the area power consumption in the physical optimization of the integrated circuit according to the timing information new_TNS and the timing information TNS of the entire netlist. The problem of excessive area power consumption in the physical optimization design process under the condition of unchanged timing can be solved.

The application discloses an anti-radiation three-mode redundant latch, and belongs to the field of anti-radiation design of special integrated circuits. The application designs a novel main-stage latch and a novel redundant voting circuit, which comprises a first transistor-stage voting circuit, a second transistor-stage voting circuit and a protection gate circuit. The application reinforces the main-stage latch and the voting circuit from the circuit structure, enhances the resistance of the main-stage latch to SNU and DNU, reduces the influence of SNU of the voting circuit itself on the output result, and enhances the stability of the three-mode redundant system. The total number of MOS tubes of the redundant voting circuit of the application is only 30% of the total number of MOS tubes of the full three-mode redundant voting circuit, effectively reduces the area cost of the three-mode redundant system, and is more suitable for the anti-radiation design of super large scale integrated circuits.

A computer implemented method includes determining a noise adjustment value for a specific subnet of a very large scale integrated (VLSI) circuit. A K factor for the specific subnet is determined based on the noise adjustment value of the specific subnet. The K factor is constant such that a timing of the specific subnet including the K factor is equal to the noise adjustment value of the specific subnet. The K factor for the specific subnet is stored in a design architecture.

The invention provides low-expansion zinc-aluminum-silicon microcrystalline glass and a preparation method thereof, and belongs to the field of electronic ceramic materials. The material is prepared from the following components in percentage by weight: 15 to 25 percent of ZnO, 23 to 25 percent of Al2O3, 37 to 45 percent of SiO2, 10 to 15 percent of B2O3, 0 to 3 percent of MgO and 0 to 5 percent of K2O. The main crystalline phase of the zinc-aluminum-silicon microcrystalline glass provided by the invention is zinc-aluminum spinel ZnAl2O4, and the zinc-aluminum-silicon microcrystalline glass has the thermal expansion coefficient of 4.47-5.28 ppm / DEG C, the bending strength of 130-155 MPa, the Young modulus of 73-83 GPa, the dielectric constant of 5.24-6.91 and the dielectric loss of 2.3-2.9 * 10 <-3 >. The preparation method provided by the invention is low in cost, simple in process, beneficial to industrial production and suitable for a super-large-scale integrated circuit packaging substrate.

The application discloses a kind of molecular dynamics simulation methods of Cu interconnect dielectric material.It is established interconnect dielectric material SiCOH molecular dynamics model using melting-cooling method according to molecular dynamics theory, the feasibility of model is verified using structure and dielectric property, on this basis, the optimal performance combination of interconnect dielectric material is obtained by calculating electric, thermal, mechanical properties and fracture mechanics properties with adjacent interconnect structure, and the result is fed back to adjust to guide material design.The application establishes the simulation model of dielectric material SiCOH performance by molecular dynamics simulation, obtains the optimal performance parameter combination for packaging structure and product, reduces the cost of test and production trial and error, so as to guide the design of high-performance, high-reliability very large scale integrated circuit post-process interconnect material and structure.

The present application relates to a constrained multi-objective evolutionary method based on multi-stage search. Different search strategies are adopted in three stages of the method. In order to make the population quickly cross the large infeasible region and approach the Pareto front, the method does not consider the constraint condition in the first stage, and a convergence index is used to guide the population search; a set of uniformly distributed weight vectors is used to maintain the diversity of the population in the second stage, and an improved epsilon constraint processing strategy is proposed to retain high-quality solutions in the infeasible region; and the constraint priority principle is adopted in the third stage to concentrate the search preference in the feasible region to ensure the feasibility of the final solution set.

The invention relates to a via hole pitch parameter calculation method, computer equipment, a medium and a product. The calculation method comprises the following steps of: obtaining netlist structure information in the design of the super-large-scale integrated circuit, and filtering disconnected parts of a line net and parts where no current passes actually; starting from an input pin of each line network, searching for interconnection lines and via holes in contact with the line network, marking an initial node, recording the position of a contact point, and recursively searching for the associated interconnection lines or via holes until returning to an output pin of the line network; according to the central point positions of the interconnection lines and the via holes and the metal layer where the interconnection lines are located, the relative connection relation between the interconnection lines and the via holes is determined, and a tree-shaped network structure is constructed; constructing a virtual interconnection line; and performing bidirectional traversal on any intermediate node of the tree network structure, traversing all nodes in the path upwards and downwards along the tree network structure, and calculating the sum of the distances among all via hole nodes in the traversal path to obtain the via hole pitch.

This invention discloses a deep learning-based VLSI circuit layout optimization method and system in the field of integrated circuit technology. The method includes the following steps: abstracting a large-scale integrated circuit into a hypergraph structure; receiving the hypergraph structure; generating a node embedding matrix using a hypergraph neural network; optimizing the segmentation loss function through unsupervised training to obtain a probability distribution matrix; determining the segmented subsets based on the probability distribution matrix; mapping each subset to a physical layout unit; generating the physical region layout of the chip according to area balance constraints and timing constraints; providing constraint feedback on the physical layout results; and dynamically adjusting the parameters of the segmentation loss function until all physical constraints are met. This invention can be used for the layout of very large-scale integrated circuits, providing an optimization method and means for providing high-quality VLSI circuit layout solutions.

The invention relates to a local density sensing buffer insertion method, and belongs to the field of super-large-scale integrated circuits. The method comprises the following steps: uniformly dividing a physical design area of a chip into a plurality of rectangular grids, traversing and calculating local layout density values of all the grids, and forming a digital density map; based on the digital density map, high-density areas are identified by adopting a density-based clustering algorithm, and each identified high-density area is marked as a density obstacle; aiming at a target line network, generating an interconnection tree capable of avoiding all density obstacles, and generating a series of buffer insertion candidate points on a path of the interconnection tree; an improved dynamic programming algorithm is adopted, searching is carried out in a candidate point set formed by buffer insertion candidate points, and a final buffer insertion position and type are determined by taking a signal time sequence and local density cost caused by buffer insertion as optimization targets together. According to the method, the whole-process density perception optimization from global planning to local decision is realized.

The invention relates to a fluorine-free diamine monomer containing hydrophobic groups and a preparation method and application thereof, and belongs to the field of novel high-performance polyimide materials. The fluorine-free diamine monomer containing the hydrophobic group has a structure shown in a general formula (I), the fluorine-free diamine monomer containing the hydrophobic group has groups capable of providing a steric effect on ortho-positions R1, R2, R3 and R4 of aniline, and the probability that carbonyl oxygen in polyimide synthesized by the monomer is combined with water molecules can be reduced. The fluorine-free polyimide containing the hydrophobic group prepared from the fluorine-free diamine monomer containing the hydrophobic group has the advantages of low dielectric constant, low loss factor, high thermal stability and excellent solubility, can be used as a high-performance insulating base material, and meets the ultrahigh comprehensive performance requirement of a new generation of high-frequency and high-speed circuits on a polymer substrate; the method is suitable for the fields of super-large-scale integrated circuits, high-frequency high-speed circuit boards, photosensitive polyamideimide and the like

This invention discloses a configurable convolution acceleration device and method supporting shared micro-exponential format data, belonging to the field of neural network hardware acceleration for very large-scale integrated circuits. This acceleration device accelerates convolutional neural networks quantized using a shared micro-exponential data format. The device features a configurable design, supporting the following convolution modes: a kernel size of [value missing], a stride of 2, and zero padding of 1; and a kernel size of [value missing], a stride of 1, and zero padding of 0. The supported input feature map channels and the maximum number of rows and columns supported for these channels are: 32 / 320, 64 / 160, 128 / 80, and 256 / 40. Furthermore, the design method for this configurable convolution acceleration device, supporting new data formats, can also achieve convolution support for different MX quantization formats for input feature map data and weight data by modifying the design parameters.

The application discloses a spectrum sensing hypergraph partitioning method for MFS large-scale signal processing, which is used for partitioning a super large-scale integrated circuit which is comprehensively completed on an MFS platform, and comprises the following steps: hypergraph coarsening based on an LSH algorithm; performing an initialization method with spectrum sensing on the most coarsened hypergraph to obtain an initialization partition; running an FM algorithm with distance weighting on the obtained initialization partition to perform optimization, then desparsing, restoring the coarsened hypergraph to the hypergraph of the previous level, again using the FM algorithm to locally optimize, and alternately performing desparsing and the FM algorithm until the most original hypergraph, and completing the hypergraph partitioning. Compared with a traditional multi-polarized hypergraph partitioning method, the application can perform topology optimization for an MFS system, can process multi-dimensional weights, is helpful to improve the performance of the distributed circuit, and leaves more resource redundancy for subsequent wiring.

Test networks implemented using BEOL and / or MOL devices provide on-chip test probes that enable direct access to selected test points within the circuitry on a VLSI integrated circuit. The test network allows for direct application of inputs to the target test point and direct observation of outputs at the target test point, significantly improving the observability and controllability of the integrated circuit. Multiple test networks can be employed in the integrated circuit to enable independent and / or parallel testing of circuitry and / or functional blocks of the chip. Because the test circuits and networks are implemented using BEOL and / or MOL devices, they can be manufactured on layers of the integrated circuit stacked on top of the main circuitry, thus avoiding a significant increase in the chip's die area.

The application provides a data processing method based on layer information, a plurality of nodes are arranged for storing layer information; the nodes are arranged with levels; the plurality of nodes form a tree structure; the information of the nodes comprises: node name, information of a plurality of layers and layer bounding boxes thereof, basic graphic element quantity, and starting basic graphic element number. The data processing method based on layer information is beneficial to simplifying the checking operation of basic graphic elements in a layout file and further saving computer storage space. The application also provides a data structure generation method, which can generate a data structure file of the data processing method, and has corresponding advantages. The query method is used for checking the connection relationship between basic graphic elements in a layout file, and uses the data structure obtained by the data structure generation method, has corresponding advantages, can greatly improve the checking speed, and is beneficial to further improving the design level of ultra-large scale integrated circuits.

The invention belongs to the technical field of chemical engineering, and particularly relates to a system and a method for preparing electronic-grade hydrogen fluoride by utilizing industrial-grade sodium fluoride. The method comprises the following steps: taking industrial-grade sodium fluoride as a raw material, carrying out double decomposition reaction on the industrial-grade sodium fluoride and 98% industrial-grade concentrated sulfuric acid in a'reaction-filtration-drying 'three-in-one reactor, and generating anhydrous hydrogen fluoride gas and a sodium hydrogen sulfate byproduct under the conditions that the temperature is 200-290 DEG C and the sulfuric acid is excessive; byproducts are filtered by high-pressure nitrogen, and hydrogen fluoride residues are avoided after hot nitrogen is dried, so that the production safety is remarkably improved. The generated hydrogen fluoride gas sequentially passes through a '3A molecular sieve + modified acid-resistant molecular sieve 'synergistic adsorption column to deeply remove water, SO2, CO2 and other impurities (the water content is less than or equal to 5ppm, and the content of SO2 and CO2 is less than or equal to 0.5 ppm), and then passes through a light component removal tower and a heavy component removal tower for two-stage rectification purification to remove H2, N2, O2 / Ar and other light components and heavy component impurities, and finally an electronic-grade hydrogen fluoride product with the purity of 5N-8N (99.999%-99.999999%) is obtained. The method overcomes the defects of scarce raw materials and difficulty in impurity removal of a traditional fluorite method, is compact in equipment, low in leakage risk and controllable in energy consumption and cost, solves the industrial problem of efficient purification of electronic-grade hydrogen fluoride, and is suitable for a wafer processing technology in manufacturing of integrated circuits and super-large-scale integrated circuits.

The invention discloses a layout link tracking efficiency optimization method based on a through hole embedded index, belongs to the field of integrated circuit electronic design automation (EDA), and particularly relates to a data organization and index construction method for layout link tracking. The method comprises the following steps: performing uniform grid division on a layout region, and constructing an R *-tree index structure in a metal layer in each grid; by utilizing the characteristic that the through holes need to be wrapped by upper and lower layers of metal under a process rule, screening and accurately judging metal polygons containing the through holes in the indexes of the upper and lower layers of metal corresponding to the through holes, and establishing an embedded index relationship between the through holes and the metal polygons; on the basis, the link tracking process is based on embedded through hole information, connected metal is positioned in a cross-layer mode, and constant overhead traversal of layout links is achieved; according to the method, the construction frequency of the spatial index structure is reduced, the cross-layer query overhead in the link tracking process is greatly reduced, and the overall efficiency of super-large-scale integrated circuit layout link tracking can be effectively improved.

The present application belongs to the technical field of electronic design automation physical design in integrated circuits, and relates to a chip-oriented global routing method based on directed acyclic graph and congestion awareness, which can be used for global routing in chip physical design. The present application innovatively introduces a wire mesh routing sequence strategy based on internal pin density and average congestion density, dynamically gives the most difficult-to-route wire mesh the highest routing priority by scientifically quantifying the internal topology of the wire mesh and the congestion degree of the external environment; a dynamic via punishment mechanism with congestion awareness is proposed, which can obtain the congestion gradient of the underlying grid in real time, and intelligently apply nonlinear vertical layer transition resistance in the congestion hotspot area; an enhanced directed acyclic graph mode routing space is constructed in the underlying engine, and combined with a node cost fast updating algorithm based on dynamic programming, the iteration number of wire breaking and rerouting is reduced, and the time overhead of the super large scale integrated circuit routing link is saved.

The embodiment of the invention provides a lightweight multi-mode super-large scale integrated circuit wiring congestion prediction method, and the method comprises the steps: extracting geometric features which are strongly related to congestion from a layout, and carrying out the splicing of the geometric features in a channel dimension, and forming a multi-channel feature map; inputting the multi-channel feature map to a CNN branch; determining a feature value corresponding to grid on the feature map as a feature vector of a Gcell node, and obtaining output of a GNN branch; obtaining a congestion prediction map through a fusion result; on the basis of a heterogeneous graph compression strategy of a sliding window, key topological information is reserved while a graph structure is simplified; a Cross-pitch self-adaptive fusion mechanism is adopted, and on-demand interaction of multi-modal features is realized through a small number of learnable weights; the composite loss functions of MSE, MS-SSIM and Diff are fused, and the global and local quality of the congestion graph is considered; and through a lightweight architecture, adaptive fusion and multi-dimensional optimization.