16 results about "Under bump metallurgy" patented technology

A method comprises the following steps. A photoresist composition is applied over an under bump metallurgy (UBM) layer to form a photoresist layer. The photoresist composition comprises a polymer, a crosslinker and a photo initiator. The photo initiator is a floating photo initiator. The photo initiator has a first concentration in a top portion of the photoresist layer and a second concentration in a bottom portion of the photoresist layer. The first concentration is greater than the second concentration. The photoresist layer is exposed. The photoresist layer is developed using a developer. A conductive layer is formed over the UBM layer. After forming the conductive layer over the UBM layer, the photoresist layer is removed.

A SAW filter package and a method for manufacturing same are provided. A surface acoustic wave (SAW) filter package comprises: a first substrate on which a SAW filter is formed; an electrode pad layer formed on the first substrate; an under bump metallurgy (UBM) layer formed on the electrode pad; a second substrate; and a metal bump electrically connecting the first substrate and the second substrate to each other, wherein the UBM layer includes an aluminum-copper alloy, and the metal bump includes a gold-palladium alloy.

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

A semiconductor package includes a redistribution substrate having first and second surfaces, and an insulating member and a plurality of redistribution layers on different levels in the insulating member and electrically connected together; a plurality of under bump metallurgy (UBM) pads in the insulating member and connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the first surface, the UBM pads having a lower surface exposed to the first surface of the redistribution substrate; a dummy pattern between the UBM pads in the insulating member, the dummy pattern having a lower surface located at a level higher than the lower surface of the UBM pads; and at least one semiconductor chip on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the second surface.

The present invention provides a semiconductor package having electrodes and a method for forming the same. [Solution] The semiconductor package includes a wiring structure 21, which includes a first insulating layer 23, a conductive pad 48 on the first insulating layer, a second insulating layer 25 on the conductive pad, through holes that penetrate the second insulating layer and are superimposed on the conductive pad, a protruding pattern 57 placed on the conductive pad within the through holes, and a UBM (Under Bump Metallurgy) layer 63 that contacts the upper and side surfaces of the protruding pattern and is connected to the conductive pad. A semiconductor chip 90 connected to the UBM layer is placed on the wiring structure.

A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.

A substrate body is provided.SOLUTION: A substrate body according to the present invention includes a substrate, a plurality of under bump metallurgy layers (UBMs), and a plurality of tapered microbumps. The protective layer of the substrate has a hole, and a pad is exposed from the hole. The recess of each UBM is provided in the hole and is electrically connected to the pad. A root portion of each of the tapered micro-bumps is located in the recess, and a contact portion of each of the tapered micro-bumps protrudes into the recess. Each of the tapered micro-bumps includes an insulating tapered portion, a conductive layer, and a bonding layer. The conductive layer covers the insulating tapered portion and is electrically connected to the UBM. The bonding layer covers the conductive layer and is electrically connected to the conductive layer. A maximum outer diameter of each of the tapered micro-bumps is less than or equal to 20 μm.SELECTED DRAWING: Figure 10

A package structure is provided. The package structure includes a redistribution structure. The redistribution structure includes a first conductive pad, a second conductive pad adjacent to the first conductive pad, a first conductive via connected to the first conductive pad, and a second conductive via connected to the second conductive pad. The package structure further includes a first under bump metallurgy structure connected to the first conductive via, a second under bump metallurgy structure connected to the second conductive via, and a substrate electrically connected to the redistribution structure through the first under bump metallurgy structure and a second under bump metallurgy structure. A first distance between the first and second conductive pads is less than a second distance between the first and second under bump metallurgy structures. The second distance is less than a third distance between the first and second conductive vias.

Provided is a method of manufacturing a semiconductor package, the method including: forming a bonding layer on a carrier, forming a redistribution substrate on the bonding layer, mounting a plurality of semiconductor chips on the redistribution substrate, forming a package structure for a plurality of semiconductor packages; bonding an ultraviolet (UV)-curable adhesive sheet to a surface of the package structure opposite the bonding layer and redistribution substrate; separating or removing the carrier and the bonding layer from the package structure; forming an under bump metallurgy (UBM) layer and forming an external connection conductor on the redistribution substrate; cutting the package structure into the plurality of semiconductor packages; irradiating the UV-curable adhesive sheet with UV rays, after cutting the plurality of semiconductor packages; and separating the plurality of semiconductor packages from the UV-curable adhesive sheet.

A method of manufacturing a semiconductor package includes forming a first redistribution structure comprising a first redistribution layer and a first insulating layer, and first under bump metallurgy (UBM) structures spaced apart from the first redistribution layer, forming first conductive posts on the first redistribution structure, forming a first encapsulant on the first redistribution structure, forming a second redistribution structure, comprising a second redistribution layer and a second insulating layer, on the first encapsulant and the first conductive posts, forming first semiconductor chips on the second redistribution structure and forming second semiconductor chips on the first semiconductor chips, and forming first bumps on the first UBM structures. The first UBM structures overlap the first conductive posts in a first direction perpendicular with an upper surface of the first redistribution structure.

In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.

A semiconductor package includes a wiring structure. The wiring structure includes a first insulating layer, a conductive pad on the first insulating layer, a second insulating layer on the conductive pad, a through hole passing through the second insulating layer and overlapping with the conductive pad, a protruding pattern disposed on the conductive pad and located in the through hole, and an under bump metallurgy (UBM) layer that contacts the upper surface and side surface of the protruding pattern and is connected to the conductive pad. A semiconductor chip connected to the UBM layer and disposed on the wiring structure.

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

Provided are a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate, an under bump metallurgy (UBM) structure, and a solder. The UBM structure is disposed over the substrate. The UBM structure includes a first metal layer; a second metal layer disposed on the first metal layer; and a third metal layer disposed on the second metal layer. A sidewall of the first metal layer is substantially aligned with a sidewall of the second metal layer, and a sidewall of the third metal layer is laterally offset inwardly from the sidewalls of the first and second metal layers. The solder is disposed on the third metal layer.

A semiconductor package includes: a package substrate including first and second sides that are opposite to each other, and including an insulating member and a plurality of redistribution layers; a semiconductor chip disposed on the first side and including a plurality of contact pads that are connected to a first redistribution layer of the plurality of redistribution layers; a protective layer disposed on the second side and exposing a portion of a second redistribution layer of the plurality of redistribution layers; a plurality of under bump metallurgy (UBM) pads disposed on the second side and connected to the exposed portion of the second redistribution layer; a dummy pattern formed on the protective layer; an insulating pattern covering the dummy pattern; and a passive element disposed on the insulating pattern and a first set of UBM pads of the plurality of UBM pads.

A semiconductor package includes a semiconductor chip having chip pads on a horizontal first surface thereof; a redistribution wiring layer covering the first surface, and including redistribution wirings provided on at least one insulating layer and electrically connected to the chip pads, a protective layer on the at least one insulating layer covering the redistribution wirings and including a first cover portion having a first opening exposing a portion of a first redistribution wiring and a second cover portion covering second and third redistribution wirings adjacent to each other, and an under bump metallurgy (UBM) pad provided on the portion of the first redistribution wiring exposed by the first opening; and conductive bumps disposed on the UBM pads of the redistribution wiring layer. The first cover portion has a first vertical thickness, and the second cover portion may have a second vertical thickness less than the first thickness.