Semiconductor chip and manufacturing method thereof

Abstract

The invention discloses a semiconductor chip and a manufacturing method thereof, wherein the semiconductor chip compirses a conductive bump on a semiconductor chip. A substrate is provided. A bond pad is over the substrate. An under bump metallurgy (UBM) layer is over the bond pad. A copper pillar is over the UBM layer. The copper pillar has a top surface with a first width and sidewalls with a concave shape. A nickel layer having a top surface and a bottom surface is over the top surface of the copper pillar. The bottom surface of the nickel layer has a second width. A ratio of the second width to the first width is between about 0.93 to about 1.07. A solder material is over the top surface of the cap layer. The semiconductor chip and the manufacturing method thereof can reduce crack of the boundary between the conducting column and the soldering flux caused by stress.

Description

technical field [0001] The invention relates to a semiconductor packaging process, in particular to a structure of a conductive bump in a flip-chip package and a manufacturing method thereof. Background technique [0002] Flip-chip technology plays an integral role in semiconductor device packaging. Flip-chip MEMS assembly involves using solder bumps as interconnects to directly electrically connect face-down electronic components to a substrate (such as a circuit board). Because flip chip packaging has advantages in size, performance, and design flexibility compared to other packaging methods, the utilization rate of flip chip packaging has grown significantly. [0003] Recently, copper pillar technology has been developed. Electronic components use copper pillars instead of solder bumps to connect electronic components and substrates. Copper pillar technology minimizes the chance of bump bridging, reduces capacitive loading on circuits, and enables electronic components...

AI Technical Summary

Problems solved by technology

However, the UBM layer may be eroded laterally during the etching process, resulting in an undercut of the UBM layer.

Undercutting of the UBM layer can cause stress during the solder bumping process

Such stress may cause cracking of the low-k dielectric layer in the underlying substrate

In the copper pillar process, the stress may crack along the interface between the copper pillar and the solder used to connect the electronic components, as well as along the undercut and the interface between the copper pillars, which may cause high leakage current and serious Affect reliability

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