457 results about "Flip chip" patented technology

The invention discloses an intelligent sealing test method and system for a wafer in a semiconductor chip, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: initializing a magneto-electric field cooperation parameter, optimizing the magneto-electric field cooperation parameter through a multi-target genetic algorithm, and driving core-shell nanoparticles to carry out the metallization filling of a high-precision through hole wafer, generating a wafer with a metalized through hole structure; based on the metalized through hole structure wafer, bonding parameters are generated through a laser Doppler frequency vibration spectrum analysis method, flip interconnection is achieved through a thermal ultrasonic virtual process, and a low-defect bonding wafer is generated; a finite element inversion algorithm is adopted, a stress distribution map of a bonding interface is established, an anti-thermal-stress packaging layer is constructed through an intelligent stress matching algorithm, and the low-defect bonding wafer is packaged; and through a multi-target genetic algorithm, magnetoelectric field cooperation parameters are optimized, core-shell nano-particles are driven to directionally deposit, and accurate control over the metallization filling process is achieved.

The invention relates to the technical field of semiconductor packaging, and provides a semiconductor packaging process which comprises the following steps: obtaining a circuit board, and preprocessing the circuit board; performing SMT assembly operation on the bottom surface of the circuit board; silk-screening solder paste on the top surface of the circuit board; a tin cap of the flip chip is dipped with a soldering flux; mounting a flip chip and other elements on the top surface of the circuit board; performing reflow soldering operation on the top surface of the circuit board; according to the semiconductor packaging process provided by the embodiment of the invention, the tin cap of the flip chip can be dipped with the soldering flux before confluence welding operation is carried out on the flip chip, so that in the reflow soldering process, the soldering flux can effectively protect the tin cap and a PCB bonding pad and prevent oxidation, the collapsed tin cap can recover the original state of the tin cap to the greatest extent during reflow soldering, and the reliability of the flip chip is improved. The tin cap can be in contact with the PCB bonding pad more effectively, good welding is formed, the wettability is improved, oxidation is reduced, the welding strength is enhanced, and the problems of pseudo soldering, open circuit and the like are reduced.

The invention relates to the technical field of signal processing, and discloses a flip chip vibration signal denoising method and system, and the method comprises the steps: obtaining a vibration signal responded by a to-be-detected flip chip under the action of external ultrasonic excitation, carrying out the segmentation processing of the vibration signal, constructing an initial sparse dictionary according to the segmented vibration signal, and iteratively updating the sparse dictionary; in the iteration updating process, sparseness parameters are adjusted in real time along with the number of iterations, and soft threshold denoising is conducted on residual terms; introducing a feature projection matrix to perform joint modeling on each section of vibration signal, and constructing a joint optimization model according to the updated sparse dictionary and the corresponding sparse coefficient; alternately optimizing the sparse coefficient and the feature projection matrix in the joint optimization model to obtain an optimal solution of the sparse coefficient; and combining the updated sparse dictionary and the optimal solution of the sparse coefficient to reconstruct the vibration signal to obtain a denoised vibration signal. According to the method, transient features can be effectively extracted, expression of key features is enhanced, noise is suppressed, and denoising robustness and reconstruction precision are improved.

The invention relates to a method for predicting the thermal stress of a flip-chip bonding micro-welding spot interconnection structure, which comprises the following steps of: performing a flip-chip bonding test on an electronic device based on a reflow soldering process, establishing a three-dimensional geometric model, and calculating the thermal stress of the micro-welding spot interconnection structure based on the change of the interconnection structure between the micro-welding spot and a Ni-P / Cu bonding pad in the flip-chip bonding process of the electronic device. Coupling the material attributes of the chip, the substrate, the micro-solder joint and the Ni-P / Cu bonding pad in the flip-chip bonding test to obtain an equivalent finite element model, and simulating corresponding flip-chip bonding based on a birth-death element method in the equivalent finite element model; and finally, calculating and identifying the maximum equivalent thermal stress distribution rule at the interface of the micro welding spot layer, the intermetallic compound layer and the bonding pad by using the equivalent finite element model, namely predicting the thermal stress of the flip-chip micro welding spot interconnection structure. Theoretical support is provided for improving the reliability of the flip-chip bonding micro-welding spot interconnection structure, and a theoretical foundation is laid for thermal stress regulation and control.

The embodiment of the invention provides a flip chip offset measurement system and method, the measurement system comprises a first light source and a second light source which are different in emergent light beam wavelength, an imaging assembly and a processing assembly, and the first light source is controlled to emit a first light beam which penetrates through a flip chip and irradiates a first target in a deep layer; obtaining a first image containing the first target from the first detector; controlling a second light source to emit a second light beam to irradiate a second target on the surface of the flip chip, acquiring a second image containing the second target from a second detector, and finally acquiring a first offset and a second offset of the flip chip relative to the substrate based on the first image and the second image by a processing assembly, and obtaining the bonding offset of the flip chip according to the first offset and the second offset. According to the invention, the dual-wavelength light source is adopted to cooperatively irradiate the flip chip in a time-sharing / wave-band-sharing manner, so that the penetrability-reflectivity contradiction of single-wavelength detection is broken through, and the accuracy and reliability of lamination offset detection are improved.

The invention provides an underfill adhesive capable of controlling adhesive width, a preparation method of the underfill adhesive and a flip chip, and the underfill adhesive comprises the following components in percentage by mass: 60%-67% of an inorganic filler, 17%-21% of epoxy resin, 15%-20% of an amine curing agent, 0.05%-0.3% of hydrophobic modified fumed silica, 0.1%-0.3% of an amine accelerator and 0.1%-0.2% of carbon black. According to the invention, through a specific formula proportion and control of the addition amount of the hydrophobic modified fumed silica, the control of the hydrophobic degree of the bottom filling glue solution is realized, so that the control of the glue width in the dispensing process is realized, and the reliability and the manufacturing yield of chip packaging are improved.

The invention relates to the field of semiconductor packaging stress testing, and discloses a mounting method for a micro-size packaging type strain gauge, which comprises the following steps of: placing a sample to be tested in a bearing clamp, fixing the sample to be tested, then loading the sample to be tested into a bearing base of high-precision inverted mounting equipment, fixing the bearing clamp, and starting vacuum adsorption; putting a strain gauge adhesive into an adhesive dipping disc and scraping the adhesive; the customized suction head sucks the strain gauges and moves the strain gauges to the position above the glue dipping disc to be dipped in the bonding glue; the strain gauge pattern coincides with the to-be-pasted position of the product, and the customized suction head pastes the strain gauge to the to-be-detected position of the product; the customized suction head exerts pressure downwards as a whole, and the strain gauge is further flattened in a hot pressing mode; and putting the processed sample to be detected together with the strain gauge into an air pressure drying oven for pressurizing and curing. According to the invention, the flatness of the micro-sized packaged strain gauge after surface mounting and curing is greatly improved, and the precision and stability of subsequent stress testing are further improved.

The present invention refers to a hybrid integrated silicon drift detector (HiSDD) for X-ray detection, particularly to a HiSDD combining a silicon drift detector (SDD) with a low-noise preamplifier on a SDD sensor chip to improve the electrical and structural properties of the detector assembly. The invention further refers to a corresponding method for the fabrication of a HiSDD. A HiSDD according to the invention hybridly integrates a silicon drift detector, SDD, sensor chip and a preamplifier module; wherein electrically conductive paths are formed on a surface of the SDD sensor chip, having first ends configured for flip chip bonding and second ends configured for wire bonding; wherein the preamplifier module having contacts disposed on a surface of the preamplifier module, and wherein the first ends of the electrically conductive paths are flip chip bonded to the contacts of the preamplifier module.

The invention provides an on-chip integrated laser light source and an optical coupling integration method thereof.The on-chip integrated laser light source comprises a silicon optical substrate and a light source chip assembly integrated on the silicon optical substrate, and the silicon optical substrate comprises an optical signal transmission waveguide; the light source chip assembly comprises a surface-emitting distributed feedback laser chip so as to generate laser beams emitted in the direction perpendicular to the surface of the chip. The on-chip integrated laser light source further comprises a grating coupling structure arranged between the surface emission distributed feedback laser chip and the optical signal transmission waveguide. The light-emitting surface of the surface-emitting distributed feedback laser chip is arranged towards the silicon light substrate, and a laser beam generated by the surface-emitting distributed feedback laser chip is directly projected and coupled into the light signal transmission waveguide through the grating coupling structure; the surface-emitting distributed feedback laser chip is fixedly combined on the silicon optical substrate through a flip chip technology, so that the high-precision end face alignment requirement of the heterogeneous integrated waveguide is converted into high-efficiency grating coupling based on a surface light emitting mode. In this way, harsh end face coupling is converted into efficient grating coupling.

The present disclosure provides a package structure having a photonic integrated circuit, the package structure includes a substrate, a chip and an optical module. The chip has an optical waveguide structure and a recessed portion. The optical waveguide structure is adjacent to the recessed portion. The recessed portion faces the substrate, and the chip is engaged to the substrate by flip chip. The optical module is provided in the recessed portion of the chip.

The invention discloses a flip chip bottom filling adhesive and a preparation method and application thereof, and belongs to the technical field of chip packaging. The bottom filling adhesive for the flip chip is prepared from the following components in percentage by mass: 48 to 52 weight percent of bisphenol F type epoxy resin, 18 to 22 weight percent of curing agent, 3 to 9 weight percent of toughening agent, 8 to 16 weight percent of aluminum nitride, 4 to 8 weight percent of nano silicon dioxide, 4 to 8 weight percent of boron nitride, 0.5 to 1 weight percent of thixotropic agent and 1.0 to 1.5 weight percent of latent accelerant. Bisphenol F type epoxy resin is used as a matrix and is matched with a rapid curing agent and a toughening agent, and high-thermal-conductivity aluminum nitride, nano silicon dioxide and flaky boron nitride are added to form a synergistic system, so that medium-low-temperature rapid curing, high toughness, low thermal stress and excellent thermal conductivity are realized. According to the preparation method disclosed by the invention, the product has high thermal conductivity, low stress and excellent dimensional stability while the medium and low temperature rapid curing is ensured.

A light emitting device includes a substrate including a roughened surface; a light emitter disposed on the substrate, which includes a first conductivity layer; and a mesa disposed on a partial region of the first conductivity layer. An ohmic electrode can be disposed on the mesa; and a contact electrode can be disposed on the first conductivity layer. The light emitting device further includes a first reflection layer; a first pad electrode and a second pad electrode; and a second reflection layer. The first reflection layer covers at least a portion of the light emitter, the ohmic electrode and the contact electrode. The second reflection layer is disposed on an opposite side of the substrate.

The present invention discloses a gold-silver alloy bump for replacing a pure gold bump in flip-chip packaging and a preparation method thereof, belonging to the technical field of electroplating gold-silver alloys. The gold-silver alloy bump is composed of two layers of gold-silver alloy layers, namely a connection layer and a protective layer; the content of gold in the connection layer is 20-50 wt%; the thickness of the protective layer is much smaller than that of the connection layer, and the content of gold is above 60 wt%; the average grain size of the grains in the gold-silver alloy layer is 0.10-0.30 μm. The gold-silver alloy bump provided by the present invention has hardness, roughness and anti-sulfuration performance comparable to those of a pure gold bump, can meet the technical requirements of flip-chip packaging, and can greatly reduce costs at the same time. The method for the gold-silver alloy bump provided by the present invention can obtain the double-layer gold-silver alloy bump of the present invention by only changing the current density through the same equipment and plating solution, simplifies the preparation process, improves the production efficiency, and reduces the production cost.

1. The name of the design product: X-ray detection equipment (AX8500). 2. The use of the design product: The design product is used for the detection of BGA, CSP, flip chip detection, semiconductors, packaged components, electronic connector module detection, ceramic products, aviation components, photovoltaic industry, battery industry and other special industries on large circuit boards. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: perspective view.

The present application provides a flip chip light emitting diode and a manufacturing method thereof. The flip chip light emitting diode comprises a transparent substrate, an epitaxial composite layer, a first conductive type electrode pad, a second conductive type electrode pad and a wafer bonding composite layer. The epitaxial composite layer is disposed on the transparent substrate. The first conductive type electrode pad is disposed on the transparent substrate and electrically connected to the epitaxial composite layer. The second conductive type electrode pad is disposed on the epitaxial composite layer and electrically connected to the epitaxial composite layer, and is located on the same horizontal plane as the first conductive type electrode pad on the same side of the transparent substrate. The wafer bonding composite layer comprises at least one titanium dioxide (TiO2) layer and at least one silicon dioxide (SiO2) layer, and is interposed between the epitaxial composite layer and the transparent substrate.

A power amplifier includes a substrate, first and second transistor amplifiers, and at least one matching circuit. Respective output terminals of the first and second transistor amplifiers are coupled to a combining node, and the matching circuit includes one or more passive electrical components coupled between one of the respective output terminals and the combining node. At least one of the first and second transistor amplifiers or the one or more passive electrical components is mounted on the substrate in a flip chip configuration. The matching circuit may include a shunt inductance that is coupled to the one of the respective drain terminals by a conductive bump. Related devices are also discussed.

A solid state drive (SSD) device includes a substrate, a first buffer chip disposed on the substrate, a second buffer chip disposed on the first buffer chip, a plurality of first non-volatile memory chips connected to the second buffer chip through wire bonding, a controller configured to send a control signal to the plurality of first non-volatile memory chips through a first channel, and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through first wires.

Flip chip LEDs comprise a transparent carrier and an active material layer such as AlInGaP bonded to the carrier and that emits light between about 550 to 650 nm. The flip chip LED has a first electrical terminal in contact with a first region of the active material layer, and a second electrical terminal in contact with a second region of the active material layer, wherein the first and second electrical terminals are positioned along a common surface of the active material layer. Chip-on-board LED packages comprise a plurality of the flip chip LEDs with respective first and second electrical terminals interconnected with one another. The package may include Flip chip LEDs that emit light between 420 to 500 nm, and the flip chip LEDs are covered with a phosphorus material comprising a yellow constituent, and may comprise a transparent material disposed over the phosphorus material.

The invention discloses an ultrasonic nondestructive testing system and method for defects of a flip-chip. The ultrasonic nondestructive testing system comprises an upper computer, a pulse transceiver, an acquisition card, an ultrasonic sensor, a displacement platform, a three-dimensional motion platform and a motion controller, the upper computer serves as a control platform and is responsible for control instruction issuing and data processing. The pulse transceiver, the acquisition card and the high-frequency ultrasonic sensor form a signal acquisition and transmission platform which is responsible for transmitting, receiving, transmitting and analog-to-digital conversion of ultrasonic signals; the displacement platform is used for fixing the flip-chip bonding chip; the three-dimensional motion platform and the motion controller form a three-dimensional motion control system, and the three-dimensional motion control system is responsible for carrying an ultrasonic sensor to execute scanning at different spatial positions. The chip is integrally detected, welding spots do not need to be detected one by one, and the defect detection efficiency can be greatly improved.

A micromechanical component for a sound transducer device. The micromechanical component includes a substrate, a diaphragm, at least one piezoelectric element, and at least one electrical contact connection. The diaphragm can vibrate and is connected to the substrate. The at least one piezoelectric element is disposed between the diaphragm and the substrate and is connected to the diaphragm. The at least one piezoelectric element is designed to produce and / or detect vibrations of the diaphragm in the ultrasonic range. The at least one electrical contact connection is electrically connected to the at least one piezoelectric element. The micromechanical component can be connected, using flip chip technology, to a control circuit such that the at least one piezoelectric element can be electrically connected to the control circuit by means of the at least one electrical contact connection.

The invention provides a high-yield low-capacitance TVS (Transient Voltage Suppressor) diode packaging process, which comprises the following steps: S1, back metallization: a sputtering table is adopted, the thickness of Ti / Ni / Ag is 50 / 200 / 800nm, and the back temperature is lt; the contact resistance is less than or equal to 0.05 m omega.mm < 2 > and the resistance is gt; 0.08, sputtering again; s2, wafer thinning and stress release are carried out; s3, front passivation / low-k dielectric layer preparation; s4, preparing an aluminum-copper bump; s5, performing laser scribing; s6, inversely mounting a patch; s7, performing vacuum reflow soldering; s8, plasma cleaning and plasma underfilling are carried out; and S9, laser marking is carried out. According to the process, five contradictions of'extreme low capacitance, extreme yield, low temperature drift, zero cavity and green manufacturing 'are simultaneously grounded in the same package, so that the TVS device really meets the dual requirements of a 40Gbps high-speed interface and a vehicle gauge for the first time.

A fan-out wafer-level packaging (FOWLP) unit including a substrate, at least one first die, a first dielectric layer, a plurality of first conductive circuits, a second dielectric layer, a plurality of second conductive circuits, and at least one second die is provided. A range perpendicular to a second surface of the first die is defined as a chip area. The second dielectric layer is provided with a plurality of second slots allowing the second conductive circuit to expose and form bonding pads. The bonding pads located around the chip area are first bonding pads. The second die is disposed over the second dielectric layer by flip chip and electrically connected to the first die which is electrically connected with the outside by the first bonding pads. Thereby problems of conventional FOWLP generated during manufacturing of the conductive circuits including higher manufacturing cost and less environmental benefit can be solved.

A light emitting diode (LED) structure that includes a stent substrate; and a circuit having a plurality of contact pads arranged along a length of the stent substrate. The structure further includes a plurality of light emitting diode (LED) chips, wherein each light emitting diode chip in the plurality of chips is engaged to a set of contact pads along the length of the metal stent substrate. A continuous phosphor layer is present overlying the plurality of light emitting diode (LED) chips, the continuous phosphor layer including first portions that are in direct contact with at least a light transmission surface of the light emitting diode (LED) chips and second portions that bridge across the space separating adjacently positioned light emitting diode. An encapsulant present over the continuous phosphor layer that is covering at least the light emitting diode chips.

The invention relates to an integrated LED device based on a flip-chip process, which comprises a driving chip substrate with a driving circuit on the top surface, an RGB LED chip group is welded on the top surface of the driving chip substrate in a flip-chip manner, and an elastic reinforcing piece is arranged around the flip-chip welding position of the RGB LED chip group; the driving chip substrate, the RGB LED chip set and the elastic reinforcing piece are packaged in the packaging colloid layer, the bottom surface of the driving chip substrate is exposed out of the packaging colloid layer, and the expansion coefficient of the elastic reinforcing piece is smaller than that of the packaging colloid layer; the RGB LED chip set is connected with a heat dissipation piece which is of an inverted-L-shaped structure, arranged in the elastic reinforcing piece and the packaging colloid layer in a penetrating mode and vertically extends downwards to the bottom face of the packaging colloid layer. And a plurality of connecting ends are arranged on the bottom surface of the driving chip substrate. According to the invention, the size of the device is reduced, and the heat dissipation capability and the mechanical stress resistance of the device are improved.

The invention discloses a manufacturing method of an electromagnetic shielding structure for board-level plastic package of a vertical structure chip and a flip chip, which comprises the following steps of: firstly, manufacturing a bottom interconnection line layer, a bottom bonding pad and an external grounding point at the bottom end of a partition box dam of a shielding cover structure according to design requirement parameters, and then manufacturing the partition box dam and a copper column for realizing vertical interconnection; after the plastic package chip is fixedly mounted, a vertical interconnection line and a top metal layer of a shielding cover structure are sequentially manufactured layer by layer; when the carrier is separated, a layer of copper foil is reserved for manufacturing an outer circuit layer and an outer bonding pad, and finally cutting is carried out to obtain a single packaged finished product; a top metal layer, a partition box dam, vertically interconnected copper columns, interconnection line layers at all levels, bonding pads and grounding points are directly processed and manufactured by using a substrate wet process such as laser drilling, copper deposition, electroplating and pattern transfer in the prior art, so that the space occupation area can be reduced, the process is simplified, the space utilization rate is improved, and the cost input is reduced; and the stability and reliability of the product are ensured.

The invention relates to the technical field of flip chips, and provides a semiconductor level flip chip surface mounting technology production process, which comprises the following steps: obtaining a circuit board and a flip chip; first solder paste is printed on the circuit board, and the flip chip is pasted to the first solder paste of the circuit board; welding the flip chip to the circuit board through a reflow soldering process; filling the bottom of the flip chip; according to the semiconductor-level flip chip surface mounting technology production process provided by the embodiment of the invention, the flip chip is welded to the circuit board, so that the flip chip has higher connection density and better electrical performance, and the bottom of the flip chip is filled, so that the filler can enhance the mechanical bonding force between the flip chip and the circuit board, thereby improving the reliability of the flip chip. The probability that the flip chip falls off from the circuit board or the welding point is loosened due to external force or temperature change can be effectively reduced.

The utility model discloses a packaging structure for chips of 2nm and below based on metal band connection, which comprises a substrate, an adapter plate and a first flip chip, and the thickness of the first chip is not more than 2nm. The adapter plate is arranged on the substrate, the first chip is inversely arranged on the adapter plate, and a metal contact is arranged on the back face of the first chip. The substrate is correspondingly provided with a wafer back power supply metal contact, and the wafer back power supply metal contact and the substrate are conductively connected through the first and second conductive material layers and an integrally formed metal belt. The metal belt comprises vertical and transverse extension structures, and forms a conductive network for power supply of the crystal back, so that the heat conduction capability is improved. The structure realizes high integration, reduces the packaging height and the physical size, and improves the power supply efficiency and the energy utilization efficiency at the same time. The flip chip cooperates with the conductive network to realize wafer back power supply, thereby shortening the power supply path and reducing the resistance. The integrally formed metal belt design simplifies the assembly process, reduces the welding and connecting steps, and improves the production efficiency. The packaging structure is suitable for chips of 2nm and below, and has a wide application prospect.

The utility model discloses an embodiment of backlight module and display module, this backlight module includes backboard, light guide plate, lamp plate and electronic component, and backboard includes bottom plate and side plate, and bottom plate and side plate form accommodating space, light guide plate is located bottom plate one side in accommodating space, and lamp plate is located light guide plate far from bottom plate one side, and lamp plate is fixedly connected with light guide plate, and lamp plate is provided with luminous element to light guide plate one side, and electronic component sets up on lamp plate, the technical scheme provided by the utility model embodiment, through with the integral design of lamp strip and circuit board as lamp plate, thereby save the connector for connecting lamp strip and circuit board, and through with lamp plate and light guide plate assembly together, and make lamp plate flip chip in light guide plate's light -admitting side, make backboard not use again make for the lug of bearing circuit board, and lamp plate also need not use screw lock on the lug of backboard, be favorable to simplifying backplate, save assembly work hours.

The utility model relates to a transparent device with a built-in integrated circuit (IC), which comprises an insulated transparent substrate, a driving IC packaged on the front surface of the transparent substrate through an insulated transparent adhesive layer, a transparent conductive circuit electrically connected to the driving IC, and a transparent light-emitting diode (LED) flip chip with three primary colors of red, green and blue (RGB), the conductive circuit comprises a connecting end which is exposed outside the insulating transparent adhesive layer and is connected with a pin of the driving IC and an internal conductive circuit which is packaged in the insulating transparent adhesive layer, and the LED flip chip is electrically connected with the driving IC through the internal conductive circuit. The utility model has the advantages of compact structure, small volume, light weight and the like, and can be used for better manufacturing the transparent display screen.

The invention provides a flip chip airtight packaging method and a packaged chip, and relates to the technical field of semiconductor packaging. Comprising the steps that a preset number of half grooves are etched in the top face of a silicon-based adapter plate through a dry etching method, the preset number is the number of chips needing to be packaged, and each half groove comprises a plurality of silicon columns corresponding to chip function points or grounding points of the corresponding chips; solder is evaporated on the periphery of each half groove and the top end of each silicon column, and an annular gold layer is electroplated on the periphery of each chip needing to be packaged; and setting preset hot pressing process parameters, mounting each chip needing to be packaged on the corresponding half groove in an inverted manner by adopting a hot pressing process, and carrying out plastic packaging by utilizing a plastic packaging material. According to the invention, the air tightness requirement can be improved while the size of the packaged chip is reduced.