766 results about "Flip chip" patented technology

The invention provides a packaging test method of an LED flip chip and related equipment. The method comprises the following steps: acquiring wafer packaging parameters of the LED flip chip; determining a warping degree prediction model of wafer packaging parameters and a process parameter sensitivity sequence through multi-physics field coupling modeling; monitoring a warpage measurement distribution diagram of the wafer according to the warpage prediction model; determining wafer warpage compensation data according to the process parameter sensitivity sequence and the warpage measurement distribution diagram; comparing a three-dimensional deformation graph correspondingly generated by the wafer warping degree compensation data with a prediction result of the warping degree prediction model, and determining a comparison result; and performing welding spot defect high-resolution scanning on the wafer of the LED flip chip according to the comparison result, and identifying the welding spot defect of wafer packaging. Through the implementation of the scheme of the invention, accurate prediction, effective compensation and reliable detection of wafer buckling deformation in the packaging process of the LED flip chip can be realized, and the packaging quality is remarkably improved.

The invention discloses an intelligent sealing test method and system for a wafer in a semiconductor chip, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: initializing a magneto-electric field cooperation parameter, optimizing the magneto-electric field cooperation parameter through a multi-target genetic algorithm, and driving core-shell nanoparticles to carry out the metallization filling of a high-precision through hole wafer, generating a wafer with a metalized through hole structure; based on the metalized through hole structure wafer, bonding parameters are generated through a laser Doppler frequency vibration spectrum analysis method, flip interconnection is achieved through a thermal ultrasonic virtual process, and a low-defect bonding wafer is generated; a finite element inversion algorithm is adopted, a stress distribution map of a bonding interface is established, an anti-thermal-stress packaging layer is constructed through an intelligent stress matching algorithm, and the low-defect bonding wafer is packaged; and through a multi-target genetic algorithm, magnetoelectric field cooperation parameters are optimized, core-shell nano-particles are driven to directionally deposit, and accurate control over the metallization filling process is achieved.

The invention provides a low-warpage underfill adhesive for FC-BGA packaging, a preparation method thereof and a flip chip. The underfill adhesive comprises the following components in percentage by mass: 50%-60% of silicon dioxide, 24%-29% of epoxy resin, 16%-20% of a curing agent, 0.1%-0.2% of carbon black and 0.1%-0.2% of an accelerant. Wherein the epoxy resin is composed of high-purity bisphenol A epoxy resin, polyurethane modified epoxy resin and phenolic aldehyde modified epoxy resin. By adjusting the proportion of the high-purity bisphenol A epoxy resin, the polyurethane modified epoxy resin and the phenolic aldehyde modified epoxy resin and combining the curing agent and the accelerant, the stress of the underfill adhesive is integrally reduced, and the underfill adhesive with good fluidity and low warpage is obtained; therefore, the packaging yield and the packaging efficiency of chip packaging are improved.

The invention discloses a semiconductor device structure, a preparation method thereof and a chip, and belongs to the technical field of semiconductor devices. The semiconductor device structure comprises a gold-silver alloy bump and a UBM layer, and the UBM layer is composed of a seed layer, a diffusion barrier layer and an adhesion layer or composed of the diffusion barrier layer and the adhesion layer. The diffusion barrier layer is composed of a platinum group element simple substance and / or an alloy containing a platinum group element, preferably composed of platinum, rhodium, iridium or an alloy thereof; the bottom of the gold-silver alloy bump is connected with the seed layer or the diffusion barrier layer, and the adhesion layer is connected with a chip electrode. By improving the UBM layer, the combination reliability of the gold-silver alloy bump and the UBM layer is improved, the obtained semiconductor device structure can pass a high-end chip reliability test, and a flip chip is prepared by replacing gold with gold-silver alloy.

The invention provides a high-reliability single-component bottom filling adhesive, a preparation method thereof and a flip chip. The bottom filling adhesive comprises the following components in percentage by mass: 50%-60% of spherical silicon dioxide, 28%-32% of epoxy resin, 13%-17% of a modified polyether amine curing agent, 0.1%-0.2% of carbon black, 0.3%-0.5% of a silane coupling agent and 0.2%-0.4% of an adhesion promoter. The epoxy resin is composed of bisphenol A epoxy resin and first epoxy resin, and the model of the first epoxy resin is NANOPOXE500 or NANOPOXE470. The thermal expansion coefficient and the storage modulus of the underfill adhesive are controlled by adjusting the proportion of the first epoxy resin, the bisphenol A epoxy resin and the modified polyether amine curing agent, so that the underfill adhesive is still in close contact with a chip in a high-low temperature environment for a long time, and the reliability of chip packaging is improved.

The invention relates to the technical field of semiconductor packaging, and provides a semiconductor packaging process which comprises the following steps: obtaining a circuit board, and preprocessing the circuit board; performing SMT assembly operation on the bottom surface of the circuit board; silk-screening solder paste on the top surface of the circuit board; a tin cap of the flip chip is dipped with a soldering flux; mounting a flip chip and other elements on the top surface of the circuit board; performing reflow soldering operation on the top surface of the circuit board; according to the semiconductor packaging process provided by the embodiment of the invention, the tin cap of the flip chip can be dipped with the soldering flux before confluence welding operation is carried out on the flip chip, so that in the reflow soldering process, the soldering flux can effectively protect the tin cap and a PCB bonding pad and prevent oxidation, the collapsed tin cap can recover the original state of the tin cap to the greatest extent during reflow soldering, and the reliability of the flip chip is improved. The tin cap can be in contact with the PCB bonding pad more effectively, good welding is formed, the wettability is improved, oxidation is reduced, the welding strength is enhanced, and the problems of pseudo soldering, open circuit and the like are reduced.

Devices and methods are disclosed for high power inverter modules with enhanced thermal and mechanical performance, for use in electric vehicles. The disclosed devices feature enlarged clips that cover an entire die, to distribute mechanical forces, thus preventing die cracks for improved reliability. In these power modules, semiconductor dies are sandwiched between a three-layer direct bond metal (DBM) structure and the enlarged clip. A pre-molded clip assembly can be used that includes integrated metalliization to eliminate the need for external wire bonds. Alternatively, semiconductor dies can be inverted in a flip-chip configuration to face a modified DBM structure that integrates the metallization. Simulations of the disclosed power inverters indicate improved efficiency in dissipating heat.

The invention relates to the technical field of signal processing, and discloses a flip chip vibration signal denoising method and system, and the method comprises the steps: obtaining a vibration signal responded by a to-be-detected flip chip under the action of external ultrasonic excitation, carrying out the segmentation processing of the vibration signal, constructing an initial sparse dictionary according to the segmented vibration signal, and iteratively updating the sparse dictionary; in the iteration updating process, sparseness parameters are adjusted in real time along with the number of iterations, and soft threshold denoising is conducted on residual terms; introducing a feature projection matrix to perform joint modeling on each section of vibration signal, and constructing a joint optimization model according to the updated sparse dictionary and the corresponding sparse coefficient; alternately optimizing the sparse coefficient and the feature projection matrix in the joint optimization model to obtain an optimal solution of the sparse coefficient; and combining the updated sparse dictionary and the optimal solution of the sparse coefficient to reconstruct the vibration signal to obtain a denoised vibration signal. According to the method, transient features can be effectively extracted, expression of key features is enhanced, noise is suppressed, and denoising robustness and reconstruction precision are improved.

A leadframe includes first leads and second leads, wherein each lead of the first and second leads has an upper surface. First and second silver spots are provided on the upper surface of each lead of the first and second leads. An integrated circuit die has a front surface including first and second interconnection pads. A first pillar is mounted to each first interconnection pad, and second pillar is mounted to each second interconnection pad. The integrated circuit die is mounted in flip chip orientation to the leadframe with the first pillars soldered to the first silver spots and the second pillars soldered to the second silver spots. A resin body encapsulates the integrated circuit die mounted to the leadframe.

A described example includes: a heat slug coupled to a package substrate, the heat slug configured to conduct a current between terminals of the package substrate; a first magnetic shield mounted to a top surface of the package substrate, the first magnetic shield including a die mount area; a semiconductor die flip chip mounted to the die mount area; a second magnetic shield mounted to the package substrate, the second magnetic shield having a cantilever portion extending over a portion of the semiconductor die including a Hall element; electrical connections of wire bonds or ribbon bonds between bond pads of the semiconductor die and leads on the package substrate; and mold compound covering the electrical connections, the semiconductor die, the first magnetic shield, and the second magnetic shield, while a portion of the heat slug is exposed forming a thermal pad for a semiconductor device package.

A package is disclosed. The package includes a carrier that comprises a first conductive layer on a first side and a second conductive layer on a second side opposite the first side. The first conductive layer comprises wire bonding pads. The package also includes a semiconductor die that is flip chip mounted on the first side of the carrier.

The invention provides a chip packaging structure and a packaging method, and relates to the technical field of semiconductor packaging. In the chip packaging structure, a first flip chip is mounted on a substrate and is electrically connected with the substrate. The second flip chip is at least partially mounted to the first flip chip. The second flip chip is provided with a first electric connecting column which is electrically connected with the substrate; the second flip chip is provided with a first cylinder. The third flip chip is at least partially attached to the second flip chip; the third flip chip is provided with a second electric connecting column which is electrically connected with the substrate; the third flip chip is provided with a second cylinder. The first column body is located between the first electric connection column and the first flip chip, and a gap is formed between the first column body and the substrate. The second column body is located between the second electric connection column and the second flip chip, and a gap is formed between the second column body and the substrate. The packaging structure is beneficial to improving the flowability and the filling property of the bottom colloid, and prevents the colloid from cracking or generating a cavity.

The invention relates to a method for predicting the thermal stress of a flip-chip bonding micro-welding spot interconnection structure, which comprises the following steps of: performing a flip-chip bonding test on an electronic device based on a reflow soldering process, establishing a three-dimensional geometric model, and calculating the thermal stress of the micro-welding spot interconnection structure based on the change of the interconnection structure between the micro-welding spot and a Ni-P / Cu bonding pad in the flip-chip bonding process of the electronic device. Coupling the material attributes of the chip, the substrate, the micro-solder joint and the Ni-P / Cu bonding pad in the flip-chip bonding test to obtain an equivalent finite element model, and simulating corresponding flip-chip bonding based on a birth-death element method in the equivalent finite element model; and finally, calculating and identifying the maximum equivalent thermal stress distribution rule at the interface of the micro welding spot layer, the intermetallic compound layer and the bonding pad by using the equivalent finite element model, namely predicting the thermal stress of the flip-chip micro welding spot interconnection structure. Theoretical support is provided for improving the reliability of the flip-chip bonding micro-welding spot interconnection structure, and a theoretical foundation is laid for thermal stress regulation and control.

The embodiment of the invention provides a flip chip offset measurement system and method, the measurement system comprises a first light source and a second light source which are different in emergent light beam wavelength, an imaging assembly and a processing assembly, and the first light source is controlled to emit a first light beam which penetrates through a flip chip and irradiates a first target in a deep layer; obtaining a first image containing the first target from the first detector; controlling a second light source to emit a second light beam to irradiate a second target on the surface of the flip chip, acquiring a second image containing the second target from a second detector, and finally acquiring a first offset and a second offset of the flip chip relative to the substrate based on the first image and the second image by a processing assembly, and obtaining the bonding offset of the flip chip according to the first offset and the second offset. According to the invention, the dual-wavelength light source is adopted to cooperatively irradiate the flip chip in a time-sharing / wave-band-sharing manner, so that the penetrability-reflectivity contradiction of single-wavelength detection is broken through, and the accuracy and reliability of lamination offset detection are improved.

The invention provides an underfill adhesive capable of controlling adhesive width, a preparation method of the underfill adhesive and a flip chip, and the underfill adhesive comprises the following components in percentage by mass: 60%-67% of an inorganic filler, 17%-21% of epoxy resin, 15%-20% of an amine curing agent, 0.05%-0.3% of hydrophobic modified fumed silica, 0.1%-0.3% of an amine accelerator and 0.1%-0.2% of carbon black. According to the invention, through a specific formula proportion and control of the addition amount of the hydrophobic modified fumed silica, the control of the hydrophobic degree of the bottom filling glue solution is realized, so that the control of the glue width in the dispensing process is realized, and the reliability and the manufacturing yield of chip packaging are improved.

The invention relates to the technical field of quantum chips, in particular to a superconducting quantum flip chip and a preparation method thereof. Comprising an upper layer substrate, a first superconducting metal layer, a second superconducting metal layer and a lower layer substrate which are stacked, and the upper layer substrate, the first superconducting metal layer, the second superconducting metal layer and the lower layer substrate form a closed cavity; the metal part is arranged on the second superconducting metal layer and is supported between the second superconducting metal layer and the first superconducting metal layer; the first superconducting metal layer comprises a first circuit layer and a Josephson junction, and the second superconducting metal layer comprises a second circuit layer; and the first circuit layer, the second circuit layer, the Josephson junction and the metal part are all located in the closed cavity. According to the invention, the metal part is only prepared on the lower substrate, the metal part does not need to be arranged on the upper top substrate, the negative influence of the metal part processing technology on the bit performance is avoided as far as possible, and the chip performance is improved.

The invention discloses a flip chip single particle test heat dissipation system and heat dissipation method.The system comprises a radiator, a semiconductor chilling plate, a graphene film and an insulating spacer, the radiator is of a middle-hollowed-out structure, and a bare chip substrate can be completely exposed in the hollowed-out area of the radiator; the bottom of the radiator is attached to the hot end of the semiconductor chilling plate through heat-conducting glue. The semiconductor chilling plate adopts a middle hollow structural form, and a bare chip substrate can be completely exposed in a hollow area of the semiconductor chilling plate; the surface of the graphene film can completely cover the surface of the semiconductor chilling plate and is not hollowed out; one side of the graphene film is attached to the cold end of the semiconductor chilling plate through heat-conducting glue, and the other side of the graphene film directly covers the bare chip substrate and the insulating spacer of the flip chip. The method is implemented based on the system. The device has the advantages of simple and compact structure, convenience in operation, good heat dissipation effect, low cost and the like.

Methods and apparatuses for plasma treatment of electrical interconnects of electronic assemblies for integrated circuits such as flip chips are disclosed. A method of interconnect bonding includes applying a plasma comprising activated hydrogen via an atmospheric pressure plasma applicator to a metallic contact supported on a substrate to remove oxidation and create a newly deoxidized metal surface. The metallic contact can be bonded to another via reflow or thermocompression bonding. An inert gas environment can be formed within an enclosure for application of the plasma and / or bonding of the metallic contact.

The invention relates to the technical field of flip chips, in particular to a flip chip ultrasonic excitation vibration signal denoising method and system, and the method comprises the steps: obtaining an ultrasonic excitation vibration signal of a flip chip; empirical Fourier decomposition is improved based on Welch transformation and automatic multi-scale peak detection, and the vibration signals are decomposed; screening decomposition components of the vibration signals based on an information entropy and kurtosis joint index; and performing dimensionality reduction compression on the signal component by using principal component analysis, extracting main frequency characteristics to create a reference signal of a frequency domain adaptive filter, and performing noise reduction processing on a chip vibration signal. According to the method, the modal characteristics of the chip can be effectively extracted while the ultrasonic excitation vibration signal noise of the flip chip is removed, excellent denoising performance is achieved, the noise reduction effect on the ultrasonic excitation vibration signal of the flip chip is improved, and therefore the accuracy and reliability of flip chip defect detection are improved.

The invention relates to the technical field of semiconductor packaging materials, and discloses an epoxy resin plastic packaging material and a preparation method and application thereof. The method comprises the following steps: mixing 2-40 wt% of epoxy resin, 3-30 wt% of a curing agent, 0.01-10 wt% of a curing accelerator, 20-90 wt% of an inorganic filler, 0.05-5 wt% of a release agent, 0.04-3 wt% of a coupling agent, 0-25 wt% of a flame retardant, 0-3 wt% of a modifier and 0-3 wt% of a coloring agent to obtain a mixture, and then extruding and mixing the mixture; wherein the inorganic filler is selected from one or more than two of silicon dioxide, aluminum oxide and magnesium oxide, and the maximum particle size of the inorganic filler is less than or equal to 20 microns; the extrusion mixing process is carried out in equipment with a non-metal lining. The epoxy resin plastic packaging material has the characteristics of low viscosity, high filling property, high reliability, low warpage and the like, so that the epoxy resin plastic packaging material meets the requirement of flip chip packaging.

The invention relates to the field of semiconductor packaging stress testing, and discloses a mounting method for a micro-size packaging type strain gauge, which comprises the following steps of: placing a sample to be tested in a bearing clamp, fixing the sample to be tested, then loading the sample to be tested into a bearing base of high-precision inverted mounting equipment, fixing the bearing clamp, and starting vacuum adsorption; putting a strain gauge adhesive into an adhesive dipping disc and scraping the adhesive; the customized suction head sucks the strain gauges and moves the strain gauges to the position above the glue dipping disc to be dipped in the bonding glue; the strain gauge pattern coincides with the to-be-pasted position of the product, and the customized suction head pastes the strain gauge to the to-be-detected position of the product; the customized suction head exerts pressure downwards as a whole, and the strain gauge is further flattened in a hot pressing mode; and putting the processed sample to be detected together with the strain gauge into an air pressure drying oven for pressurizing and curing. According to the invention, the flatness of the micro-sized packaged strain gauge after surface mounting and curing is greatly improved, and the precision and stability of subsequent stress testing are further improved.

The invention relates to an underfill adhesive for flip chips, which is prepared from the following raw materials in parts by mass: 22-30 parts of bifunctional epoxy resin, 5-8 parts of polyfunctional epoxy resin, 10-14 parts of polyether modified flexible epoxy resin, 7-10 parts of trifunctional maleimide compound shown in a formula (I), 4-7 parts of curing agent containing more than two amino groups and 3-4 parts of low molecular weight polyamide, 1-3 parts of a coupling agent, 0.5-2 parts of a curing accelerator and 100 parts of coupling agent modified spherical silica powder. The underfill adhesive provided by the invention has very good fluidity, relatively high Tg, proper mechanical strength and excellent warping resistance, also has high-temperature-resistant and damp-heat-resistant aging resistance and excellent moisture resistance, and can be applied to various high-temperature / high-humidity scenes.

The invention discloses a flip chip packaging structure and method, and relates to the technical field of chip packaging, the flip chip packaging structure comprises a substrate, bonding pads, solder bumps, a chip unit and a bearing assembly, the upper end of the substrate is fixedly provided with a plurality of groups of bonding pads, and the upper ends of the bonding pads are provided with the solder bumps fixedly connected with the bonding pads; a bearing assembly is also arranged between the substrate and the chip unit; the bearing assembly sequentially comprises a lower supporting layer, a middle layer and an upper supporting layer which are integrally formed from bottom to top; through holes are formed in the positions, corresponding to the solder bumps and the bonding pads, of the lower supporting layer; a plurality of grooves which are communicated with one another are formed in the positions, corresponding to the solder bumps, of the middle layer, a feeding opening which is communicated with one groove is formed in the position, corresponding to the groove, of the middle layer, and an exhaust hole is formed in the end, away from the feeding opening, of the middle layer; by arranging the bearing assembly, the filling effect of the first filling glue is improved, and the situation of air residue is reduced.

Provided in the present invention are an underfill adhesive for eliminating flow marks and a preparation method therefor and a flip chip. The underfill adhesive comprises the following components in percentages by mass: 16-24% of a polyurethane-modified epoxy resin, 52-64% of a filling agent, 19-23% of a curing agent, 0.2-0.6% of an accelerant and 0.1-0.2% of a coloring agent. The underfill adhesive for eliminating flow marks of the present application is prepared from the polyurethane-modified epoxy resin, the filling agent, the curing agent, the accelerant and the coloring agent according to a specific proportion. The good compatibility between the polyurethane-modified epoxy resin and the filling agent is utilized, the curing agent is added to change a reaction system into a solid state from a flowing state, and the reaction rate is increased by means of the accelerant, thereby improving the curing rate of the underfill adhesive, and thus improving the manufacturing efficiency of a flip chip.

The present invention refers to a hybrid integrated silicon drift detector (HiSDD) for X-ray detection, particularly to a HiSDD combining a silicon drift detector (SDD) with a low-noise preamplifier on a SDD sensor chip to improve the electrical and structural properties of the detector assembly. The invention further refers to a corresponding method for the fabrication of a HiSDD. A HiSDD according to the invention hybridly integrates a silicon drift detector, SDD, sensor chip and a preamplifier module; wherein electrically conductive paths are formed on a surface of the SDD sensor chip, having first ends configured for flip chip bonding and second ends configured for wire bonding; wherein the preamplifier module having contacts disposed on a surface of the preamplifier module, and wherein the first ends of the electrically conductive paths are flip chip bonded to the contacts of the preamplifier module.

The invention provides an on-chip integrated laser light source and an optical coupling integration method thereof.The on-chip integrated laser light source comprises a silicon optical substrate and a light source chip assembly integrated on the silicon optical substrate, and the silicon optical substrate comprises an optical signal transmission waveguide; the light source chip assembly comprises a surface-emitting distributed feedback laser chip so as to generate laser beams emitted in the direction perpendicular to the surface of the chip. The on-chip integrated laser light source further comprises a grating coupling structure arranged between the surface emission distributed feedback laser chip and the optical signal transmission waveguide. The light-emitting surface of the surface-emitting distributed feedback laser chip is arranged towards the silicon light substrate, and a laser beam generated by the surface-emitting distributed feedback laser chip is directly projected and coupled into the light signal transmission waveguide through the grating coupling structure; the surface-emitting distributed feedback laser chip is fixedly combined on the silicon optical substrate through a flip chip technology, so that the high-precision end face alignment requirement of the heterogeneous integrated waveguide is converted into high-efficiency grating coupling based on a surface light emitting mode. In this way, harsh end face coupling is converted into efficient grating coupling.

The present disclosure provides a package structure having a photonic integrated circuit, the package structure includes a substrate, a chip and an optical module. The chip has an optical waveguide structure and a recessed portion. The optical waveguide structure is adjacent to the recessed portion. The recessed portion faces the substrate, and the chip is engaged to the substrate by flip chip. The optical module is provided in the recessed portion of the chip.

A device includes a first substrate having a principal surface; a second substrate having a principal surface, in which the first substrate is bump-bonded to the second substrate such that the principal surface of the first substrate faces the principal surface of the second substrate; a circuit element having a microwave frequency resonance mode, in which a first portion of the circuit element is arranged on the principal surface of the first substrate and a second portion of the circuit element is arranged on the principal surface of the second substrate; and a first bump bond connected to the first portion of the circuit element and to the second portion of the circuit element, in which the first superconductor bump bond provides an electrical connection between the first portion and the second portion.

A system for laser bonding of flip chip, and more particularly, to a system for laser bonding of flip chip for bonding a flip chip-type semiconductor chip to a substrate by using a laser beam is provided. According to the system for laser bonding of flip chip of the present disclosure, by performing laser bonding on a substrate while pressurizing semiconductor chips, even semiconductor chips which are bent or likely to bend may be bonded to the substrate without causing poor contact of solder bumps.

The invention discloses a flip chip FC packaging technology method, and relates to the technical field of chip packaging, and the method comprises the steps: collecting the physical parameters of a flip chip packaging material, building a thermal-mechanical coupling model, carrying out the thermal-mechanical coupling simulation and mechanical stress analysis of a packaging structure through the built thermal-mechanical coupling model, and carrying out the analysis of the mechanical stress of the packaging structure. And a stress concentration area and a part with large deformation are identified, and optimization design of the packaging structure is carried out based on a thermal-mechanical coupling analysis result. The reliability of the packaging structure is remarkably improved through optimization design and a strict testing process, in the design stage, a stress concentration area and a potential deformation problem are analyzed and recognized through thermal-mechanical coupling, so that the geometrical shape, material selection and solder ball layout are optimized in advance, and the reliability of the packaging structure is improved through optimization of a thermal management strategy. The heat management performance of the packaging structure is effectively improved, the heat dissipation efficiency of the packaging structure is remarkably improved, and the packaging structure can better adapt to application scenes with extremely high requirements for heat management.