353 results about "Flip chip" patented technology

The invention discloses an intelligent sealing test method and system for a wafer in a semiconductor chip, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: initializing a magneto-electric field cooperation parameter, optimizing the magneto-electric field cooperation parameter through a multi-target genetic algorithm, and driving core-shell nanoparticles to carry out the metallization filling of a high-precision through hole wafer, generating a wafer with a metalized through hole structure; based on the metalized through hole structure wafer, bonding parameters are generated through a laser Doppler frequency vibration spectrum analysis method, flip interconnection is achieved through a thermal ultrasonic virtual process, and a low-defect bonding wafer is generated; a finite element inversion algorithm is adopted, a stress distribution map of a bonding interface is established, an anti-thermal-stress packaging layer is constructed through an intelligent stress matching algorithm, and the low-defect bonding wafer is packaged; and through a multi-target genetic algorithm, magnetoelectric field cooperation parameters are optimized, core-shell nano-particles are driven to directionally deposit, and accurate control over the metallization filling process is achieved.

The invention relates to a method for predicting the thermal stress of a flip-chip bonding micro-welding spot interconnection structure, which comprises the following steps of: performing a flip-chip bonding test on an electronic device based on a reflow soldering process, establishing a three-dimensional geometric model, and calculating the thermal stress of the micro-welding spot interconnection structure based on the change of the interconnection structure between the micro-welding spot and a Ni-P / Cu bonding pad in the flip-chip bonding process of the electronic device. Coupling the material attributes of the chip, the substrate, the micro-solder joint and the Ni-P / Cu bonding pad in the flip-chip bonding test to obtain an equivalent finite element model, and simulating corresponding flip-chip bonding based on a birth-death element method in the equivalent finite element model; and finally, calculating and identifying the maximum equivalent thermal stress distribution rule at the interface of the micro welding spot layer, the intermetallic compound layer and the bonding pad by using the equivalent finite element model, namely predicting the thermal stress of the flip-chip micro welding spot interconnection structure. Theoretical support is provided for improving the reliability of the flip-chip bonding micro-welding spot interconnection structure, and a theoretical foundation is laid for thermal stress regulation and control.

The invention relates to the field of semiconductor packaging stress testing, and discloses a mounting method for a micro-size packaging type strain gauge, which comprises the following steps of: placing a sample to be tested in a bearing clamp, fixing the sample to be tested, then loading the sample to be tested into a bearing base of high-precision inverted mounting equipment, fixing the bearing clamp, and starting vacuum adsorption; putting a strain gauge adhesive into an adhesive dipping disc and scraping the adhesive; the customized suction head sucks the strain gauges and moves the strain gauges to the position above the glue dipping disc to be dipped in the bonding glue; the strain gauge pattern coincides with the to-be-pasted position of the product, and the customized suction head pastes the strain gauge to the to-be-detected position of the product; the customized suction head exerts pressure downwards as a whole, and the strain gauge is further flattened in a hot pressing mode; and putting the processed sample to be detected together with the strain gauge into an air pressure drying oven for pressurizing and curing. According to the invention, the flatness of the micro-sized packaged strain gauge after surface mounting and curing is greatly improved, and the precision and stability of subsequent stress testing are further improved.

The present invention refers to a hybrid integrated silicon drift detector (HiSDD) for X-ray detection, particularly to a HiSDD combining a silicon drift detector (SDD) with a low-noise preamplifier on a SDD sensor chip to improve the electrical and structural properties of the detector assembly. The invention further refers to a corresponding method for the fabrication of a HiSDD. A HiSDD according to the invention hybridly integrates a silicon drift detector, SDD, sensor chip and a preamplifier module; wherein electrically conductive paths are formed on a surface of the SDD sensor chip, having first ends configured for flip chip bonding and second ends configured for wire bonding; wherein the preamplifier module having contacts disposed on a surface of the preamplifier module, and wherein the first ends of the electrically conductive paths are flip chip bonded to the contacts of the preamplifier module.

The invention provides an on-chip integrated laser light source and an optical coupling integration method thereof.The on-chip integrated laser light source comprises a silicon optical substrate and a light source chip assembly integrated on the silicon optical substrate, and the silicon optical substrate comprises an optical signal transmission waveguide; the light source chip assembly comprises a surface-emitting distributed feedback laser chip so as to generate laser beams emitted in the direction perpendicular to the surface of the chip. The on-chip integrated laser light source further comprises a grating coupling structure arranged between the surface emission distributed feedback laser chip and the optical signal transmission waveguide. The light-emitting surface of the surface-emitting distributed feedback laser chip is arranged towards the silicon light substrate, and a laser beam generated by the surface-emitting distributed feedback laser chip is directly projected and coupled into the light signal transmission waveguide through the grating coupling structure; the surface-emitting distributed feedback laser chip is fixedly combined on the silicon optical substrate through a flip chip technology, so that the high-precision end face alignment requirement of the heterogeneous integrated waveguide is converted into high-efficiency grating coupling based on a surface light emitting mode. In this way, harsh end face coupling is converted into efficient grating coupling.

The invention discloses a flip chip bottom filling adhesive and a preparation method and application thereof, and belongs to the technical field of chip packaging. The bottom filling adhesive for the flip chip is prepared from the following components in percentage by mass: 48 to 52 weight percent of bisphenol F type epoxy resin, 18 to 22 weight percent of curing agent, 3 to 9 weight percent of toughening agent, 8 to 16 weight percent of aluminum nitride, 4 to 8 weight percent of nano silicon dioxide, 4 to 8 weight percent of boron nitride, 0.5 to 1 weight percent of thixotropic agent and 1.0 to 1.5 weight percent of latent accelerant. Bisphenol F type epoxy resin is used as a matrix and is matched with a rapid curing agent and a toughening agent, and high-thermal-conductivity aluminum nitride, nano silicon dioxide and flaky boron nitride are added to form a synergistic system, so that medium-low-temperature rapid curing, high toughness, low thermal stress and excellent thermal conductivity are realized. According to the preparation method disclosed by the invention, the product has high thermal conductivity, low stress and excellent dimensional stability while the medium and low temperature rapid curing is ensured.

1. The name of the design product: X-ray detection equipment (AX8500). 2. The use of the design product: The design product is used for the detection of BGA, CSP, flip chip detection, semiconductors, packaged components, electronic connector module detection, ceramic products, aviation components, photovoltaic industry, battery industry and other special industries on large circuit boards. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: perspective view.

The present application provides a flip chip light emitting diode and a manufacturing method thereof. The flip chip light emitting diode comprises a transparent substrate, an epitaxial composite layer, a first conductive type electrode pad, a second conductive type electrode pad and a wafer bonding composite layer. The epitaxial composite layer is disposed on the transparent substrate. The first conductive type electrode pad is disposed on the transparent substrate and electrically connected to the epitaxial composite layer. The second conductive type electrode pad is disposed on the epitaxial composite layer and electrically connected to the epitaxial composite layer, and is located on the same horizontal plane as the first conductive type electrode pad on the same side of the transparent substrate. The wafer bonding composite layer comprises at least one titanium dioxide (TiO2) layer and at least one silicon dioxide (SiO2) layer, and is interposed between the epitaxial composite layer and the transparent substrate.

A solid state drive (SSD) device includes a substrate, a first buffer chip disposed on the substrate, a second buffer chip disposed on the first buffer chip, a plurality of first non-volatile memory chips connected to the second buffer chip through wire bonding, a controller configured to send a control signal to the plurality of first non-volatile memory chips through a first channel, and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through first wires.

The invention discloses an ultrasonic nondestructive testing system and method for defects of a flip-chip. The ultrasonic nondestructive testing system comprises an upper computer, a pulse transceiver, an acquisition card, an ultrasonic sensor, a displacement platform, a three-dimensional motion platform and a motion controller, the upper computer serves as a control platform and is responsible for control instruction issuing and data processing. The pulse transceiver, the acquisition card and the high-frequency ultrasonic sensor form a signal acquisition and transmission platform which is responsible for transmitting, receiving, transmitting and analog-to-digital conversion of ultrasonic signals; the displacement platform is used for fixing the flip-chip bonding chip; the three-dimensional motion platform and the motion controller form a three-dimensional motion control system, and the three-dimensional motion control system is responsible for carrying an ultrasonic sensor to execute scanning at different spatial positions. The chip is integrally detected, welding spots do not need to be detected one by one, and the defect detection efficiency can be greatly improved.

A micromechanical component for a sound transducer device. The micromechanical component includes a substrate, a diaphragm, at least one piezoelectric element, and at least one electrical contact connection. The diaphragm can vibrate and is connected to the substrate. The at least one piezoelectric element is disposed between the diaphragm and the substrate and is connected to the diaphragm. The at least one piezoelectric element is designed to produce and / or detect vibrations of the diaphragm in the ultrasonic range. The at least one electrical contact connection is electrically connected to the at least one piezoelectric element. The micromechanical component can be connected, using flip chip technology, to a control circuit such that the at least one piezoelectric element can be electrically connected to the control circuit by means of the at least one electrical contact connection.

The invention provides a high-yield low-capacitance TVS (Transient Voltage Suppressor) diode packaging process, which comprises the following steps: S1, back metallization: a sputtering table is adopted, the thickness of Ti / Ni / Ag is 50 / 200 / 800nm, and the back temperature is lt; the contact resistance is less than or equal to 0.05 m omega.mm < 2 > and the resistance is gt; 0.08, sputtering again; s2, wafer thinning and stress release are carried out; s3, front passivation / low-k dielectric layer preparation; s4, preparing an aluminum-copper bump; s5, performing laser scribing; s6, inversely mounting a patch; s7, performing vacuum reflow soldering; s8, plasma cleaning and plasma underfilling are carried out; and S9, laser marking is carried out. According to the process, five contradictions of'extreme low capacitance, extreme yield, low temperature drift, zero cavity and green manufacturing 'are simultaneously grounded in the same package, so that the TVS device really meets the dual requirements of a 40Gbps high-speed interface and a vehicle gauge for the first time.

A fan-out wafer-level packaging (FOWLP) unit including a substrate, at least one first die, a first dielectric layer, a plurality of first conductive circuits, a second dielectric layer, a plurality of second conductive circuits, and at least one second die is provided. A range perpendicular to a second surface of the first die is defined as a chip area. The second dielectric layer is provided with a plurality of second slots allowing the second conductive circuit to expose and form bonding pads. The bonding pads located around the chip area are first bonding pads. The second die is disposed over the second dielectric layer by flip chip and electrically connected to the first die which is electrically connected with the outside by the first bonding pads. Thereby problems of conventional FOWLP generated during manufacturing of the conductive circuits including higher manufacturing cost and less environmental benefit can be solved.

A light emitting diode (LED) structure that includes a stent substrate; and a circuit having a plurality of contact pads arranged along a length of the stent substrate. The structure further includes a plurality of light emitting diode (LED) chips, wherein each light emitting diode chip in the plurality of chips is engaged to a set of contact pads along the length of the metal stent substrate. A continuous phosphor layer is present overlying the plurality of light emitting diode (LED) chips, the continuous phosphor layer including first portions that are in direct contact with at least a light transmission surface of the light emitting diode (LED) chips and second portions that bridge across the space separating adjacently positioned light emitting diode. An encapsulant present over the continuous phosphor layer that is covering at least the light emitting diode chips.

The invention discloses a manufacturing method of an electromagnetic shielding structure for board-level plastic package of a vertical structure chip and a flip chip, which comprises the following steps of: firstly, manufacturing a bottom interconnection line layer, a bottom bonding pad and an external grounding point at the bottom end of a partition box dam of a shielding cover structure according to design requirement parameters, and then manufacturing the partition box dam and a copper column for realizing vertical interconnection; after the plastic package chip is fixedly mounted, a vertical interconnection line and a top metal layer of a shielding cover structure are sequentially manufactured layer by layer; when the carrier is separated, a layer of copper foil is reserved for manufacturing an outer circuit layer and an outer bonding pad, and finally cutting is carried out to obtain a single packaged finished product; a top metal layer, a partition box dam, vertically interconnected copper columns, interconnection line layers at all levels, bonding pads and grounding points are directly processed and manufactured by using a substrate wet process such as laser drilling, copper deposition, electroplating and pattern transfer in the prior art, so that the space occupation area can be reduced, the process is simplified, the space utilization rate is improved, and the cost input is reduced; and the stability and reliability of the product are ensured.

The utility model discloses an embodiment of backlight module and display module, this backlight module includes backboard, light guide plate, lamp plate and electronic component, and backboard includes bottom plate and side plate, and bottom plate and side plate form accommodating space, light guide plate is located bottom plate one side in accommodating space, and lamp plate is located light guide plate far from bottom plate one side, and lamp plate is fixedly connected with light guide plate, and lamp plate is provided with luminous element to light guide plate one side, and electronic component sets up on lamp plate, the technical scheme provided by the utility model embodiment, through with the integral design of lamp strip and circuit board as lamp plate, thereby save the connector for connecting lamp strip and circuit board, and through with lamp plate and light guide plate assembly together, and make lamp plate flip chip in light guide plate's light -admitting side, make backboard not use again make for the lug of bearing circuit board, and lamp plate also need not use screw lock on the lug of backboard, be favorable to simplifying backplate, save assembly work hours.

The utility model relates to a transparent device with a built-in integrated circuit (IC), which comprises an insulated transparent substrate, a driving IC packaged on the front surface of the transparent substrate through an insulated transparent adhesive layer, a transparent conductive circuit electrically connected to the driving IC, and a transparent light-emitting diode (LED) flip chip with three primary colors of red, green and blue (RGB), the conductive circuit comprises a connecting end which is exposed outside the insulating transparent adhesive layer and is connected with a pin of the driving IC and an internal conductive circuit which is packaged in the insulating transparent adhesive layer, and the LED flip chip is electrically connected with the driving IC through the internal conductive circuit. The utility model has the advantages of compact structure, small volume, light weight and the like, and can be used for better manufacturing the transparent display screen.

The invention provides a flip chip airtight packaging method and a packaged chip, and relates to the technical field of semiconductor packaging. Comprising the steps that a preset number of half grooves are etched in the top face of a silicon-based adapter plate through a dry etching method, the preset number is the number of chips needing to be packaged, and each half groove comprises a plurality of silicon columns corresponding to chip function points or grounding points of the corresponding chips; solder is evaporated on the periphery of each half groove and the top end of each silicon column, and an annular gold layer is electroplated on the periphery of each chip needing to be packaged; and setting preset hot pressing process parameters, mounting each chip needing to be packaged on the corresponding half groove in an inverted manner by adopting a hot pressing process, and carrying out plastic packaging by utilizing a plastic packaging material. According to the invention, the air tightness requirement can be improved while the size of the packaged chip is reduced.

The invention discloses a flip chip bottom filling simulation method and device, a medium and equipment, and relates to the technical field of flip chip bottom filling simulation. According to the method, a color gradient lattice Boltzmann model is adopted to simulate the bottom filling process of the flip chip in a computational domain formed by carrying out two-grid division on a flow plane perpendicular to the depth direction, and a wetting phase (filling glue) and a non-wetting phase (air) are clearly distinguished by using a color function, so that a two-phase interface is dynamically tracked; when the flow field change in the bottom filling self-absorption process of the flip chip is simulated, the interface average curvature in the depth direction and the average friction force of the upper and lower fixed walls of the flip chip are introduced to determine the acting force applied to the two-phase fluid interface, so that the three-dimensional physical effect is reflected, and on the premise that the close two-dimensional calculation cost is maintained, the flow field change is simulated. The accuracy of flip chip bottom filling simulation can be remarkably improved, and the whole process of flip chip bottom filling can be quickly predicted at low cost.

The invention discloses a miniature lamp bead packaging structure and a packaging process. The miniature lamp bead packaging structure comprises two sets of hardware, an LED flip chip and a packaging body. The LED flip chip is arranged between the two sets of hardware, the upper end faces of the hardware are welding end faces, and the positive electrode and the negative electrode of the LED flip chip are welded to the welding end faces of the two sets of hardware respectively. The packaging body is made of a transparent material and wraps the hardware and the LED flip chip; the lower end face of the hardware is a power connection end face, and the power connection end face is exposed out of the packaging body and is flush with the lower end face of the packaging body. Through the design that the power connection end face of the hardware is exposed out of the packaging body and is flush with the lower end face of the packaging body, the miniature lamp bead can be directly attached to the surface of the printed circuit board, plane attachment of the power connection end face and the circuit board is achieved, the welding operation steps are greatly simplified, the requirement for the technical level of operators is lowered, the production efficiency is improved, and the production cost is reduced. And meanwhile, the processing cost is greatly reduced.

A method for fabricating a high-speed semiconductor device, the method comprising the steps of: providing a light emitting device structure on substrate, activated p-doped; etching grooves on the p-doped layer, partially or fully filling the grooves with noble metal; and constructing at least one top emitting flip chip light emitting device and / or at least one bottom emitting flip chip light emitting device.

The utility model provides a flip chip cleaning device and cleaning equipment, and relates to the technical field of semiconductor cleaning equipment. The flip chip cleaning device comprises a cleaning base, and the cleaning base comprises a bottom wall and a peripheral side wall connected with the bottom wall. A clamping groove is formed in the peripheral side wall and used for containing a base plate. Wherein a flip chip is mounted on one side, far away from the bottom wall, of the substrate. A drain hole is formed in the bottom wall. A first water inlet hole is formed in the peripheral side wall and located in the side, away from the bottom wall, of the clamping groove. The flip chip cleaning device is favorable for fully cleaning residues such as soldering flux on the bump at the bottom of the flip chip, and can reduce the residual cleaning liquid on the surface of the substrate and improve the cleaning quality.

A packaged electronic device (100) includes a multilayer substrate (106) including a first side (103), a first layer (110) having a first plurality of conductive structures (112, 114, 116) along the first side (103), and a second layer (120) having a second plurality of conductive structures (122, 124, 126); a semiconductor die (101) soldered to a first set of conductive structures (112, 114); a conductive clip (108) directly connected to one of the conductive structures (116, 136) of the first layer (110) and directly connected to a second side (105) of the semiconductor die (101); and a package structure (140) surrounding a portion of the conductive clip (108) and the semiconductor die (101).

The utility model relates to a low-noise inductor, which belongs to the technical field of inductors and comprises a mounting plate, the top of the mounting plate is fixedly connected with a shielding cover, and a substrate is embedded in the top end of the mounting plate. The inductor has the advantages that the shielding cover outside the inductor body is of a structure with a plurality of shielding layers, each layer is made of conductive materials, electromagnetic interference can be effectively shielded, magnetic materials such as ferrite are embedded in the shielding cover outside the inductor body, the materials have a good electromagnetic shielding effect, and the electromagnetic shielding effect is good. The common-mode noise is reduced and the consistency and symmetry of the winding are ensured in a mode of symmetrically winding the annular inductor, and in the aspect of optimization of a packaging structure, a flip chip technology is adopted, a chip is directly welded on a substrate, and the length of a lead and parasitic inductance are reduced, so that the packaging structure can be optimized without remarkably increasing the size and the cost. The electromagnetic noise of the inductor is effectively reduced by improving the packaging material and process, and the overall performance and reliability of the inductor are improved.

The present disclosure relates to the technical field of semiconductor manufacturing, and in particular to an LED chip and a preparation method thereof, including: a substrate, an epitaxial layer, a current blocking layer, a current spreading layer, a first P-type electrode, a first N-type electrode, a first insulation layer, a second P-type electrode, a second N-type electrode, a second insulation layer, a third P-type electrode, a third N-type electrode, a P-type pad and a N-type pad. As for the LED chip, the electrode design of the flip chip is improved and a third N-type electrode and a third P-type electrode are added. The third N-type electrode and the P-type pad have no overlap spatially, similarly, the third P-type electrode and the N-type pad have no overlap spatially.

The application provides a flip LED chip and a manufacturing method thereof. The method comprises the following steps: placing a tin electrode of an LED wafer upwards and fixing the LED wafer on a carrier; controlling rotation of a scraping disc on a grinding workpiece table and moving the scraping disc to a position directly above the tin electrode; when the rotation speed of the scraping disc reaches a working speed, moving the carrier to the direction of the grinding workpiece table; when the scraping disc contacts the tin electrode, entering a preparation state; and controlling the carrier to enter a working state from the preparation state, wherein the working state is that the carrier moves at a constant speed to the grinding workpiece table by a certain distance so that the scraping disc contacts the tin electrode and grinding is completed. The method provided by the application can solve the problem of large height difference of the tin electrode prepared by a tin brushing process on a metal bonding layer of a flip LED chip in the prior art.

The invention provides a flyer-improved light-emitting diode and a preparation method thereof, and belongs to the technical field of photoelectron manufacturing. The preparation method comprises the following steps: placing a substrate on a graphite plate of a reaction cavity; the growth atmosphere of the reaction cavity is adjusted, an NAl defect barrier layer grows on the substrate, the growth atmosphere of the reaction cavity comprises reaction gas and carrier gas, the reaction gas comprises ammonia gas, the carrier gas comprises nitrogen gas, and the ratio of the volume of the nitrogen gas to the volume of the ammonia gas is smaller than or equal to 3.5; and growing an epitaxial layer on the NAl defect barrier layer. According to the embodiment of the invention, the probability of sheet flying can be reduced in the process of growing the NAl defect barrier layer, and the substrate or the graphite disc is prevented from being damaged.

The invention relates to a light emitting assembly based on a flip chip technology, which comprises a PCB (Printed Circuit Board), a laser, a silicon optical chip and a DSP (Digital Signal Processor) chip, the silicon optical chip and the DSP chip are arranged on one side of the PCB, the laser is positioned on the other side of the PCB, and laser emitted by the laser is coupled into the silicon optical chip; the PCB is provided with a hollow window, a heat dissipation block is arranged in the hollow window, and the laser is arranged on the heat dissipation block. The invention further provides an optical module based on the flip chip technology. The silicon optical chip and the DSP chip are both arranged on one side of the PCB, and the laser is arranged on the other side of the PCB, so that heat generated by the laser can be guided to the side of the DSP chip through the heat dissipation block, coplanar heat dissipation of the laser and the DSP chip is achieved, the laser and the DSP chip are both subjected to heat dissipation in the direction of the main heat dissipation face of the optical module, and the heat dissipation efficiency of the optical module is improved. Therefore, the high-temperature power consumption of the optical module is reduced, the junction temperature of the laser during high-temperature working is reduced, and the output power is further increased.

A light emitting diode (LED) structure that includes a stent substrate; and a circuit having a plurality of contact pads arranged along a length of the stent substrate. The structure further includes a plurality of light emitting diode (LED) chips, wherein each light emitting diode chip in the plurality of chips is engaged to a set of contact pads along the length of the metal stent substrate. A continuous phosphor layer is present overlying the plurality of light emitting diode (LED) chips, the continuous phosphor layer including first portions that are in direct contact with at least a light transmission surface of the light emitting diode (LED) chips and second portions that bridge across the space separating adjacently positioned light emitting diode. An encapsulant present over the continuous phosphor layer that is covering at least the light emitting diode chips.

The present application relates to the technical field of LED packaging, and particularly relates to a CSP device with global metal pads and a preparation method and application thereof, comprising: a super-thin aluminum substrate, one side surface of the super-thin aluminum substrate is provided with an enlarged electrode pad, the enlarged electrode pad and the super-thin aluminum substrate are integrated; the surface of the super-thin aluminum substrate is provided with a first bonding layer; a flip chip, one side surface of the flip chip is provided with a metal layer, the metal layer is sequentially stacked with an adhesive metal layer, a barrier layer and a second bonding layer from the direction close to the flip chip to the direction away from the flip chip; the first bonding layer and the second bonding layer are bonded and connected; and an encapsulation layer is used for covering the super-thin aluminum substrate, the flip chip and the bonding and connecting area. The scheme effectively overcomes inherent defects such as poor heat dissipation, low welding reliability and insufficient structural stability in the traditional process, significantly improves the comprehensive performance of the device, and meets the use requirements of Mini CSP direct SMT patch and other application scenarios.