86 results about "Chip-scale package" patented technology

The invention relates to the technical field of chip-scale packaging, in particular to a chip-scale LED device packaging method and system, and the method comprises the steps: collecting bonding point surface topography data, extracting key parameters, calculating a fracture toughness predicted value, generating a bonding pressure dynamic compensation amount when the fracture toughness predicted value is lower than a lower threshold value, and generating a bonding angle composite correction amount when the fracture toughness predicted value exceeds an upper threshold value. And acquiring light intensity distribution data based on the correction amount, generating a dynamic correction amount of lens curvature, calculating a packaging body inclination angle adjustment proportion, and generating a global adaptation amount. By collecting surface morphology data of the bonding point and extracting multiple key parameters, the fracture toughness prediction accuracy is improved, the bonding pressure is dynamically adjusted to strengthen the interface stability, the bonding angle is corrected in combination with morphology feedback, local stress concentration is relieved, the lens curvature is corrected in real time based on light intensity distribution change, and light spot center offset is accurately controlled; the inclination angle parameter is synchronously corrected in combination with the mapping relation between the packaging body inclination angle and the bonding point density, and the packaging optical consistency and the structural integrity are effectively improved.

The invention provides a multi-level PDN modeling optimization method and system based on advanced packaging, and belongs to the technical field of electrical packaging design, and the method comprises the steps: in multi-level packaging including a chip level, a packaging substrate level and a PCB level, under the condition that actual electromagnetic parameters, power supply layout, wiring topology and the actual length of a power supply loop of materials are considered, the actual length of the power supply loop is calculated; obtaining a PDN model for completing voltage stability and power supply capability under each level; through a three-dimensional loop path mapping algorithm and a target impedance rule, obtaining a PDN model of stable power supply of a power supply network in a full frequency band under different levels; obtaining a plurality of PDN optimization models under each level; and inputting one model under each level into the simulation tool at the same time to obtain an optimal PDN model under each level. The invention aims to solve the problem that only the mutual influence between electronic devices in the PDN model of each layer is considered when the PDN model is carried out on a PCB (Printed Circuit Board), a semiconductor and a chip.

A multi-chip package includes: a first semiconductor integrated-circuit (IC) chip; a second semiconductor integrated-circuit (IC) chip over and bonded to the first semiconductor integrated-circuit (IC) chip; a plurality of first metal posts over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the plurality of first metal posts are in a space beyond and extending from a sidewall of the second semiconductor integrated-circuit (IC) chip; and a first polymer layer over the first semiconductor integrated-circuit (IC) chip and in the space, wherein the plurality of first metal posts are in the first polymer layer, wherein a top surface of the first polymer layer, a top surface of the second semiconductor integrated-circuit (IC) chip and a top surface of each of the plurality of first metal posts are coplanar.

The utility model relates to the technical field of backlight display equipment, and provides a CSP (Chip Scale Package) backlight source double-layer packaging structure, which comprises a substrate provided with a light-emitting circuit; the CSP comprises a packaging structure and a light-emitting chip arranged in the packaging structure, the light-emitting chip is arranged on the substrate and electrically connected with the light-emitting circuit, and the light-emitting chip is a Mini LED; the packaging adhesive layer comprises a first adhesive layer and a second adhesive layer, the first adhesive layer is connected to the substrate in a sealed mode and wraps the CSP package, a first gap is formed between the first adhesive layer and the CSP package, the second adhesive layer is connected to the substrate, and the first gap is filled with the second adhesive layer and sealed by the second adhesive layer; the first glue layer and the second glue layer are transparent shells formed through glue dispensing and curing of a glue dispenser. According to the CSP backlight source double-layer packaging structure, air gaps between the first adhesive layer and the CSP packaging and between the first adhesive layer and the second adhesive layer can be eliminated, meanwhile, the risk that the CSP backlight source is eroded by water vapor is eliminated, and the effect of improving the light emitting quality of the CSP backlight source is achieved.

An LED includes a first composite layer on a first of its doped layers. Primary vias extend through the first composite layer, through the first doped layer and active region of the LED, and into a second doped layer thereof. A second composite layer (TCO, dielectric, multilayer reflector, and metal layers) is positioned on the second doped layer within the primary vias, on lateral surfaces of the primary vias, and on portions of the first composite layer. A dielectric spacer layer separates the first composite layer, the first doped layer, and the active region from the second composite layer. The TCO layer includes embedded electrical contact areas outside the primary vias, each being separated from the first doped layer by the first composite layer and the dielectric spacer layer. The second composite layer within the primary vias increases LED luminance (by reducing absorption, increasing reflectivity, and reducing darkening or dimming).

The utility model relates to the technical field of backlight of display equipment, and provides a CSP backlight source and a display device. The CSP backlight comprises: a substrate comprising a light emitting circuit; the light-emitting packaging part is arranged on the substrate, electrically connected with the light-emitting circuit and comprises a blue light chip and a red-green fluorescence conversion layer which are sequentially stacked from bottom to top, and the red-green fluorescence conversion layer at least covers the blue light chip and is used for converting and mixing light emitted by the blue light chip so as to emit white light; the light-emitting packaging piece is manufactured through a chip scale package (CSP) technology; the diffusion reflection layer covers the light-emitting packaging piece in a gapless mode, the diffusion reflection layer comprises a cup-shaped diffusion part and a reflection part arranged on the periphery of the diffusion part, and the diffusion powder concentration of the central area of the diffusion part is larger than that of the edge area of the diffusion part; and the lens covers the diffusion reflection layer in a gapless manner.

The embodiment of the invention provides a wafer-level chip packaging structure and electronic equipment, relates to the field of semiconductors, and aims to improve the transmission performance between chips. The wafer-level chip packaging structure comprises an adapter plate and a wafer-level chip. The adapter plate comprises a first rewiring layer and a second rewiring layer which are arranged in a stacked mode, the first rewiring layer comprises an optical interconnection channel, and the second rewiring layer comprises an electric interconnection channel. The wafer level chip is arranged on the adapter plate. The wafer level chip includes a plurality of device regions, each device region including at least one chip. Along a first direction parallel to the adapter plate, the chips in the two adjacent device regions are connected through an electric interconnection channel, and the chips in the two device regions at the two ends are connected through an optical interconnection channel. Along a second direction parallel to the adapter plate, the chips in the two adjacent device regions are connected through an electric interconnection channel, the chips in the two device regions at the two ends are connected through an optical interconnection channel, and the first direction and the second direction are crossed.

The chip-level package photodiode of the present invention has a first conductive layer located on a first side of the photodiode. A first contact is located on a second side of the chip-level package photodiode. A dopant diffusion layer is formed between the first conductive layer and the first contact to electrically connect the first conductive layer to the first contact. The dopant diffusion layer extends from the first side of the chip-level package photodiode through the entire depletion zone of the chip-level package photodiode to the second side of the chip-level package photodiode.

A surface acoustic wave (SAW) wafer-level package is disclosed, comprising: a substrate; an interdigitated transducer (IDT) formed on the substrate; a sidewall formed on the substrate along the periphery of the IDT; a cover formed on the sidewall and above the IDT to form a hollow portion with the sidewall above the IDT; a connecting electrode formed on the substrate, electrically connected to the IDT and extending outward from the periphery of the sidewall; a connecting terminal electrically connected to the portion of the connecting electrode extending outward from the periphery of the sidewall, formed as an outer surface covering the sidewall and a surface and a portion of the top surface of the cover, and having a top surface formed above the top surface of the cover; and an organic solderable corrosion protectant (OSP) coating formed at least on the top surface of the connecting terminal.

In examples, a semiconductor package comprises a wafer chip scale package (WCSP) having circuitry formed in a device side and an insulative layer above the device side. The WCSP includes one or more plated walls extending vertically to form a defined space, the one or more plated walls configured to prevent mold compound from flowing into the defined space. The WCSP includes mold compound abutting surfaces of the one or more plated walls opposing the defined space. The WCSP includes a conductive terminal coupled to the circuitry and extending from the WCSP into the defined space.

A microelectronic device includes a die with input / output (I / O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I / O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I / O terminals, and a head contacting the column at an opposite end of the column from the I / O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

The invention relates to industrial chip scale packaging for microelectronic devices. A microelectronic device (100) includes a die (102) having input / output (I / O) terminals (104) and a dielectric layer (106) on the die (102). The microelectronic device (100) includes a conductive strut (110) electrically coupled to the I / O terminal (104) and extending through the dielectric layer (106) to an exterior of the microelectronic device (100). Each post (110) includes a post (112) electrically coupled to one of the I / O terminals (104), and a head (114) contacting the post (112) at an end of the post (112) opposite the I / O terminal (104). The head (114) extends laterally beyond the post (112) in at least one lateral direction.

The application relates to the technical field of semiconductor chip production, and discloses a continuous production device and a continuous production process of a reel chip level packaging module, which comprises a tin paste printing structure, a flip chip structure, a reflow soldering structure and a filling and solidifying structure. The tin paste printing structure is used for conveying a reel carrier tape and printing tin paste on the reel carrier tape. The flip chip structure is arranged downstream of the tin paste printing structure, and is used for overturning chips to flip the chips on the reel carrier tape after the tin paste is printed. The reflow soldering structure is arranged downstream of the flip chip structure, and is used for reflow soldering the reel carrier tape with the flipped chips. The filling and solidifying structure is arranged downstream of the reflow soldering structure, and is used for bottom glue filling and solidification of the module after the reflow soldering is completed. The structure completes the reel carrier tape type chip production, and meets the large-scale and high-efficiency production demand.

A semiconductor package comprises two or more chips, a first molding layer, a second molding layer, a third molding layer, a fourth molding layer, a bottom redistribution layer (RDL), a middle RDL, and a top RDL. The two or more chips comprise a first chip and a second chip. The top RDL comprises a first copper plate and a second copper plate. A plurality of vias electrically connect the second copper plate to the second chip. A method comprises the steps of preparing two or more chips; forming a chip-level molding layer; forming a middle RDL; forming a lower-level molding layer; forming a bottom RDL; forming a lowest-level molding layer; forming a top RDL; and forming a top-level molding layer so as to fabricate a semiconductor package.

The present invention discloses a fan-out package structure and a packaging method for embedding a sensor or display chip, and relates to the field of semiconductor processing technology. The method comprises the following steps: 1) making a chip-level package; 2) making a fan-out package; 3) adhering and assembling a plurality of chip-level packages to a first glass carrier; 4) processing a second mold resin layer on the outside of each fan-out package, making a plurality of third RDL layers corresponding to each fan-out package on the second mold resin layer, providing a third copper bump at the contact point of the top third RDL layer, and implanting solder balls at the third copper bump to obtain an initial product; and 5) separating the first glass carrier and then cutting the initial product into individual chips. The present invention embeds a plurality of chip-level packages in the mold resin. Because the coplanarity of the plurality of chip-level packages is not changed by subsequent processes, and because multiple chips are encapsulated in the same package, the volume of the system can be reduced.

A wafer level chip scale package (WLCSP) with portions that have different thicknesses. A first passive surface of a die in the WLSCP includes a plurality of surfaces. The plurality of surfaces may include inclined surfaces or flat surfaces. Thicker portions of die, with more semiconductor material remaining are non-critical portions that increase a WLCSP's strength for further processing and handling after formation, and the thinner portions are critical portions that reduce a Coefficient of Thermal Expansion (CTE) mismatch between a WLCSP and a PCB.

The utility model discloses a kind of chip level packaging structures of MiniLED display module, including cooling combination package shell, the cooling combination package shell is wrapped in the outside of MiniLED display module;MiniLED display module package base plate and its top LED chip, the cooling combination package shell includes upper annular plate and lower annular plate, the inside of the lower annular plate is equipped with refrigeration plate, the refrigeration surface of the refrigeration plate is towards the base plate;The chip level packaging structure of this MiniLED display module is wrapped by stratification, accurate heat dissipation, sealing buffer etc. Design, realizes the efficient heat dissipation, firm protection and convenient maintenance of MiniLED display module, significantly improves the working stability of module, service life and assembly efficiency.

The invention provides a packaging method of a VCSEL chip device, and relates to the technical field of semiconductor laser packaging. The method comprises the following steps of: copying a micro lens array at one time on the back surface of a VCSEL (Vertical Cavity Surface Emitting Laser) wafer on which a front electrode is completed by utilizing wafer-level UV (Ultraviolet) nano-imprinting, so that the optical center of a micro lens is self-aligned with the center of an active area of a light-emitting unit, and meanwhile, realizing light beam shaping and wafer-level mechanical protection; cutting the wafer into single chips, directly bonding front electrodes of the chips to a metal bonding pad of a driving IC (integrated circuit) in a flip-chip bonding manner, enabling the back surfaces of the chips to become final light-emitting surfaces, and synchronously establishing electric connection and a low-thermal-resistance heat dissipation channel; and finally, low-modulus bottom filling glue is injected between the chip and the driving IC, and high-transmission transparent epoxy resin is coated on the periphery of the chip and above the micro lenses on the back surface to form a chip-scale packaging body without a shell. Through the steps, alignment and forming of the micro lens are completed in the wafer stage, and the packaging thickness and the optical loss are remarkably reduced.

The utility model relates to the technical field of backlight of display equipment, and provides a CSP backlight source. The CSP backlight comprises: a substrate comprising a light emitting circuit; the light-emitting packaging part is arranged on the substrate, electrically connected with the light-emitting circuit and comprises a blue light chip and a red-green fluorescence conversion layer which are sequentially stacked from bottom to top, and the red-green fluorescence conversion layer at least covers the blue light chip and is used for converting and mixing light emitted by the blue light chip so as to emit white light; the light-emitting packaging piece is manufactured through a chip scale package (CSP) technology; the lens layer covers the light-emitting packaging piece in a gapless manner; and the blue light filter lens is arranged above the lens layer.

The invention discloses a cutting fluid and application and device thereof in chip scale packaging LED cutting, and relates to the technical field of LED packaging technologies, the cutting fluid is fluorocarbon liquid which is not mutually soluble with water, the cutting fluid serves as a cutting medium and is used for cutting a chip scale packaging LED of which a packaging body contains fluoride fluorescent powder, and the cutting fluid is used for cutting the chip scale packaging LED of which the packaging body contains fluoride fluorescent powder. The fluorocarbon liquid which is high in chemical inertness and is not mutually soluble with water is used as a cutting medium instead of pure water, so that the hydrolysis reaction of the fluorescent powder and the generation of corrosive byproducts are radically eradicated, the crystal structure of the fluorescent powder is effectively protected, and the long-term reliability and the service life of a device are improved.

A semiconductor device, an optical receiver, and a manufacturing method for a photodetector are disclosed. The semiconductor device comprises a photodetector die, and the photodetector die comprises a main body, a second electrode, and a protective layer. The main body comprises a first electrode, and the first electrode comprises a first surface. The second electrode is at least partially formed on the first surface of the first electrode, and the protective layer comprises a first part configured to at least partially cover the joint of the edge of the second electrode and the main body of the photodetector. The first part comprises a first opening to expose part of the area of the second electrode as a wire bonding area. According to the photodetector die structure of the semiconductor device, the isolation between a chip internal circuit and a chip wiring position and an external environment can be achieved, the stability of a wire bonding structure can be improved, the requirement of the automotive grade on the chip-level packaging process of a photodetector is reduced, and the packaging cost is reduced.

The invention provides a wafer-level chip packaging structure and electronic equipment, relates to the field of semiconductors, and aims to solve the problems of low bandwidth density, poor signal integrity, long transmission delay and the like of electric signals in a wafer when the physical distance is relatively long. The wafer-level chip packaging structure comprises an adapter plate and a wafer-level chip. The adapter plate comprises a first rewiring layer and a second rewiring layer which are stacked, the first rewiring layer comprises an optical interconnection channel, and the second rewiring layer comprises an electric interconnection channel; the wafer-level chip is arranged on the adapter plate; the wafer-level chip comprises a plurality of device areas, each device area comprises a plurality of computing power chips and an exchange chip, and each computing power chip is electrically connected with the exchange chip through an electric interconnection channel; the switching chip of one device area is connected with the switching chip of the other device area through an optical interconnection channel. According to the invention, the interconnection bandwidth of the whole system is improved, and the overall communication efficiency can be improved.

The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor through hole, a semiconductor interposer and a preparation method of the semiconductor interposer. The invention provides a preparation method of a semiconductor interposer, which comprises the following steps of: forming lattice defects in a preset through hole region of a semiconductor substrate, and growing an epitaxial semiconductor material layer; selectively removing the amorphous or polycrystalline semiconductor material in the preset through hole region through a corrosion process to obtain a semiconductor intermediate layer through hole; filling the through hole with metal to form a conductive through hole; and thinning the second surface of the semiconductor substrate until the conductive through hole penetrates through the remaining semiconductor substrate and the epitaxial semiconductor material layer to form a semiconductor intermediate layer. According to the method, local internal stress generated by deep reactive ion etching or laser through holes is fundamentally avoided, etching damage to the inner walls of the through holes is reduced, the integrity of the semiconductor interposer is remarkably improved, and the risks of warping, internal stress and even breakage of high wafer level or chip level packaging are fundamentally reduced.

The present disclosure is directed to a package (e.g., a chip scale package, a wafer level chip scale package (WLCSP), or a package containing a sensor die) with a sensor die on a substrate (e.g., an application-specific integrated circuit die (ASIC), an integrated circuit, or some other type of die having active circuitry) and encased in a molding compound. The sensor die includes a sensing component that is aligned with a centrally located opening that extends through the substrate. The centrally located opening extends through the substrate at an inactive portion of the substrate. The centrally located opening exposes the sensing component of the sensor die to an external environment outside the package.

To reduce processing costs by a cheap manufacturing process in wafer level packaging.SOLUTION: An assembly 300 includes a substrate 304 having opposing first and second surfaces, a device-on-substrate 316 on a first surface 318 of the substrate, a wafer cap 302 on the first surface of the substrate above the device-on-substrate, and a fusible alloy 305 with a peripheral ring layer 320 hermetically sealing the wafer cap 302 to the first surface 318 of the substrate around the device-on-substrate. The connection of the wafer cap 302 to the peripheral ring layer 320 can be implemented as a die-level packaging process rather than using a wafer-level process, thereby reducing manufacturing costs.SELECTED DRAWING: Figure 3

The invention relates to the technical field of chip testing, and discloses CSP packaging chip testing equipment which comprises a processing bin, a conveyor is installed in the processing bin, an operation table is arranged at the tail end of the conveyor, and a lifting table is installed at the top end of the operation table. According to the CSP chip testing equipment, detection is carried out based on the surface spiral moving track of the solder ball, the detection accuracy is greatly improved, a semicircular straight gear is driven to form a motion mode of self-rotation and revolution around a shaft through a composite transmission structure of the spherical surface transposition assembly, the probe assembly is driven to move along the outer spherical surface of the solder ball in a spiral track mode, and the detection accuracy is greatly improved. The single detection limitation of vertical contact of traditional equipment is thoroughly broken through, the problem of unstable electrical connection caused by a local oxide layer of the solder ball can be effectively avoided through the multi-point sampling mode, the surface detection point positions of the solder ball are comprehensively covered, the chip performance misjudgment risk caused by single-point contact misjudgment is remarkably reduced, and the real electrical performance state of the chip is precisely restored.

The invention relates to the technical field of chip packaging, in particular to a silica gel film for CSP (Chip Scale Package) as well as a preparation method and application of the silica gel film. The coating comprises the following components in percentage by weight: 30-50% of organic silicon resin, 20-50% of modified glass powder and 20-50% of fluorescent powder, the preparation raw materials of the modified glass powder comprise a modifier and glass powder, and the modifier comprises 20-50wt% of a silane coupling agent, 30-50wt% of an organic solvent and 20-50wt% of water. The prepared silica gel film is applied to CSP surface mounting of a Mini LED, the light transmittance is larger than 97%, the color tolerance is smaller than or equal to 3, and the material throwing rate is smaller than 2%.

The invention discloses a chip-scale packaging structure of a power chip and a packaging process thereof, the chip-scale packaging structure comprises a metal substrate and the power chip, and the metal substrate comprises a chip carrier area and a back lead-out ball mounting area. The height of the chip carrying table area is lower than that of the back lead-out ball mounting area, the height difference between the chip carrying table area and the back lead-out ball mounting area is matched with the thickness of the power chip, and the power chip is arranged on the upper side of the chip carrying table area. The method is suitable for a high-density integration scene, the metal substrate provides large current bearing capacity, and the welding ball array distribution optimizes the current distribution uniformity.