51 results about "Chip-scale package" patented technology

The utility model relates to the technical field of backlight display equipment, and provides a CSP (Chip Scale Package) backlight source double-layer packaging structure, which comprises a substrate provided with a light-emitting circuit; the CSP comprises a packaging structure and a light-emitting chip arranged in the packaging structure, the light-emitting chip is arranged on the substrate and electrically connected with the light-emitting circuit, and the light-emitting chip is a Mini LED; the packaging adhesive layer comprises a first adhesive layer and a second adhesive layer, the first adhesive layer is connected to the substrate in a sealed mode and wraps the CSP package, a first gap is formed between the first adhesive layer and the CSP package, the second adhesive layer is connected to the substrate, and the first gap is filled with the second adhesive layer and sealed by the second adhesive layer; the first glue layer and the second glue layer are transparent shells formed through glue dispensing and curing of a glue dispenser. According to the CSP backlight source double-layer packaging structure, air gaps between the first adhesive layer and the CSP packaging and between the first adhesive layer and the second adhesive layer can be eliminated, meanwhile, the risk that the CSP backlight source is eroded by water vapor is eliminated, and the effect of improving the light emitting quality of the CSP backlight source is achieved.

An LED includes a first composite layer on a first of its doped layers. Primary vias extend through the first composite layer, through the first doped layer and active region of the LED, and into a second doped layer thereof. A second composite layer (TCO, dielectric, multilayer reflector, and metal layers) is positioned on the second doped layer within the primary vias, on lateral surfaces of the primary vias, and on portions of the first composite layer. A dielectric spacer layer separates the first composite layer, the first doped layer, and the active region from the second composite layer. The TCO layer includes embedded electrical contact areas outside the primary vias, each being separated from the first doped layer by the first composite layer and the dielectric spacer layer. The second composite layer within the primary vias increases LED luminance (by reducing absorption, increasing reflectivity, and reducing darkening or dimming).

The utility model relates to the technical field of backlight of display equipment, and provides a CSP backlight source and a display device. The CSP backlight comprises: a substrate comprising a light emitting circuit; the light-emitting packaging part is arranged on the substrate, electrically connected with the light-emitting circuit and comprises a blue light chip and a red-green fluorescence conversion layer which are sequentially stacked from bottom to top, and the red-green fluorescence conversion layer at least covers the blue light chip and is used for converting and mixing light emitted by the blue light chip so as to emit white light; the light-emitting packaging piece is manufactured through a chip scale package (CSP) technology; the diffusion reflection layer covers the light-emitting packaging piece in a gapless mode, the diffusion reflection layer comprises a cup-shaped diffusion part and a reflection part arranged on the periphery of the diffusion part, and the diffusion powder concentration of the central area of the diffusion part is larger than that of the edge area of the diffusion part; and the lens covers the diffusion reflection layer in a gapless manner.

The embodiment of the invention provides a wafer-level chip packaging structure and electronic equipment, relates to the field of semiconductors, and aims to improve the transmission performance between chips. The wafer-level chip packaging structure comprises an adapter plate and a wafer-level chip. The adapter plate comprises a first rewiring layer and a second rewiring layer which are arranged in a stacked mode, the first rewiring layer comprises an optical interconnection channel, and the second rewiring layer comprises an electric interconnection channel. The wafer level chip is arranged on the adapter plate. The wafer level chip includes a plurality of device regions, each device region including at least one chip. Along a first direction parallel to the adapter plate, the chips in the two adjacent device regions are connected through an electric interconnection channel, and the chips in the two device regions at the two ends are connected through an optical interconnection channel. Along a second direction parallel to the adapter plate, the chips in the two adjacent device regions are connected through an electric interconnection channel, the chips in the two device regions at the two ends are connected through an optical interconnection channel, and the first direction and the second direction are crossed.

A surface acoustic wave (SAW) wafer-level package is disclosed, comprising: a substrate; an interdigitated transducer (IDT) formed on the substrate; a sidewall formed on the substrate along the periphery of the IDT; a cover formed on the sidewall and above the IDT to form a hollow portion with the sidewall above the IDT; a connecting electrode formed on the substrate, electrically connected to the IDT and extending outward from the periphery of the sidewall; a connecting terminal electrically connected to the portion of the connecting electrode extending outward from the periphery of the sidewall, formed as an outer surface covering the sidewall and a surface and a portion of the top surface of the cover, and having a top surface formed above the top surface of the cover; and an organic solderable corrosion protectant (OSP) coating formed at least on the top surface of the connecting terminal.

In examples, a semiconductor package comprises a wafer chip scale package (WCSP) having circuitry formed in a device side and an insulative layer above the device side. The WCSP includes one or more plated walls extending vertically to form a defined space, the one or more plated walls configured to prevent mold compound from flowing into the defined space. The WCSP includes mold compound abutting surfaces of the one or more plated walls opposing the defined space. The WCSP includes a conductive terminal coupled to the circuitry and extending from the WCSP into the defined space.

A microelectronic device includes a die with input / output (I / O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I / O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I / O terminals, and a head contacting the column at an opposite end of the column from the I / O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

The invention relates to industrial chip scale packaging for microelectronic devices. A microelectronic device (100) includes a die (102) having input / output (I / O) terminals (104) and a dielectric layer (106) on the die (102). The microelectronic device (100) includes a conductive strut (110) electrically coupled to the I / O terminal (104) and extending through the dielectric layer (106) to an exterior of the microelectronic device (100). Each post (110) includes a post (112) electrically coupled to one of the I / O terminals (104), and a head (114) contacting the post (112) at an end of the post (112) opposite the I / O terminal (104). The head (114) extends laterally beyond the post (112) in at least one lateral direction.

The application relates to the technical field of semiconductor chip production, and discloses a continuous production device and a continuous production process of a reel chip level packaging module, which comprises a tin paste printing structure, a flip chip structure, a reflow soldering structure and a filling and solidifying structure. The tin paste printing structure is used for conveying a reel carrier tape and printing tin paste on the reel carrier tape. The flip chip structure is arranged downstream of the tin paste printing structure, and is used for overturning chips to flip the chips on the reel carrier tape after the tin paste is printed. The reflow soldering structure is arranged downstream of the flip chip structure, and is used for reflow soldering the reel carrier tape with the flipped chips. The filling and solidifying structure is arranged downstream of the reflow soldering structure, and is used for bottom glue filling and solidification of the module after the reflow soldering is completed. The structure completes the reel carrier tape type chip production, and meets the large-scale and high-efficiency production demand.

A semiconductor package comprises two or more chips, a first molding layer, a second molding layer, a third molding layer, a fourth molding layer, a bottom redistribution layer (RDL), a middle RDL, and a top RDL. The two or more chips comprise a first chip and a second chip. The top RDL comprises a first copper plate and a second copper plate. A plurality of vias electrically connect the second copper plate to the second chip. A method comprises the steps of preparing two or more chips; forming a chip-level molding layer; forming a middle RDL; forming a lower-level molding layer; forming a bottom RDL; forming a lowest-level molding layer; forming a top RDL; and forming a top-level molding layer so as to fabricate a semiconductor package.

The utility model discloses a kind of chip level packaging structures of MiniLED display module, including cooling combination package shell, the cooling combination package shell is wrapped in the outside of MiniLED display module;MiniLED display module package base plate and its top LED chip, the cooling combination package shell includes upper annular plate and lower annular plate, the inside of the lower annular plate is equipped with refrigeration plate, the refrigeration surface of the refrigeration plate is towards the base plate;The chip level packaging structure of this MiniLED display module is wrapped by stratification, accurate heat dissipation, sealing buffer etc. Design, realizes the efficient heat dissipation, firm protection and convenient maintenance of MiniLED display module, significantly improves the working stability of module, service life and assembly efficiency.

The utility model relates to the technical field of backlight of display equipment, and provides a CSP backlight source. The CSP backlight comprises: a substrate comprising a light emitting circuit; the light-emitting packaging part is arranged on the substrate, electrically connected with the light-emitting circuit and comprises a blue light chip and a red-green fluorescence conversion layer which are sequentially stacked from bottom to top, and the red-green fluorescence conversion layer at least covers the blue light chip and is used for converting and mixing light emitted by the blue light chip so as to emit white light; the light-emitting packaging piece is manufactured through a chip scale package (CSP) technology; the lens layer covers the light-emitting packaging piece in a gapless manner; and the blue light filter lens is arranged above the lens layer.

The invention discloses a cutting fluid and application and device thereof in chip scale packaging LED cutting, and relates to the technical field of LED packaging technologies, the cutting fluid is fluorocarbon liquid which is not mutually soluble with water, the cutting fluid serves as a cutting medium and is used for cutting a chip scale packaging LED of which a packaging body contains fluoride fluorescent powder, and the cutting fluid is used for cutting the chip scale packaging LED of which the packaging body contains fluoride fluorescent powder. The fluorocarbon liquid which is high in chemical inertness and is not mutually soluble with water is used as a cutting medium instead of pure water, so that the hydrolysis reaction of the fluorescent powder and the generation of corrosive byproducts are radically eradicated, the crystal structure of the fluorescent powder is effectively protected, and the long-term reliability and the service life of a device are improved.

The invention provides a wafer-level chip packaging structure and electronic equipment, relates to the field of semiconductors, and aims to solve the problems of low bandwidth density, poor signal integrity, long transmission delay and the like of electric signals in a wafer when the physical distance is relatively long. The wafer-level chip packaging structure comprises an adapter plate and a wafer-level chip. The adapter plate comprises a first rewiring layer and a second rewiring layer which are stacked, the first rewiring layer comprises an optical interconnection channel, and the second rewiring layer comprises an electric interconnection channel; the wafer-level chip is arranged on the adapter plate; the wafer-level chip comprises a plurality of device areas, each device area comprises a plurality of computing power chips and an exchange chip, and each computing power chip is electrically connected with the exchange chip through an electric interconnection channel; the switching chip of one device area is connected with the switching chip of the other device area through an optical interconnection channel. According to the invention, the interconnection bandwidth of the whole system is improved, and the overall communication efficiency can be improved.

The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor through hole, a semiconductor interposer and a preparation method of the semiconductor interposer. The invention provides a preparation method of a semiconductor interposer, which comprises the following steps of: forming lattice defects in a preset through hole region of a semiconductor substrate, and growing an epitaxial semiconductor material layer; selectively removing the amorphous or polycrystalline semiconductor material in the preset through hole region through a corrosion process to obtain a semiconductor intermediate layer through hole; filling the through hole with metal to form a conductive through hole; and thinning the second surface of the semiconductor substrate until the conductive through hole penetrates through the remaining semiconductor substrate and the epitaxial semiconductor material layer to form a semiconductor intermediate layer. According to the method, local internal stress generated by deep reactive ion etching or laser through holes is fundamentally avoided, etching damage to the inner walls of the through holes is reduced, the integrity of the semiconductor interposer is remarkably improved, and the risks of warping, internal stress and even breakage of high wafer level or chip level packaging are fundamentally reduced.

The present disclosure is directed to a package (e.g., a chip scale package, a wafer level chip scale package (WLCSP), or a package containing a sensor die) with a sensor die on a substrate (e.g., an application-specific integrated circuit die (ASIC), an integrated circuit, or some other type of die having active circuitry) and encased in a molding compound. The sensor die includes a sensing component that is aligned with a centrally located opening that extends through the substrate. The centrally located opening extends through the substrate at an inactive portion of the substrate. The centrally located opening exposes the sensing component of the sensor die to an external environment outside the package.

The invention relates to the technical field of chip testing, and discloses CSP packaging chip testing equipment which comprises a processing bin, a conveyor is installed in the processing bin, an operation table is arranged at the tail end of the conveyor, and a lifting table is installed at the top end of the operation table. According to the CSP chip testing equipment, detection is carried out based on the surface spiral moving track of the solder ball, the detection accuracy is greatly improved, a semicircular straight gear is driven to form a motion mode of self-rotation and revolution around a shaft through a composite transmission structure of the spherical surface transposition assembly, the probe assembly is driven to move along the outer spherical surface of the solder ball in a spiral track mode, and the detection accuracy is greatly improved. The single detection limitation of vertical contact of traditional equipment is thoroughly broken through, the problem of unstable electrical connection caused by a local oxide layer of the solder ball can be effectively avoided through the multi-point sampling mode, the surface detection point positions of the solder ball are comprehensively covered, the chip performance misjudgment risk caused by single-point contact misjudgment is remarkably reduced, and the real electrical performance state of the chip is precisely restored.

The invention discloses a chip-scale packaging structure of a power chip and a packaging process thereof, the chip-scale packaging structure comprises a metal substrate and the power chip, and the metal substrate comprises a chip carrier area and a back lead-out ball mounting area. The height of the chip carrying table area is lower than that of the back lead-out ball mounting area, the height difference between the chip carrying table area and the back lead-out ball mounting area is matched with the thickness of the power chip, and the power chip is arranged on the upper side of the chip carrying table area. The method is suitable for a high-density integration scene, the metal substrate provides large current bearing capacity, and the welding ball array distribution optimizes the current distribution uniformity.

In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.

The application discloses a local thinning method for a polyimide layer in a chip-level packaging structure, which comprises the following steps: protecting the area of the polyimide layer except the area to be thinned; and adopting a dry etching process to thin the area to be thinned of the polyimide layer for multiple times until the color of the polyimide layer in the area to be thinned reaches a transparent state. The polyimide layer in the area to be thinned is thinned for multiple times gradually, so that the thinning amount of the area to be thinned can be well controlled, the thinning success rate is improved, and the re-wiring layer under the polyimide layer is prevented from being damaged due to excessive thinning, so that the integrity of the re-wiring layer is ensured. Meanwhile, the thinning process of the polyimide layer is judged by observing the color of the polyimide layer, the need of cutting the chip-level packaging structure due to the need of detecting the thickness of the polyimide layer is avoided, the integrity of the chip-level packaging structure is ensured, and the subsequent use of the chip-level packaging structure is not affected.

A light emitting filament diode that includes a filament substrate; a plurality of light emitting diodes (LEDs) electrically connected and disposed along a length of the filament substate; and a phosphorus encapsulant present in direct contact with an upper surface and sidewalls of at least one of the plurality of light emitting diodes (LEDs). No portion of phosphorus encapsulant is present overlying a portion of the filament substrate extending between the sidewalls of adjacently situated light emitting diodes having phosphorus encapsulant present thereon. The light emitting filament diode may also include a transparent encapsulant present over at least the light emitting diode chips.

The utility model relates to the technical field of backlight of display equipment, and provides a CSP backlight source. The CSP backlight comprises: a substrate comprising a light emitting circuit; the light-emitting packaging part is arranged on the substrate, electrically connected with the light-emitting circuit and comprises a blue light chip, a light nano material layer and a red-green-fluorescence conversion layer which are sequentially stacked from bottom to top, the light nano material layer at least covers the light-emitting front face of the blue light chip, and the red-green-fluorescence conversion layer at least covers the light nano material layer; the light-emitting packaging piece is used for converting and mixing light emitted by the blue light chip so as to emit white light, and the light-emitting packaging piece is manufactured through a chip scale package (CSP) technology; and the lens layer covers the light-emitting packaging piece in a gapless manner.

A sensor package structure and a chip-scale sensor package structure. The chip-scale sensor package structure includes a sensor chip, a supporting layer having a ring-shape, and a light-permeable layer. A top surface of the sensor chip includes a sensing region and a carrying region that surrounds the sensing region. The supporting layer is disposed on the carrying region, and the light-permeable layer is disposed on the supporting layer through a ring-shaped segment thereof, so that the light-permeable layer, the supporting layer, and the sensor chip jointly define an enclosed space. The ring-shaped segment has a ring-shaped roughened region. A projection space defined by orthogonally projecting the ring-shaped roughened region toward the top surface of the sensor chip is located outside of the sensing region and overlaps an entirety of the supporting layer and a part of the enclosed space.

The utility model relates to the technical field of backlight of display equipment, and provides a CSP (Chip Scale Package) backlight source structure with efficient heat dissipation, which comprises a circuit substrate with a first surface; the plurality of CSP light sources are arranged on the first surface, and the outer side of each CSP light source is covered with an optical lens layer; the heat dissipation layer is arranged between the circuit substrate and the CSP light source; the heat dissipation layer makes contact with the CSP light source and extends to the outer side of the optical lens layer so as to dissipate heat of the CSP light source. The problem that the performance of a light-emitting chip is reduced due to the fact that an existing CSP light source is poor in heat dissipation is solved.

The invention discloses a method for designing a low-power-consumption miniature solid-state relay considering electromagnetic compatibility, which comprises the following steps of: 1, integrating a power switch device and a driving circuit in the same packaging body by adopting a chip scale package (CSP) process, and reducing the volume of a finished product; step 2, constructing a complementary push-pull CMOS drive circuit, and performing dynamic cooperative control through a P-channel MOSFET and an N-channel MOSFET; step 3, designing a three-level EMI protection system; 4, implementing a switching frequency optimization strategy, and fixing the working frequency outside a conduction test frequency band of 134kHz + / -5kHz through a PLL (Phase Locked Loop) technology; 5, adopting a ZVS soft switching technology, and realizing zero-voltage switching-on through parameter matching of a resonant inductor and a capacitor; and 6, thermal management design is executed, an AlN ceramic substrate is matched with 6063-T5 aluminum alloy cooling fins, and the thermal resistance is smaller than or equal to 4.5 DEG C / W. According to the design method of the low-power-consumption miniature solid-state relay considering the electromagnetic compatibility, performance optimization of miniaturization, low power consumption, high electromagnetic compatibility, high efficiency and strong heat dissipation is achieved.

A semiconductor package includes: a semiconductor substrate having a front surface and a back surface opposite the front surface of the semiconductor substrate; a plurality of contact pads attached to the front surface of the semiconductor substrate; a first thick metal layer having a front surface and a back surface opposite to the front surface of the first thick metal layer, the front surface of the first thick metal layer being attached to the back surface of the semiconductor substrate through a seed layer; and a second thick metal layer having a front side and a back side opposite the front side of the second thick metal layer, the front side of the second thick metal layer being attached to the back side of the first thick metal layer; wherein the first thick metal layer and the second thick metal layer are configured as two layers having opposite stress states.

In accordance with various embodiments of the present disclosure, a fan-out wafer-level chip scale package is provided that comprises a semiconductor die having a top side with an active layer, an opposing bottom side, and four peripheral sides; a molding compound surrounding the peripheral sides of the semiconductor die; a redistribution layer at least partially embedded in a dielectric layer and providing a plurality of electrical connections to the semiconductor die; a plurality of solder balls on the redistribution layer, each of the plurality of solder balls providing an electrical connection to a corresponding connection point of the semiconductor die; and a first conductive wall embedded in the molding compound adjacent and substantially parallel to a first one of the peripheral sides of the semiconductor die, the first conductive wall having a top edge in electrical contact with the redistribution layer.

The utility model relates to the technical field of backlight of display equipment, and provides a CSP backlight source and a display device. The CSP backlight comprises: a substrate comprising a light emitting circuit; the light-emitting packaging part is arranged on the substrate, electrically connected with the light-emitting circuit and comprises a near ultraviolet light chip and a composite fluorescence conversion layer which are sequentially stacked from bottom to top, the composite fluorescence conversion layer comprises at least two fluorescence conversion layers, and the composite fluorescence conversion layer at least covers the near ultraviolet light chip; the light-emitting packaging piece is used for converting and mixing light emitted by the near ultraviolet light chip so as to emit white light, and the light-emitting packaging piece is manufactured through a chip scale package (CSP) technology; and the lens layer covers the light-emitting packaging piece in a gapless manner.