591 results about "Chip stacking" patented technology

According to the storage and calculation integrated chip architecture, the chip stacking packaging structure and the terminal equipment, physical tight coupling of storage and calculation is realized through the 3D stacking design of the first storage unit and the logic calculation unit, the problem of physical separation of traditional storage and calculation is solved, the data carrying distance and the cross-chip communication overhead are remarkably reduced, and the communication efficiency is improved. And the chip area and the packaging process complexity are reduced, and the application scenarios of end-side artificial intelligence reasoning and mass data reading and writing are supported. According to the storage and calculation integrated chip architecture, the first storage unit and the logic calculation unit are directly interconnected through the vertical interconnection technology, the data access delay is reduced, the requirement of end side equipment for low delay is met, and the energy efficiency ratio of the storage and calculation integrated chip architecture is remarkably reduced.

The invention provides a memory computing chip and a manufacturing method thereof, which are characterized in that a logic chip with a computing processor, a buffer chip and a DRAM (dynamic random access memory) chip (or a DRAM chip stack) are vertically stacked through silicon through holes, and the chips can be directly communicated through the silicon through holes, so that the chip area can be saved, the integration level is high, the wafer processing difficulty is reduced, and the manufacturing cost is reduced. The logic chip can visit the low-speed DRAM chip in parallel in a large number through the buffer chip, high-bandwidth and large-capacity cache is provided, inter-chip communication between the buffer chip and the logic chip does not need a physical layer interface, and cost of hardware resources is greatly reduced.

Technologies for chip-to-chip (C2C) yield and performance optimization in a die stacking platform are described. One apparatus includes a substrate, a first integrated circuit disposed on the substrate at a first location, a second integrated circuit disposed on the substrate at a second location, and a third integrated circuit disposed on the second integrated circuit. The second integrated circuit is coupled to the first integrated circuit using a first chip-to-chip (C2C) interface via a physical terminal. The third integrated circuit is coupled to the first integrated circuit using a second C2C interface via the physical terminal. Only one of the first C2C interface and the second C2C interface is active at a time.

The invention designs a broadband intermediate-frequency heterogeneous integrated communication transceiving micro module and a three-dimensional packaging method, and belongs to the technical field of advanced packaging. The micro module comprises a TSV silicon adapter plate, a Fan-out module, an HTCC ceramic substrate and a digital chip. The TSV silicon adapter plate adopts a high-resistance silicon substrate, and a coaxial shielding TSV structure is arranged on the TSV silicon adapter plate and comprises an inner layer signal through hole and an outer layer grounding layer. A frequency synthesizer chip and a radio frequency chip are embedded in the Fan-out module, and high-density horizontal interconnection is realized through a plurality of redistribution layers. The HTCC ceramic substrate is of a multi-layer laminated structure, and an impedance matching network is arranged in the HTCC ceramic substrate. The three-dimensional packaging method comprises the steps of TSV silicon adapter plate preparation, Fan-out module processing, digital chip stacking and system-level integration. High-density packaging of the radio frequency chip and the digital chip is achieved through the three-dimensional heterogeneous integrated architecture, and low-loss transmission of broadband signals is guaranteed through the coaxial shielding TSV structure and the impedance matching network.

Stacked semiconductor packages with features to mitigate trace exposer and associated systems and methods are disclosed herein. In some embodiments, the stacked semiconductor package includes a base substrate, a stack of dies carried by the base substrate, and a mold material deposited at least partially encapsulating the stack of dies. The base substrate can include an active surface and a back surface opposite the active surface. Further, the active surface can include one or more cuts into a peripheral portion of the active surface (e.g., stepped structures at the peripheral edges of the base substrate). The base substrate can also include a plurality of bond pads carried by the active surface over the peripheral portion. Still further, the mold material can fill each of the one or more cuts in the active surface, thereby insulating the bond pads from exposure at a sidewall of the stacked semiconductor package.

The invention relates to the technical field of semiconductor packaging and chip power supply, in particular to a three-dimensional chip stacking power supply system and method based on a power wafer, and the system comprises an integrated power wafer, a calculation chip and a power peripheral device. A high-density capacitor array is integrated in the integrated power supply wafer, a rewiring layer is formed on the surface of the integrated power supply wafer, and a distributed voltage regulation module is configured; the computing chip is a known qualified chip and is inversely mounted on the rewiring layer through a micro bump / copper column, and a power supply bonding pad is directly connected with a power supply node; the power supply peripheral device is attached to the free area of the integrated power supply wafer or the same packaging substrate. The method comprises the steps of prefabrication of an integrated power supply wafer, flip mounting of a computing chip, bottom filling and integration with a packaging substrate. Through chip-wafer integration, the power supply path is shortened, resistance and noise are reduced, precision pipe and heterogeneous integration is achieved, the yield is increased, cost is reduced, bidirectional heat dissipation is achieved, and the power supply method is suitable for high-performance chip power supply.

An electronics package can comprise a first die, a cooling element disposed over the first die, a second die disposed over the cooling element, and a plurality of vias extending through the cooling element from the first die to the second die. The cooling element can comprise at least one cavity. The at least one cavity can comprise a wicking layer disposed over an interior surface of the at least one cavity.

The present disclosure describes a semiconductor device assembly including a first wafer having complementary metal oxide semiconductor (CMOS) devices including a plurality of string drivers, where each of the plurality of string drivers includes a field effect transistor (FET), a global word line connected to a source of the FET, and a local word line vertically passing through the FET; and a second wafer having a memory array including a plurality of word lines, each of the word lines connected to a corresponding one of the string drivers of the first wafer through a local word line of the corresponding one of the string drivers, wherein the backside surface of the first wafer is bonded to the front side surface of the second wafer to form a wafer stack WOW bond.

The embodiment of the invention provides a wafer bonding structure and a manufacturing method thereof, a manufacturing method of a chip stacking structure and a packaging structure. The manufacturing method of the wafer bonding structure comprises the following steps: providing a first wafer and a second wafer; the first wafer and the second wafer comprise a plurality of chips; forming a first dielectric layer covering the first surfaces of the first wafer and the second wafer; forming a first conductive structure penetrating through the first dielectric layer; the first conductive structure is in contact with the side wall of the first dielectric layer and the top surface of the corresponding chip; a first height difference exists between the top surface of the first dielectric layer and the top surface of the first conductive structure; forming a second dielectric layer covering the top surface of the first dielectric layer; a second height difference exists between the top surface of the second dielectric layer and the top surface of the first conductive structure; the absolute value of the second height difference is greater than that of the first height difference.

A semiconductor package may include a substrate including a plurality of vias and a chip stack on the substrate. The chip stack may include a plurality of semiconductor chips, wherein a first semiconductor chip is a lowermost one of the plurality of semiconductor chips in the chip stack, chip pads of the first semiconductor and substrate pads of the substrate are bonded to each other, and the chip pads and the substrate pads are integrally formed of the same metal material, the first semiconductor chip includes a corner region adjacent to a corner of the first semiconductor chip, and a center region excluding the corner region, the substrate includes a trench on an upper surface of the substrate, and the trench extends along a boundary between the corner region and the center region of the first semiconductor chip.

The invention relates to the technical field of semiconductors, provides a semiconductor device, and is used for solving the technical problem that a large lifting space still exists in a high-bandwidth memory technology. The semiconductor device includes: a chip stacking structure including a first semiconductor chip and a second semiconductor chip stacking structure stacked in a first direction; the first semiconductor chip comprises a controller, a calculation module and an interface module; the controller is configured to execute a first access operation on storage data in the second semiconductor chip stacking structure and send the storage data to the interface module to allow external equipment to access the storage data in the second semiconductor chip stacking structure through the interface module; and performing a second access operation on the storage data in the second semiconductor chip stack structure and sending the storage data to the computing module to allow the computing module to perform a computing operation on the storage data. Therefore, the integration level can be improved, the data transmission path can be shortened, and bandwidth consumption and energy consumption loss can be reduced.

Provided is a multi-dies stacking structure, which includes: a plurality of core dies stacked, wherein each core die comprises a first sub-core die and a second sub-core die vertically stacked; adjacent core dies are interconnected through micro-metal bumps, and the first sub-core die is interconnected with the second sub-core die through hybrid bonding members.

To provide a semiconductor device manufacturing apparatus and manufacturing method that stack a plurality of chips with high accuracy and high yield.SOLUTION: A manufacturing apparatus comprises a first stage 101 that supports a substrate 11, a second stage 102 that supports chips 12a to 12c so as to face the substrate, and a movable camera unit 103 that captures alignment markers of the substrate and the chips. At least one of the first stage and the second stage is movable, and the second stage performs alignment using a reference marker 21 or a chip marker 22a formed on the chip 12a, and a chip marker 22c formed on the chip 12c supported by the second stage, and thereafter stacks the chip 12c on the chips 12a and 12b. A depth of field of an objective lens included in the camera unit is equal to or less than a sum of a thickness of the chip 12b sandwiched between the chip marker 22a and the chip marker 22c, and a distance between the chip 12a and the chip 12c after the alignment.SELECTED DRAWING: Figure 4

A three-dimensional (3D) stacked chip is described. The 3D stacked chip includes a first die having a front-side surface and a backside surface, opposite the front-side surface. The backside surface on a front-side surface of a first redistribution layer (RDL). The 3D stacked chip also includes a second die having a front-side surface on the front-side surface of the first die and a backside surface being distal from the first RDL. The 3D stacked chip further includes a via extending from the backside surface of the second die to a back-end-of-line (BEOL) layer of the second die.

The present invention discloses a heterogeneously integrated optoelectronic chip based on an optical through-substrate via (TSV), comprising multiple stacked optoelectronic chips based on the same or different types of substrates, each layer of optoelectronic chips having several optoelectronic devices, and at least one pair of optoelectronic chip layers are attached back-to-back and have an optical TSV with interlayer coupling structures at both ends, so as to establish optical interconnection between at least one pair of optoelectronic devices in different layers. The interlayer coupling structures include coupling gratings with high alignment tolerance, and a high-reflectivity metal film at a certain distance above the grating to achieve efficient unidirectional coupling. The invention solves the technical difficulties of III-V / silicon heterogeneous integration and 3D multi-chip stacking. It achieves interlayer connections through optical TSVs, enabling front electrodes of optoelectronic chips to be used for interconnection with electronic chips, avoiding the fabrication difficulty of electrical TSVs.

The invention discloses a stacked chip architecture of a distributed cache and a chip. The stacked chip architecture comprises a logic calculation unit and a storage unit which are arranged in a stacked manner; the stacked chip architecture further comprises cache units, one cache unit is correspondingly connected with the logic calculation unit and the storage unit, the number of the cache units is multiple, and the multiple cache units are in topological connection; wherein the cache unit is used for storing a data address corresponding to the storage unit, and the logic calculation unit initiates a memory access request to the cache unit; if the memory access request hits the data address stored in the cache unit, returning the storage data of the storage unit to the logic calculation unit; and if the memory access request does not hit the data address stored in the cache unit, forwarding the memory access request to other cache units. According to the technical scheme, the requirement for high-bandwidth communication with the storage unit can be effectively met.

The invention provides a chip stacking structure, a manufacturing method thereof, a chip packaging structure and electronic equipment. The chip stacking structure comprises a first chip, at least one second chip and a supporting structure. Each second chip is located between the first chip and the supporting structure. The first chip is electrically connected with the second chips, and the supporting structure is connected with the second chips. An integrated passive device is arranged in the supporting structure, and the integrated passive device is electrically connected with at least one second chip; and / or the integrated passive device is electrically connected with the first chip. In the embodiment of the invention, the integrated passive device is integrated into the supporting structure, so that the integrated passive device, the second chip and the first chip can be stacked in the vertical direction, the interconnection distance between the second chip and / or the first chip and the integrated passive device can be greatly reduced, the integration level of the chip stacking structure is improved, the manufacturing cost is reduced, and moreover, the chip stacking structure is suitable for large-scale popularization and application. The substrate utilization rate of the supporting structure can be improved, and the internal structure of the chip stacking structure is reasonably utilized.

A semiconductor device includes: a wiring board having a surface; a chip stack disposed above the surface and including a first semiconductor chip; a second semiconductor chip disposed between the surface and the chip stack; a spacer disposed between the surface and the first semiconductor chip, the spacer surrounding the second semiconductor chip along the surface, and the spacer containing a material higher in thermal conductivity than silicon; and a sealing insulation layer covering the chip stack.

A stacked system-on-chip (SoC) is described. The stacked SoC includes a first memory die comprising a dynamic random-access memory (DRAM). The stacked SoC also includes a compute logic die. The compute logic die comprises a static random-access memory (SRAM) having a first SRAM partition and a second SRAM partition. The first memory die is stacked on the compute logic die. The compute logic die includes a memory controller. The memory controller is coupled between the first SRAM partition and the second SRAM partition. Additionally, the memory controller is coupled to a DRAM bus of the first memory die.

A semiconductor package includes a package substrate, a control chip, and a chip stack. A connection conductive pattern is on the top surface of the package substrate, spaced from the control chip. The package substrate has a first substrate pad, an extended interconnection line with first and second branch portions, and first and second interconnection lines. The control chip includes a mode selection pin and a chip connection terminal between the first substrate pad and the mode selection pin. The connection conductive pattern contacts the first branch portion and the first interconnection line but is spaced from the second branch portion and second interconnection line. A level of a top surface of the connection conductive pattern is lower than a level of a bottom surface of the control chip.

The invention discloses a CoWoS packaging technology for a GPU chip, and the technology comprises the following steps: S1, forming a glass substrate with a glass wafer as a temporary carrier, and coating a temporary bonding glue layer; s2, using a deep reactive ion etching technology to form a copper through silicon via, depositing an insulating layer and a barrier layer, patterning a metal wiring layer, and using a Cu Pin process to optimize TSV manufacturing to form a copper column interconnection structure; s3, forming a first EMC layer by using an epoxy molding compound; s4, the first EMC layer is thinned and flattened, the upper end face of the copper column is exposed, and the composition is defined as an intermediate layer; s5, making micro-bumps on the front surface of the interposer, and forming an insulating layer on the surface; and S6-S13, sequentially completing chip stacking, plastic packaging, glass substrate removal, C4 bump manufacturing, film pasting, cutting, butt joint and BGA ball implantation. According to the process, the TSV process is simplified through the CuPin process, the equipment investment is reduced by 40%, the productivity is improved by 30%, the process is compatible with the existing CoWoS-S process, and core equipment does not need to be transformed.

The invention discloses a stacked quantum chip supporting structure. The stacked quantum chip supporting structure comprises a first chip and a second chip, a cut-off layer is arranged on the end face between the first chip and the second chip, the cut-off layer is provided with multiple sets of limiting columns, and the first chip and the one or more second chips are aligned and bonded through the limiting columns to form a multi-layer stacked structure. According to the invention, a plurality of groups of limiting columns are arranged at the corresponding positions of one or more cut-off layers between the chips, so that the stress can be better balanced without influencing the wiring of the chips, the stress is more uniform and the chips are not deformed when the chips are subjected to flip-chip bonding or stacking design, and the sizes of the gaps between the chips can be determined by controlling the heights of the limiting columns, so that the yield of the chips is improved. Gaps and design are ensured to be consistent, and the problems of inclination, collapse and the like after multiple layers of chips are stacked are effectively solved; in addition, a lantern ring structure is formed by mutually embedding and connecting the coating cavities, so that the supporting stability is further improved, interconnected metal can be effectively prevented from overflowing to influence an external circuit structure, and the gap distance between the chips can be accurately controlled.

The utility model discloses a kind of co-encapsulation type light engine and networking.The co-encapsulation type light engine includes data processing bare core and the light chip stacked above the data processing bare core;The light chip is configured as the way of optical signal transceiver data;The data processing bare core is configured to process the data.The scheme provided by the utility model cancels silicon medium plate, adapter plate etc. intermediate substrate, further shorten transmission path, improve data transmission efficiency, in addition, this close coupling can also significantly reduce signal loss, improve high-speed signal integrity.

The invention relates to a chip stack package. Embodiments of the present disclosure provide a chip-on-package package, the chip-on-package package including: a first semiconductor chip having a front bump on a first surface; a second semiconductor chip stacked on a second surface of the first semiconductor chip opposite to the first surface; a carrier bump bonded to the front bump; a molding member surrounding the first semiconductor chip, the second semiconductor chip, and the carrier bump; and an external connection bump disposed on the carrier bump.

An apparatus and method for efficiently routing power signals across semiconductor dies. A semiconductor fabrication process (or process) places a first semiconductor die in an integrated circuit and stacks a second semiconductor die vertically adjacent to the first semiconductor die. The process forms multiple backside metal layers vertically adjacent to a backside of a silicon substrate of the second semiconductor die. The process forms a first backside metal layer that includes at least a first power route that forms a rectangle within the first backside metal layer. The process forms a second backside metal layer that includes at least a second power rail that forms an L-shape within the second backside metal layer. The process connects one or more corners of the rectangle of the first power rail to a corresponding corner of a separate power rail of the second backside metal layer that forms an L-shape.

This invention provides a silicon-based dielectric resonant antenna with adjustable beamwidth, comprising a beamwidth adjustment structure, an antenna substrate and a dielectric resonator, an excitation antenna, and solder bumps. The multilayer antenna substrate and dielectric resonator are arranged sequentially from top to bottom, with an air cavity formed in the middle. The excitation antenna is located at the bottom of the air cavity. The beamwidth adjustment structure is located on top of the top layer of the antenna substrate and dielectric resonator. A through-silicon via (TSV) is located in the middle of the bottom layer of the antenna substrate and dielectric resonator, with solder bumps located at the bottom of the TSV. This invention significantly reduces the antenna size and improves its radiation efficiency by using high-resistivity silicon as the antenna dielectric. By introducing an air cavity structure and adjusting the beamwidth through the top-layer beamwidth adjustment structure, the antenna application frequency can be changed according to usage, the feeding method can be modified and optimized according to application conditions, and it can be stacked with chips to achieve three-dimensional heterogeneous high-density integration.

The invention provides a semiconductor packaging structure and a preparation method, the semiconductor packaging structure comprises a circuit substrate and a second chip unit bonded on the surface of the circuit substrate, the second chip unit comprises multiple layers of stacked first chip units, and each first chip unit comprises a first chip and a second chip which are bonded up and down. A two-layer chip bonding structure is adopted as a single stacking unit, and compared with a single-layer chip, the structural strength is improved, so that larger internal stress can be borne during bonding, and buckling deformation is avoided. Besides, the preparation method adopts the technological process of bonding the wafers first and then cutting out the chip stacking units, so that the working efficiency and the productivity can be improved, particularly, multiple layers of wafers are stacked to form the wafer stacking body and then the second chip units are directly cut out, the subsequent process of stacking the first chip units one by one is omitted, and the production cost is reduced. And the manufacturing efficiency is further improved.

Microelectronic assemblies with a die stack positioned such that a face of each die in the stack is orthogonal to a face of a base are disclosed. Each die has a first face and a second face opposite the first face. The die stack includes multiple dies, with the faces of each die parallel to the faces of the other dies in the die stack. The die stack is positioned on the base such that the faces of each die are substantially orthogonal to the face of the base. Each die in the die stack can have a corresponding conductive contact, and the conductive contact on each die in the die stack can be coupled to a conductive contact on the base via an interconnect. The interconnect can be a solder joint, such as a solder bump or solder ball.

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a semiconductor device, the semiconductor structure comprising: a multilayer storage module stacked on the upper surface of the logic chip along a first direction, the first direction being perpendicular to the upper surface of the logic chip; the storage module comprising a plurality of storage chips stacked in a second direction, the second direction being parallel to the upper surface of the logic chip; the storage chip at the top layer having one second wireless communication unit; the storage chip at a non-top layer having two second wireless communication units arranged in the first direction and a wired communication unit connected between the two second wireless communication units; in the first direction, the two second wireless communication units arranged adjacently and located in different storage chips perform wireless communication; and the first wireless communication unit performs wireless communication with the second wireless communication unit in the bottom layer storage chip closest to the first wireless communication unit. The embodiment of the present disclosure can at least improve the capacity density and performance of the semiconductor structure.