803 results about "Chip stacking" patented technology

The invention relates to the technical field of electronic packaging, in particular to a welding process applied to a double-mesa device. The technology comprises the following steps that firstly, a heat conduction model of a double-table-board device is built, a temperature field prediction system is built in combination with measured data, secondly, an asymmetric double-pulse-current welding strategy is adopted, differential pulse waveforms are loaded to an upper table board and a lower table board respectively, independent temperature control over all welding areas is achieved, a temperature difference closed-loop feedback mechanism is introduced in the process, and the temperature field prediction system is obtained. Pulse parameters are dynamically adjusted according to real-time temperature deviation, a stress prediction and weld penetration monitoring module is used for assistance, the welding spot forming quality and heat stress balanced release are ensured, a staged annealing type cooling mode is adopted after welding, and the structural stability is improved. The method can be widely applied to MEMS modules, SiC power devices and heterogeneous chip laminated packaging double-mesa structure devices, and has the advantages of being high in welding precision, high in reliability and wide in process adaptability.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

A semiconductor structure includes system-on-integrated chips, a first redistribution circuit structure and first conductive terminals. The system-on-integrated chips each include a die stack having two or more than two tiers, and each tier includes at least one semiconductor die. The first redistribution circuit structure is located on and electrically connected to the system-on-integrated chips. The first conductive terminals are connected on the first redistribution circuit structure, where the first redistribution circuit structure is located between the system-on-integrated chips and the first conductive terminals.

The invention discloses a co-packaging type optical engine module and networking. The co-packaged optical engine module comprises a photonic integrated chip and a processor bare core, and the photonic integrated chip is stacked above the processor bare core and electrically connected with the processor bare core; the photonic integrated chip is configured to transmit and receive data in an optical signal mode, and an optical signal transmitting and receiving end of the photonic integrated chip is located on one side far away from the processor bare core; the processor die is configured to process the data. According to the scheme provided by the invention, intermediate substrates such as a silicon dielectric plate and an adapter plate are canceled, the transmission path is further shortened, the data transmission efficiency is improved, in addition, the signal loss can be remarkably reduced by the tight coupling, and the high-speed signal integrity is improved.

The invention discloses a multi-chip stacked packaging structure and a manufacturing method, and the manufacturing method comprises the steps: designing a welding spot which is downwards connected to a lower-layer chip and a welding spot which is upwards connected to an upper-layer chip on a metal frame according to the connection demands of a wafer, placing the wafer in a welding pad on the standardized metal frame, and carrying out the die bonding treatment, bonding the pin interconnection point of the wafer with the welding point through a connecting line to obtain an electric connection module; carrying out injection molding packaging on the electric connection module, then carrying out cutting processing to form a plurality of single chips, and carrying out test processing on the single chips; and stacking the plurality of qualified single chips on the circuit board in the vertical direction, and packaging the stacked structure in the single packaging cavity to obtain the multi-chip stacked packaging structure. According to the invention, through vertical stacking and single packaging cavity packaging, high integration level and miniaturized packaging are realized, the excellent thermal conductivity of the metal frame enables the heat dissipation performance of the chip to be improved, and the service life of the chip is prolonged.

According to the storage and calculation integrated chip architecture, the chip stacking packaging structure and the terminal equipment, physical tight coupling of storage and calculation is realized through the 3D stacking design of the first storage unit and the logic calculation unit, the problem of physical separation of traditional storage and calculation is solved, the data carrying distance and the cross-chip communication overhead are remarkably reduced, and the communication efficiency is improved. And the chip area and the packaging process complexity are reduced, and the application scenarios of end-side artificial intelligence reasoning and mass data reading and writing are supported. According to the storage and calculation integrated chip architecture, the first storage unit and the logic calculation unit are directly interconnected through the vertical interconnection technology, the data access delay is reduced, the requirement of end side equipment for low delay is met, and the energy efficiency ratio of the storage and calculation integrated chip architecture is remarkably reduced.

The embodiment of the invention provides a memory chip, a logic chip, a chip stacking structure and a memory, a global signal area of the memory chip is penetrated by a plurality of conductive through hole groups, each conductive through hole group comprises a first redundant conductive through hole group and a second redundant conductive through hole group, the first redundant conductive through hole group comprises a first conductive through hole and a fourth conductive through hole, and the second redundant conductive through hole group comprises a second conductive through hole and a third conductive through hole; the first redundant conductive through hole group is used for transmitting the same first global signal, and the second redundant conductive through hole group is used for transmitting the same second global signal.

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes an optical interposer having optical waveguides; a plurality of chip stacks disposed over the optical interposer, each of the plurality of chip stacks including a first photonic IC chip and a memory chip over the first photonic IC chip; and a plurality of first laser source chips disposed adjacent to the plurality of chip stacks, respectively, wherein the optical waveguides in the optical interposer are configured as an optical interconnect structure to couple with the memory chip through the first photonic IC chip.

The invention provides a memory computing chip and a manufacturing method thereof, which are characterized in that a logic chip with a computing processor, a buffer chip and a DRAM (dynamic random access memory) chip (or a DRAM chip stack) are vertically stacked through silicon through holes, and the chips can be directly communicated through the silicon through holes, so that the chip area can be saved, the integration level is high, the wafer processing difficulty is reduced, and the manufacturing cost is reduced. The logic chip can visit the low-speed DRAM chip in parallel in a large number through the buffer chip, high-bandwidth and large-capacity cache is provided, inter-chip communication between the buffer chip and the logic chip does not need a physical layer interface, and cost of hardware resources is greatly reduced.

The invention discloses a self-adaptive chip removal method and system of a numerical control machine tool. The method comprises the steps that machining parameters of the numerical control machine tool, chip stacking density data in a chip removal channel, chip fluidity data and discharged weight data of the chip removal tail end are collected in real time; on the basis of the machining parameters and a preset tool cutting amount model, calculating a cutting theoretical generation volume in the current machining period; according to the chip stacking density data, the fluidity data and the discharged weight data, combining a chip theory to generate a volume, and dynamically calculating the real-time stock of chips in the chip discharging channel; on the basis of the real-time stock of the cuttings, a chip removal control rule in a predefined chip removal strategy library is matched, and the start-stop state and the conveying speed of the chip removal machine are dynamically adjusted; and when the real-time stock of the cuttings exceeds the preset threshold value, the secondary flow guide action of the flow guide device is triggered to accelerate chip removal. By means of the method, starting, stopping and speed of the chip removal machine can be automatically controlled, manual intervention in the chip removal process can be greatly reduced, and labor and operation and maintenance cost is reduced.

The invention provides a multi-chip stacking packaging structure, which reduces the overall packaging thickness, realizes unlimited intersystem spacing and multi-chip stacking, reduces the loss of electric signal transmission, and is low in production cost. The packaging structure comprises a first plastic package layer assembly which comprises a first plastic package layer, a plurality of thin first chip sets and at least one second chip, and the thickness of the second chip is relatively larger than that of each chip set in the first chip sets; the second plastic package layer assembly comprises a second plastic package layer, at least one third chip and a plurality of groups of giant metal convex columns; a high-sealing metal wiring layer; and a low-density metal wiring layer.

Provided is a semiconductor package having improved signal integrity (SI) and a chip stack structure of a plurality of semiconductor chips. The semiconductor package includes a package substrate, a chip stack structure on the package substrate and including at least two semiconductor chips, and an external connection terminal on a lower surface of the package substrate. A first semiconductor chip arranged uppermost in the chip stack structure is connected to a first bonding pad of the package substrate through a first wire. A second semiconductor chip arranged under the first semiconductor chip in the chip stack structure is connected to a second bonding pad of the package substrate through a second wire. When the first bonding pad is farther from the external connection terminal than the second bonding pad, the external connection terminal is connected to the first bonding pad through a wiring line of the package substrate.

A semiconductor package includes a package substrate, stack structures on the package substrate, a buffer chip on the package substrate and spaced apart from the stack structures in a horizontal direction, a memory controller chip stacked on the buffer chip, and a photonics package including a photonic integrated circuit (PIC) chip on the package substrate, an electronic integrated circuit (EIC) chip on the PIC chip, and a first molding layer surrounding the EIC chip. Each of the stack structures includes stacked core chips each including a memory cell, the buffer chip is configured to control the memory cell of each of the stacked core chips of each of the stack structures, and the memory controller chip is configured to interconnect the buffer chip to the photonics package.

A non-volatile memory apparatus includes a stack of memory dies with multiple layers. Each layer has multiple memory die, and the stack includes separate parallel through silicon vias (TSVs) for each memory die. The non-volatile memory apparatus also includes a memory controller in electrical communication with the separate parallel TSVs for each memory die and configured to perform a high bandwidth read process for data stored in the stack across all or multiple of the memory dies.

A chip stack structure is provided. The chip stack structure includes a first chip including a first substrate and a first interconnect structure over the first substrate. The chip stack structure includes a second chip over and bonded to the first chip. The second chip has a second interconnect structure and a second substrate over the second interconnect structure. The chip stack structure includes an insulating layer over the second interconnect structure and surrounding the second substrate. The chip stack structure includes a conductive plug penetrating through the insulating layer to the second interconnect structure.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

Technologies for chip-to-chip (C2C) yield and performance optimization in a die stacking platform are described. One apparatus includes a substrate, a first integrated circuit disposed on the substrate at a first location, a second integrated circuit disposed on the substrate at a second location, and a third integrated circuit disposed on the second integrated circuit. The second integrated circuit is coupled to the first integrated circuit using a first chip-to-chip (C2C) interface via a physical terminal. The third integrated circuit is coupled to the first integrated circuit using a second C2C interface via the physical terminal. Only one of the first C2C interface and the second C2C interface is active at a time.

To provide a semiconductor package improved in reliability.SOLUTION: A semiconductor package includes an interconnection chip INC between a first chip stack CS1 and a second chip stack CS2, the interconnection chip including interconnection vias INV electrically connecting first through-vias TSV1 and second through-vias TSV2 to each other. The interconnection chip has a lower surface 210LS in contact with the first chip stack, an upper surface 210US in contact with the second chip stack, and a side surface between the lower surface and the upper surface. The side surface of the interconnection chip includes a first portion extending from the lower surface of the interconnection chip at a first inclination, and a second portion extending from the first portion to the upper surface of the interconnection chip at a second inclination lower than the first inclination.SELECTED DRAWING: Figure 1b

The invention designs a broadband intermediate-frequency heterogeneous integrated communication transceiving micro module and a three-dimensional packaging method, and belongs to the technical field of advanced packaging. The micro module comprises a TSV silicon adapter plate, a Fan-out module, an HTCC ceramic substrate and a digital chip. The TSV silicon adapter plate adopts a high-resistance silicon substrate, and a coaxial shielding TSV structure is arranged on the TSV silicon adapter plate and comprises an inner layer signal through hole and an outer layer grounding layer. A frequency synthesizer chip and a radio frequency chip are embedded in the Fan-out module, and high-density horizontal interconnection is realized through a plurality of redistribution layers. The HTCC ceramic substrate is of a multi-layer laminated structure, and an impedance matching network is arranged in the HTCC ceramic substrate. The three-dimensional packaging method comprises the steps of TSV silicon adapter plate preparation, Fan-out module processing, digital chip stacking and system-level integration. High-density packaging of the radio frequency chip and the digital chip is achieved through the three-dimensional heterogeneous integrated architecture, and low-loss transmission of broadband signals is guaranteed through the coaxial shielding TSV structure and the impedance matching network.

Stacked semiconductor packages with features to mitigate trace exposer and associated systems and methods are disclosed herein. In some embodiments, the stacked semiconductor package includes a base substrate, a stack of dies carried by the base substrate, and a mold material deposited at least partially encapsulating the stack of dies. The base substrate can include an active surface and a back surface opposite the active surface. Further, the active surface can include one or more cuts into a peripheral portion of the active surface (e.g., stepped structures at the peripheral edges of the base substrate). The base substrate can also include a plurality of bond pads carried by the active surface over the peripheral portion. Still further, the mold material can fill each of the one or more cuts in the active surface, thereby insulating the bond pads from exposure at a sidewall of the stacked semiconductor package.

The invention relates to the technical field of semiconductor packaging and chip power supply, in particular to a three-dimensional chip stacking power supply system and method based on a power wafer, and the system comprises an integrated power wafer, a calculation chip and a power peripheral device. A high-density capacitor array is integrated in the integrated power supply wafer, a rewiring layer is formed on the surface of the integrated power supply wafer, and a distributed voltage regulation module is configured; the computing chip is a known qualified chip and is inversely mounted on the rewiring layer through a micro bump / copper column, and a power supply bonding pad is directly connected with a power supply node; the power supply peripheral device is attached to the free area of the integrated power supply wafer or the same packaging substrate. The method comprises the steps of prefabrication of an integrated power supply wafer, flip mounting of a computing chip, bottom filling and integration with a packaging substrate. Through chip-wafer integration, the power supply path is shortened, resistance and noise are reduced, precision pipe and heterogeneous integration is achieved, the yield is increased, cost is reduced, bidirectional heat dissipation is achieved, and the power supply method is suitable for high-performance chip power supply.

An electronics package can comprise a first die, a cooling element disposed over the first die, a second die disposed over the cooling element, and a plurality of vias extending through the cooling element from the first die to the second die. The cooling element can comprise at least one cavity. The at least one cavity can comprise a wicking layer disposed over an interior surface of the at least one cavity.

An example microelectronic assembly includes a substrate, a bridge die over the substrate, and a die stack between the substrate and the bridge die, the die stack including a logic die and at least one memory die, where the logic die is between the at least one memory die and the bridge die.

The present disclosure describes a semiconductor device assembly including a first wafer having complementary metal oxide semiconductor (CMOS) devices including a plurality of string drivers, where each of the plurality of string drivers includes a field effect transistor (FET), a global word line connected to a source of the FET, and a local word line vertically passing through the FET; and a second wafer having a memory array including a plurality of word lines, each of the word lines connected to a corresponding one of the string drivers of the first wafer through a local word line of the corresponding one of the string drivers, wherein the backside surface of the first wafer is bonded to the front side surface of the second wafer to form a wafer stack WOW bond.

The invention discloses a co-packaged optical switching module and an optical engine network. The co-packaged optical switching module comprises a photonic integrated chip and an optical switching bare core, and the photonic integrated chip is stacked above the optical switching bare core and is electrically connected with the optical switching bare core. The photonic integrated chip is configured to transmit and receive data in an optical signal mode, and an optical signal transmitting and receiving end of the photonic integrated chip is located on one side far away from the optical switching bare core; the optical switching die is configured to process the data. According to the scheme provided by the invention, intermediate substrates such as a silicon dielectric plate and an adapter plate are canceled, the transmission path is further shortened, the data transmission efficiency is improved, in addition, the signal loss can be remarkably reduced by the tight coupling, and the high-speed signal integrity is improved.

The embodiment of the invention provides a wafer bonding structure and a manufacturing method thereof, a manufacturing method of a chip stacking structure and a packaging structure. The manufacturing method of the wafer bonding structure comprises the following steps: providing a first wafer and a second wafer; the first wafer and the second wafer comprise a plurality of chips; forming a first dielectric layer covering the first surfaces of the first wafer and the second wafer; forming a first conductive structure penetrating through the first dielectric layer; the first conductive structure is in contact with the side wall of the first dielectric layer and the top surface of the corresponding chip; a first height difference exists between the top surface of the first dielectric layer and the top surface of the first conductive structure; forming a second dielectric layer covering the top surface of the first dielectric layer; a second height difference exists between the top surface of the second dielectric layer and the top surface of the first conductive structure; the absolute value of the second height difference is greater than that of the first height difference.

A semiconductor package may include a substrate including a plurality of vias and a chip stack on the substrate. The chip stack may include a plurality of semiconductor chips, wherein a first semiconductor chip is a lowermost one of the plurality of semiconductor chips in the chip stack, chip pads of the first semiconductor and substrate pads of the substrate are bonded to each other, and the chip pads and the substrate pads are integrally formed of the same metal material, the first semiconductor chip includes a corner region adjacent to a corner of the first semiconductor chip, and a center region excluding the corner region, the substrate includes a trench on an upper surface of the substrate, and the trench extends along a boundary between the corner region and the center region of the first semiconductor chip.

The invention relates to the technical field of semiconductors, provides a semiconductor device, and is used for solving the technical problem that a large lifting space still exists in a high-bandwidth memory technology. The semiconductor device includes: a chip stacking structure including a first semiconductor chip and a second semiconductor chip stacking structure stacked in a first direction; the first semiconductor chip comprises a controller, a calculation module and an interface module; the controller is configured to execute a first access operation on storage data in the second semiconductor chip stacking structure and send the storage data to the interface module to allow external equipment to access the storage data in the second semiconductor chip stacking structure through the interface module; and performing a second access operation on the storage data in the second semiconductor chip stack structure and sending the storage data to the computing module to allow the computing module to perform a computing operation on the storage data. Therefore, the integration level can be improved, the data transmission path can be shortened, and bandwidth consumption and energy consumption loss can be reduced.

The embodiment of the invention relates to the technical field of semiconductors, and provides a stacked structure and memory equipment, the stacked structure comprises a plurality of chip sets which are arranged in a stacked mode, and each chip set comprises a first memory chip, an in-memory computing chip stacked on the first memory chip and a second memory chip stacked on the in-memory computing chip. The in-memory computing chip, the first memory chip and the second memory chip are separately arranged, so that the areas of memory units in the first memory chip and the second memory chip do not need to be sacrificed, and the integration level of the chips is improved. And the memory computing chip can use a logic manufacturing process, so that the memory computing speed is improved.

Various embodiments for die stacking are disclosed in the present disclosure for improved performance in RF circuit integration and packaging. In various layouts, a first die may be flipped and stacked on a second die via one or more bumping pillars coupled between the dies. The bumping pads may be disposed on the first die, the second die, or both. The bumping pads may comprise ground bumping pads for ground connection, RF signal bumping pads for cross-die RF signal transmission, and / or control bumping pads for biasing or logic control. Furthermore, the ground bumping pads and the RF signal bumping pad may form a ground-signal-ground pad structure for smooth RF signal transmission. The present embodiments may integrate a silicon-based die with an III-V semiconductor-based die together for a small form factor package with the well-defined ground to handle RF signals over millimeter-wave frequencies at high power levels.