963 results about "Chip stacking" patented technology

The invention relates to the technical field of chip stacking, and discloses an intelligent temperature control method and device of a multi-chip stacking structure and computer equipment. The method comprises the following steps: acquiring target temperature data of each layer of chip in a multi-chip stacking structure, and establishing a nonlinear temperature response model; constructing a hierarchical control framework, and inputting the target temperature data into an agent auxiliary temperature control algorithm for processing to obtain temperature distribution characteristic data; performing optimal sampling analysis to obtain local temperature regulation and control parameters; constructing a temperature-flow multi-stage coordination control model, and generating a cooling liquid flow distribution scheme and a flow direction control instruction; the flow and temperature of cooling liquid are controlled, gradient cooling treatment is conducted on the temperature abnormal area, and temperature adjusting process data are obtained; and carrying out multistable distribution analysis to generate a temperature control optimization strategy. According to the invention, the problem of temperature balance in a multi-chip stacking structure is effectively solved.

The invention relates to the technical field of electronic packaging, in particular to a welding process applied to a double-mesa device. The technology comprises the following steps that firstly, a heat conduction model of a double-table-board device is built, a temperature field prediction system is built in combination with measured data, secondly, an asymmetric double-pulse-current welding strategy is adopted, differential pulse waveforms are loaded to an upper table board and a lower table board respectively, independent temperature control over all welding areas is achieved, a temperature difference closed-loop feedback mechanism is introduced in the process, and the temperature field prediction system is obtained. Pulse parameters are dynamically adjusted according to real-time temperature deviation, a stress prediction and weld penetration monitoring module is used for assistance, the welding spot forming quality and heat stress balanced release are ensured, a staged annealing type cooling mode is adopted after welding, and the structural stability is improved. The method can be widely applied to MEMS modules, SiC power devices and heterogeneous chip laminated packaging double-mesa structure devices, and has the advantages of being high in welding precision, high in reliability and wide in process adaptability.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

The invention relates to the technical field of chip packaging, and discloses an ultrathin multi-layer storage chip stacking packaging method, which comprises the following steps of: obtaining a storage chip to be packaged, performing chip quality division on the storage chip to be packaged to obtain a target chip, and performing fine classification on the target chip to obtain a plurality of groups of chips; performing thickness optimization on the multiple groups of divided chips to obtain thickness-optimized chips, and performing chip selection on the thickness-optimized chips to obtain selected chips; performing material coating on the selected chip to obtain a coated chip, performing chip curing on the coated chip to obtain a cured chip, and performing chip stacking on the cured chip to obtain a stacked chip; carrying out three-dimensional modeling on the stacked chips so as to carry out dispensing path planning on the stacked chips to obtain a dispensing path, and carrying out chip reinforcement on the stacked chips to obtain reinforced chips; and performing internal interconnection, preliminary packaging and shell injection molding on the reinforced chip to obtain a packaged chip. According to the invention, the packaging quality of the ultrathin multi-layer memory chip can be improved.

A semiconductor structure includes system-on-integrated chips, a first redistribution circuit structure and first conductive terminals. The system-on-integrated chips each include a die stack having two or more than two tiers, and each tier includes at least one semiconductor die. The first redistribution circuit structure is located on and electrically connected to the system-on-integrated chips. The first conductive terminals are connected on the first redistribution circuit structure, where the first redistribution circuit structure is located between the system-on-integrated chips and the first conductive terminals.

The invention discloses a co-packaging type optical engine module and networking. The co-packaged optical engine module comprises a photonic integrated chip and a processor bare core, and the photonic integrated chip is stacked above the processor bare core and electrically connected with the processor bare core; the photonic integrated chip is configured to transmit and receive data in an optical signal mode, and an optical signal transmitting and receiving end of the photonic integrated chip is located on one side far away from the processor bare core; the processor die is configured to process the data. According to the scheme provided by the invention, intermediate substrates such as a silicon dielectric plate and an adapter plate are canceled, the transmission path is further shortened, the data transmission efficiency is improved, in addition, the signal loss can be remarkably reduced by the tight coupling, and the high-speed signal integrity is improved.

The invention discloses a multi-chip stacked packaging structure and a manufacturing method, and the manufacturing method comprises the steps: designing a welding spot which is downwards connected to a lower-layer chip and a welding spot which is upwards connected to an upper-layer chip on a metal frame according to the connection demands of a wafer, placing the wafer in a welding pad on the standardized metal frame, and carrying out the die bonding treatment, bonding the pin interconnection point of the wafer with the welding point through a connecting line to obtain an electric connection module; carrying out injection molding packaging on the electric connection module, then carrying out cutting processing to form a plurality of single chips, and carrying out test processing on the single chips; and stacking the plurality of qualified single chips on the circuit board in the vertical direction, and packaging the stacked structure in the single packaging cavity to obtain the multi-chip stacked packaging structure. According to the invention, through vertical stacking and single packaging cavity packaging, high integration level and miniaturized packaging are realized, the excellent thermal conductivity of the metal frame enables the heat dissipation performance of the chip to be improved, and the service life of the chip is prolonged.

According to the storage and calculation integrated chip architecture, the chip stacking packaging structure and the terminal equipment, physical tight coupling of storage and calculation is realized through the 3D stacking design of the first storage unit and the logic calculation unit, the problem of physical separation of traditional storage and calculation is solved, the data carrying distance and the cross-chip communication overhead are remarkably reduced, and the communication efficiency is improved. And the chip area and the packaging process complexity are reduced, and the application scenarios of end-side artificial intelligence reasoning and mass data reading and writing are supported. According to the storage and calculation integrated chip architecture, the first storage unit and the logic calculation unit are directly interconnected through the vertical interconnection technology, the data access delay is reduced, the requirement of end side equipment for low delay is met, and the energy efficiency ratio of the storage and calculation integrated chip architecture is remarkably reduced.

The embodiment of the invention provides a memory chip, a logic chip, a chip stacking structure and a memory, a global signal area of the memory chip is penetrated by a plurality of conductive through hole groups, each conductive through hole group comprises a first redundant conductive through hole group and a second redundant conductive through hole group, the first redundant conductive through hole group comprises a first conductive through hole and a fourth conductive through hole, and the second redundant conductive through hole group comprises a second conductive through hole and a third conductive through hole; the first redundant conductive through hole group is used for transmitting the same first global signal, and the second redundant conductive through hole group is used for transmitting the same second global signal.

The present disclosure provides a logic chip, a memory chip, a chip stack structure, and a memory. The logic chip is provided with a plurality of channel signal regions, conductive vias in each one of the plurality of channel signal regions are divided into a plurality of repair unit groups, and each one of the plurality of repair unit groups includes four repair units, where a first repair unit and a second repair unit are arranged symmetrically about a first axis, a third repair unit and a fourth repair unit are arranged symmetrically about the first axis, and the first repair unit and the fourth repair unit are arranged symmetrically about a second axis.

A structure including a first chip and a second chip stacked over and bonded to the first chip at a bonding interface is provided. The first and second chips form a device stack. The first chip includes a first dielectric and first interconnects arranged in the first dielectric. The second chip includes a second dielectric over the first dielectric and second interconnects arranged in the second dielectric. A trench capacitor is arranged in the device stack. The trench capacitor extends through the second chip, the bonding interface and at least partially into the first chip.

The invention provides a display module. The display module comprises a substrate, a functional chip located on the substrate, a pixel driving chip located on the functional chip, and an optical chip located on the pixel driving chip. And the functional chip is used for realizing the functions of the display module except for light emitting driving and light emitting. The pixel driving chip and the functional chip are mutually independent chips, and the pixel driving chip and the functional chip are stacked and packaged through a chip stacking technology.

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes an optical interposer having optical waveguides; a plurality of chip stacks disposed over the optical interposer, each of the plurality of chip stacks including a first photonic IC chip and a memory chip over the first photonic IC chip; and a plurality of first laser source chips disposed adjacent to the plurality of chip stacks, respectively, wherein the optical waveguides in the optical interposer are configured as an optical interconnect structure to couple with the memory chip through the first photonic IC chip.

The invention provides a memory computing chip and a manufacturing method thereof, which are characterized in that a logic chip with a computing processor, a buffer chip and a DRAM (dynamic random access memory) chip (or a DRAM chip stack) are vertically stacked through silicon through holes, and the chips can be directly communicated through the silicon through holes, so that the chip area can be saved, the integration level is high, the wafer processing difficulty is reduced, and the manufacturing cost is reduced. The logic chip can visit the low-speed DRAM chip in parallel in a large number through the buffer chip, high-bandwidth and large-capacity cache is provided, inter-chip communication between the buffer chip and the logic chip does not need a physical layer interface, and cost of hardware resources is greatly reduced.

The invention discloses a self-adaptive chip removal method and system of a numerical control machine tool. The method comprises the steps that machining parameters of the numerical control machine tool, chip stacking density data in a chip removal channel, chip fluidity data and discharged weight data of the chip removal tail end are collected in real time; on the basis of the machining parameters and a preset tool cutting amount model, calculating a cutting theoretical generation volume in the current machining period; according to the chip stacking density data, the fluidity data and the discharged weight data, combining a chip theory to generate a volume, and dynamically calculating the real-time stock of chips in the chip discharging channel; on the basis of the real-time stock of the cuttings, a chip removal control rule in a predefined chip removal strategy library is matched, and the start-stop state and the conveying speed of the chip removal machine are dynamically adjusted; and when the real-time stock of the cuttings exceeds the preset threshold value, the secondary flow guide action of the flow guide device is triggered to accelerate chip removal. By means of the method, starting, stopping and speed of the chip removal machine can be automatically controlled, manual intervention in the chip removal process can be greatly reduced, and labor and operation and maintenance cost is reduced.

Provided in the present disclosure are a chip stacking heat dissipation structure, a three-dimensional stacking packaging system and a manufacturing method. The chip stacking heat dissipation structure comprises: a re-distributed layer, a connecting layer and a chip layer which are successively stacked from bottom to top, a plurality of cooling fins being embedded in the re-distributed layer to form a heat dissipation layer, and the heat dissipation layer and the re-distributed layer being located on the same side of the chip layer. The re-distributed layer and the heat dissipation layer of the present application are both located on the same side of the chip layer, such that the re-distributed layer and the heat dissipation layer occupy relatively smaller spaces, and chip layers are stacked at a higher integration level, thus achieving a greater number of chip lays stacked per unit height, reducing the overall size and the packaging thickness of the chip stacking heat dissipation structure, enabling the chip stacking heat dissipation structure to be applied to more terminal devices having higher requirements for thickness while not losing heat dissipation effects.

The invention provides a memory chip, a logic chip, a chip stacking structure and a memory. The memory chip comprises m channels, and the m channels are sequentially arranged in the first direction and are symmetrical about the axis of the chip; each channel is provided with a channel signal region, each channel signal region is divided into 2 * 2 through hole regions which are distributed in an array, the areas of the m channel signal regions are the same, and the distribution positions of the conductive through hole groups in the m channel signal regions are the same.

Provided are a memory chip, a logic chip, a chip stack structure, and a memory. In the memory chip, four first transmission structures are arranged symmetrically about a first axis and a second axis; four second transmission structures in each second transmission structure group are arranged symmetrically about the first axis and the second axis; the memory chip receives one first identification signal from each one of the first transmission structures and generates a chip position identification code based on four first identification signals; the memory chip receives one second identification signal from each second transmission structure group and generates a stack position identification code based on B second identification signals.

The invention provides a multi-chip stacking packaging structure, which reduces the overall packaging thickness, realizes unlimited intersystem spacing and multi-chip stacking, reduces the loss of electric signal transmission, and is low in production cost. The packaging structure comprises a first plastic package layer assembly which comprises a first plastic package layer, a plurality of thin first chip sets and at least one second chip, and the thickness of the second chip is relatively larger than that of each chip set in the first chip sets; the second plastic package layer assembly comprises a second plastic package layer, at least one third chip and a plurality of groups of giant metal convex columns; a high-sealing metal wiring layer; and a low-density metal wiring layer.

Provided is a semiconductor package having improved signal integrity (SI) and a chip stack structure of a plurality of semiconductor chips. The semiconductor package includes a package substrate, a chip stack structure on the package substrate and including at least two semiconductor chips, and an external connection terminal on a lower surface of the package substrate. A first semiconductor chip arranged uppermost in the chip stack structure is connected to a first bonding pad of the package substrate through a first wire. A second semiconductor chip arranged under the first semiconductor chip in the chip stack structure is connected to a second bonding pad of the package substrate through a second wire. When the first bonding pad is farther from the external connection terminal than the second bonding pad, the external connection terminal is connected to the first bonding pad through a wiring line of the package substrate.

A semiconductor package includes a package substrate, stack structures on the package substrate, a buffer chip on the package substrate and spaced apart from the stack structures in a horizontal direction, a memory controller chip stacked on the buffer chip, and a photonics package including a photonic integrated circuit (PIC) chip on the package substrate, an electronic integrated circuit (EIC) chip on the PIC chip, and a first molding layer surrounding the EIC chip. Each of the stack structures includes stacked core chips each including a memory cell, the buffer chip is configured to control the memory cell of each of the stacked core chips of each of the stack structures, and the memory controller chip is configured to interconnect the buffer chip to the photonics package.

An example semiconductor package includes a package substrate, an electronic integrated circuit (EIC) package mounted on the package substrate, and a plurality of photonic integrated circuit (PIC) chips stacked on the EIC package. Each PIC chip of the plurality of PIC chips includes an upper groove recessed inwards from an upper surface of the PIC chip and being open toward a first side surface of the PIC chip. The EIC package includes a lower redistribution layer on the package substrate, an EIC chip mounted on the lower redistribution layer, a molding layer surrounding the EIC chip, a through via passing through the molding layer in a vertical direction and electrically connected with the lower redistribution layer, and an upper redistribution layer on the through via.

A non-volatile memory apparatus includes a stack of memory dies with multiple layers. Each layer has multiple memory die, and the stack includes separate parallel through silicon vias (TSVs) for each memory die. The non-volatile memory apparatus also includes a memory controller in electrical communication with the separate parallel TSVs for each memory die and configured to perform a high bandwidth read process for data stored in the stack across all or multiple of the memory dies.

A chip stack structure is provided. The chip stack structure includes a first chip including a first substrate and a first interconnect structure over the first substrate. The chip stack structure includes a second chip over and bonded to the first chip. The second chip has a second interconnect structure and a second substrate over the second interconnect structure. The chip stack structure includes an insulating layer over the second interconnect structure and surrounding the second substrate. The chip stack structure includes a conductive plug penetrating through the insulating layer to the second interconnect structure.

The invention provides a memory chip, a logic chip, a chip stacking structure and a memory, in the memory chip, four first transmission structures are symmetrical about a first axis and a second axis; the four second transmission structures in each second transmission structure group are symmetrical about the first axis and the second axis; the storage chip receives one first identification signal from each first transmission structure and generates a chip position identification code based on the four first identification signals; the storage chip receives one second identification signal from each second transmission structure group, and generates a stacking position identification code based on the B second identification signals.

A semiconductor package comprises a package substrate and a first chip stack. The first chip stack includes: a first semiconductor chip on the package substrate, a plurality of second semiconductor chips that are on the first semiconductor chip and have an offset stack structure, and a plurality of first adhesive layers that are respectively on a bottom surface of the first semiconductor chip and bottom surfaces of the second semiconductor chips. The first semiconductor chip includes: a first semiconductor substrate, a plurality of first integrated elements on a top surface of the first semiconductor substrate, and a first wiring layer on the top surface of the first semiconductor substrate. A width of the first semiconductor chip and a width of a lowermost one of the second semiconductor chips are the same. The first semiconductor chip is electrically insulated from the package substrate and the second semiconductor chips.

The invention provides a layout and logic diagram comparison LVS verification method, which is applied to a three-dimensional integrated circuit (3D IC) comprising at least two bare chip stacked layer by layer and at least one through silicon via (TSV), and comprises the following steps: acquiring a first netlist file; obtaining a first layout file, wherein the first layout file comprises a circuit layout of the three-dimensional integrated circuit; according to the first layout file, constructing a simplified model of the three-dimensional integrated circuit, the simplified model comprising a connection relationship and a stack structure of the at least two bare chips and the at least one TSV in a circuit layout; and comparing the first netlist file with the simplified model to obtain LVS verification information of the three-dimensional integrated circuit. According to the method, the 3D IC is simplified into a plurality of independent models, and then the models are converted into LVS verification of the 2D stacked model, so that the operation efficiency of the LVS verification is optimized.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

Technologies for chip-to-chip (C2C) yield and performance optimization in a die stacking platform are described. One apparatus includes a substrate, a first integrated circuit disposed on the substrate at a first location, a second integrated circuit disposed on the substrate at a second location, and a third integrated circuit disposed on the second integrated circuit. The second integrated circuit is coupled to the first integrated circuit using a first chip-to-chip (C2C) interface via a physical terminal. The third integrated circuit is coupled to the first integrated circuit using a second C2C interface via the physical terminal. Only one of the first C2C interface and the second C2C interface is active at a time.

To provide a semiconductor package improved in reliability.SOLUTION: A semiconductor package includes an interconnection chip INC between a first chip stack CS1 and a second chip stack CS2, the interconnection chip including interconnection vias INV electrically connecting first through-vias TSV1 and second through-vias TSV2 to each other. The interconnection chip has a lower surface 210LS in contact with the first chip stack, an upper surface 210US in contact with the second chip stack, and a side surface between the lower surface and the upper surface. The side surface of the interconnection chip includes a first portion extending from the lower surface of the interconnection chip at a first inclination, and a second portion extending from the first portion to the upper surface of the interconnection chip at a second inclination lower than the first inclination.SELECTED DRAWING: Figure 1b