338 results about "Chip stacking" patented technology

The invention designs a broadband intermediate-frequency heterogeneous integrated communication transceiving micro module and a three-dimensional packaging method, and belongs to the technical field of advanced packaging. The micro module comprises a TSV silicon adapter plate, a Fan-out module, an HTCC ceramic substrate and a digital chip. The TSV silicon adapter plate adopts a high-resistance silicon substrate, and a coaxial shielding TSV structure is arranged on the TSV silicon adapter plate and comprises an inner layer signal through hole and an outer layer grounding layer. A frequency synthesizer chip and a radio frequency chip are embedded in the Fan-out module, and high-density horizontal interconnection is realized through a plurality of redistribution layers. The HTCC ceramic substrate is of a multi-layer laminated structure, and an impedance matching network is arranged in the HTCC ceramic substrate. The three-dimensional packaging method comprises the steps of TSV silicon adapter plate preparation, Fan-out module processing, digital chip stacking and system-level integration. High-density packaging of the radio frequency chip and the digital chip is achieved through the three-dimensional heterogeneous integrated architecture, and low-loss transmission of broadband signals is guaranteed through the coaxial shielding TSV structure and the impedance matching network.

Stacked semiconductor packages with features to mitigate trace exposer and associated systems and methods are disclosed herein. In some embodiments, the stacked semiconductor package includes a base substrate, a stack of dies carried by the base substrate, and a mold material deposited at least partially encapsulating the stack of dies. The base substrate can include an active surface and a back surface opposite the active surface. Further, the active surface can include one or more cuts into a peripheral portion of the active surface (e.g., stepped structures at the peripheral edges of the base substrate). The base substrate can also include a plurality of bond pads carried by the active surface over the peripheral portion. Still further, the mold material can fill each of the one or more cuts in the active surface, thereby insulating the bond pads from exposure at a sidewall of the stacked semiconductor package.

The invention relates to the technical field of semiconductor packaging and chip power supply, in particular to a three-dimensional chip stacking power supply system and method based on a power wafer, and the system comprises an integrated power wafer, a calculation chip and a power peripheral device. A high-density capacitor array is integrated in the integrated power supply wafer, a rewiring layer is formed on the surface of the integrated power supply wafer, and a distributed voltage regulation module is configured; the computing chip is a known qualified chip and is inversely mounted on the rewiring layer through a micro bump / copper column, and a power supply bonding pad is directly connected with a power supply node; the power supply peripheral device is attached to the free area of the integrated power supply wafer or the same packaging substrate. The method comprises the steps of prefabrication of an integrated power supply wafer, flip mounting of a computing chip, bottom filling and integration with a packaging substrate. Through chip-wafer integration, the power supply path is shortened, resistance and noise are reduced, precision pipe and heterogeneous integration is achieved, the yield is increased, cost is reduced, bidirectional heat dissipation is achieved, and the power supply method is suitable for high-performance chip power supply.

The invention relates to the technical field of semiconductors, provides a semiconductor device, and is used for solving the technical problem that a large lifting space still exists in a high-bandwidth memory technology. The semiconductor device includes: a chip stacking structure including a first semiconductor chip and a second semiconductor chip stacking structure stacked in a first direction; the first semiconductor chip comprises a controller, a calculation module and an interface module; the controller is configured to execute a first access operation on storage data in the second semiconductor chip stacking structure and send the storage data to the interface module to allow external equipment to access the storage data in the second semiconductor chip stacking structure through the interface module; and performing a second access operation on the storage data in the second semiconductor chip stack structure and sending the storage data to the computing module to allow the computing module to perform a computing operation on the storage data. Therefore, the integration level can be improved, the data transmission path can be shortened, and bandwidth consumption and energy consumption loss can be reduced.

Provided is a multi-dies stacking structure, which includes: a plurality of core dies stacked, wherein each core die comprises a first sub-core die and a second sub-core die vertically stacked; adjacent core dies are interconnected through micro-metal bumps, and the first sub-core die is interconnected with the second sub-core die through hybrid bonding members.

The invention provides a chip stacking structure, a manufacturing method thereof, a chip packaging structure and electronic equipment. The chip stacking structure comprises a first chip, at least one second chip and a supporting structure. Each second chip is located between the first chip and the supporting structure. The first chip is electrically connected with the second chips, and the supporting structure is connected with the second chips. An integrated passive device is arranged in the supporting structure, and the integrated passive device is electrically connected with at least one second chip; and / or the integrated passive device is electrically connected with the first chip. In the embodiment of the invention, the integrated passive device is integrated into the supporting structure, so that the integrated passive device, the second chip and the first chip can be stacked in the vertical direction, the interconnection distance between the second chip and / or the first chip and the integrated passive device can be greatly reduced, the integration level of the chip stacking structure is improved, the manufacturing cost is reduced, and moreover, the chip stacking structure is suitable for large-scale popularization and application. The substrate utilization rate of the supporting structure can be improved, and the internal structure of the chip stacking structure is reasonably utilized.

A semiconductor device includes: a wiring board having a surface; a chip stack disposed above the surface and including a first semiconductor chip; a second semiconductor chip disposed between the surface and the chip stack; a spacer disposed between the surface and the first semiconductor chip, the spacer surrounding the second semiconductor chip along the surface, and the spacer containing a material higher in thermal conductivity than silicon; and a sealing insulation layer covering the chip stack.

A semiconductor package includes a package substrate, a control chip, and a chip stack. A connection conductive pattern is on the top surface of the package substrate, spaced from the control chip. The package substrate has a first substrate pad, an extended interconnection line with first and second branch portions, and first and second interconnection lines. The control chip includes a mode selection pin and a chip connection terminal between the first substrate pad and the mode selection pin. The connection conductive pattern contacts the first branch portion and the first interconnection line but is spaced from the second branch portion and second interconnection line. A level of a top surface of the connection conductive pattern is lower than a level of a bottom surface of the control chip.

The invention discloses a CoWoS packaging technology for a GPU chip, and the technology comprises the following steps: S1, forming a glass substrate with a glass wafer as a temporary carrier, and coating a temporary bonding glue layer; s2, using a deep reactive ion etching technology to form a copper through silicon via, depositing an insulating layer and a barrier layer, patterning a metal wiring layer, and using a Cu Pin process to optimize TSV manufacturing to form a copper column interconnection structure; s3, forming a first EMC layer by using an epoxy molding compound; s4, the first EMC layer is thinned and flattened, the upper end face of the copper column is exposed, and the composition is defined as an intermediate layer; s5, making micro-bumps on the front surface of the interposer, and forming an insulating layer on the surface; and S6-S13, sequentially completing chip stacking, plastic packaging, glass substrate removal, C4 bump manufacturing, film pasting, cutting, butt joint and BGA ball implantation. According to the process, the TSV process is simplified through the CuPin process, the equipment investment is reduced by 40%, the productivity is improved by 30%, the process is compatible with the existing CoWoS-S process, and core equipment does not need to be transformed.

The invention discloses a stacked quantum chip supporting structure. The stacked quantum chip supporting structure comprises a first chip and a second chip, a cut-off layer is arranged on the end face between the first chip and the second chip, the cut-off layer is provided with multiple sets of limiting columns, and the first chip and the one or more second chips are aligned and bonded through the limiting columns to form a multi-layer stacked structure. According to the invention, a plurality of groups of limiting columns are arranged at the corresponding positions of one or more cut-off layers between the chips, so that the stress can be better balanced without influencing the wiring of the chips, the stress is more uniform and the chips are not deformed when the chips are subjected to flip-chip bonding or stacking design, and the sizes of the gaps between the chips can be determined by controlling the heights of the limiting columns, so that the yield of the chips is improved. Gaps and design are ensured to be consistent, and the problems of inclination, collapse and the like after multiple layers of chips are stacked are effectively solved; in addition, a lantern ring structure is formed by mutually embedding and connecting the coating cavities, so that the supporting stability is further improved, interconnected metal can be effectively prevented from overflowing to influence an external circuit structure, and the gap distance between the chips can be accurately controlled.

The utility model discloses a kind of co-encapsulation type light engine and networking.The co-encapsulation type light engine includes data processing bare core and the light chip stacked above the data processing bare core;The light chip is configured as the way of optical signal transceiver data;The data processing bare core is configured to process the data.The scheme provided by the utility model cancels silicon medium plate, adapter plate etc. intermediate substrate, further shorten transmission path, improve data transmission efficiency, in addition, this close coupling can also significantly reduce signal loss, improve high-speed signal integrity.

The invention relates to a chip stack package. Embodiments of the present disclosure provide a chip-on-package package, the chip-on-package package including: a first semiconductor chip having a front bump on a first surface; a second semiconductor chip stacked on a second surface of the first semiconductor chip opposite to the first surface; a carrier bump bonded to the front bump; a molding member surrounding the first semiconductor chip, the second semiconductor chip, and the carrier bump; and an external connection bump disposed on the carrier bump.

An apparatus and method for efficiently routing power signals across semiconductor dies. A semiconductor fabrication process (or process) places a first semiconductor die in an integrated circuit and stacks a second semiconductor die vertically adjacent to the first semiconductor die. The process forms multiple backside metal layers vertically adjacent to a backside of a silicon substrate of the second semiconductor die. The process forms a first backside metal layer that includes at least a first power route that forms a rectangle within the first backside metal layer. The process forms a second backside metal layer that includes at least a second power rail that forms an L-shape within the second backside metal layer. The process connects one or more corners of the rectangle of the first power rail to a corresponding corner of a separate power rail of the second backside metal layer that forms an L-shape.

This invention provides a silicon-based dielectric resonant antenna with adjustable beamwidth, comprising a beamwidth adjustment structure, an antenna substrate and a dielectric resonator, an excitation antenna, and solder bumps. The multilayer antenna substrate and dielectric resonator are arranged sequentially from top to bottom, with an air cavity formed in the middle. The excitation antenna is located at the bottom of the air cavity. The beamwidth adjustment structure is located on top of the top layer of the antenna substrate and dielectric resonator. A through-silicon via (TSV) is located in the middle of the bottom layer of the antenna substrate and dielectric resonator, with solder bumps located at the bottom of the TSV. This invention significantly reduces the antenna size and improves its radiation efficiency by using high-resistivity silicon as the antenna dielectric. By introducing an air cavity structure and adjusting the beamwidth through the top-layer beamwidth adjustment structure, the antenna application frequency can be changed according to usage, the feeding method can be modified and optimized according to application conditions, and it can be stacked with chips to achieve three-dimensional heterogeneous high-density integration.

The invention provides a semiconductor packaging structure and a preparation method, the semiconductor packaging structure comprises a circuit substrate and a second chip unit bonded on the surface of the circuit substrate, the second chip unit comprises multiple layers of stacked first chip units, and each first chip unit comprises a first chip and a second chip which are bonded up and down. A two-layer chip bonding structure is adopted as a single stacking unit, and compared with a single-layer chip, the structural strength is improved, so that larger internal stress can be borne during bonding, and buckling deformation is avoided. Besides, the preparation method adopts the technological process of bonding the wafers first and then cutting out the chip stacking units, so that the working efficiency and the productivity can be improved, particularly, multiple layers of wafers are stacked to form the wafer stacking body and then the second chip units are directly cut out, the subsequent process of stacking the first chip units one by one is omitted, and the production cost is reduced. And the manufacturing efficiency is further improved.

Microelectronic assemblies with a die stack positioned such that a face of each die in the stack is orthogonal to a face of a base are disclosed. Each die has a first face and a second face opposite the first face. The die stack includes multiple dies, with the faces of each die parallel to the faces of the other dies in the die stack. The die stack is positioned on the base such that the faces of each die are substantially orthogonal to the face of the base. Each die in the die stack can have a corresponding conductive contact, and the conductive contact on each die in the die stack can be coupled to a conductive contact on the base via an interconnect. The interconnect can be a solder joint, such as a solder bump or solder ball.

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a semiconductor device, the semiconductor structure comprising: a multilayer storage module stacked on the upper surface of the logic chip along a first direction, the first direction being perpendicular to the upper surface of the logic chip; the storage module comprising a plurality of storage chips stacked in a second direction, the second direction being parallel to the upper surface of the logic chip; the storage chip at the top layer having one second wireless communication unit; the storage chip at a non-top layer having two second wireless communication units arranged in the first direction and a wired communication unit connected between the two second wireless communication units; in the first direction, the two second wireless communication units arranged adjacently and located in different storage chips perform wireless communication; and the first wireless communication unit performs wireless communication with the second wireless communication unit in the bottom layer storage chip closest to the first wireless communication unit. The embodiment of the present disclosure can at least improve the capacity density and performance of the semiconductor structure.

The application provides a bonded substrate and a bonding method. A bonded substrate formed by bonding a first substrate and a second substrate comprises: an internal heat dissipation structure, which is a metal layer arranged around a metal column and embedded in at least one of the first substrate and the second substrate; and a heat conduction structure connected to the internal heat dissipation structure and exposed to a surface of the bonded substrate. The application can greatly improve the heat dissipation efficiency of a three-dimensional stacked chip by adding the internal heat dissipation structure, the external heat dissipation structure and the heat conduction structure without changing the existing chip stacking process, thereby solving the problems of increased power consumption and reduced working speed of the chip caused by the increased working temperature of the chip and the increased resistance of the wire, and prolonging the service life of the chip.

The utility model relates to the field of semiconductor packaging, in particular to a multi-layer chip stacking packaging structure. Comprising a supporting frame and an electric protruding block, the positioning protruding block is used for ensuring that chips can be accurately aligned during stacking, the supporting frame is used for supporting during stacking of the chips, poor electric connection caused by deformation and collapse of the electric protruding block due to excessive extrusion is prevented, and chip displacement caused by external force or vibration is also prevented. According to the packaging structure, the supporting frame and the positioning protruding block are matched, on one hand, the stacking precision is improved, the electrical connection problem caused by inaccurate alignment is reduced, on the other hand, chip displacement caused by external force or vibration in the stacking process of the packaging structure is prevented, supporting and alignment in the chip stacking process are considered, and the packaging quality is improved. Therefore, poor electrical connection caused by deformation and collapse of the electrical bumps due to excessive extrusion is prevented, displacement of the chips in the stacking process is also prevented, and the stability of the packaging structure is ensured.

The utility model belongs to the technical field of semiconductor chips, and discloses a multi-chip stacked packaging body, which comprises a packaging substrate, a plurality of groups of first-level chips are arranged on the packaging substrate, and a plurality of groups of second-level chips are arranged on one sides, deviating from the packaging substrate, of the plurality of groups of first-level chips. The plurality of groups of first-level chips and the plurality of groups of second-level chips are electrically connected with the packaging substrate, the plurality of groups of first-level chips and the plurality of groups of second-level chips are solidified and combined by adopting a packaging material, one surface, deviating from the packaging substrate, of a combined body is a passivation layer, a protective shell is arranged outside the combined body, the depth of the protective shell is higher than that of the passivation layer, and the passivation layer is arranged outside the protective shell. The packaging structure is compact and reasonable in structural design, the first-level chips and the second-level chips are stacked and packaged with the packaging substrate into a whole, more chips can be contained in the same occupied area, the packaging structure is compact and reasonable in structure design, the packaging structure is compact in structure, the packaging structure is compact in structure, the packaging structure is compact in structure, the packaging cost is low, and the packaging structure is suitable for large-scale popularization and application. And the integration level can be greatly improved.

The embodiment of the invention provides a chip stacking structure, and the structure comprises a first wafer which is provided with a first alignment mark; the second wafer is bonded with the first wafer, and the second wafer is provided with a second alignment mark; wherein the projection of the first alignment mark and the projection of the second alignment mark on the bonding surface have a preset position corresponding relation; each of the first alignment mark and the second alignment mark comprises at least one sub-mark which is in a rectangular ring shape on a plane parallel to the bonding surface.

The invention discloses a multi-chip stacking fan-out packaging structure and a packaging method thereof, and the method comprises the steps: providing a substrate and at least two chips with different sizes, and the substrate is provided with a first surface and a second surface which are opposite to each other; enabling the function surface of the first chip with the maximum size to face upwards, and mounting the first chip on the first surface of the substrate; the size of the second chip is smaller than that of the first chip, the function face of the second chip does not affect leading-out of a bonding pad of the first chip after surface mounting, and surface mounting is repeated until all the chips are mounted on the first chip; performing plastic packaging on the stacked structure on the substrate to form a plastic packaging layer, wherein the plastic packaging layer is a mixed material film layer formed by resin or glue and inorganic matter; and windowing on the plastic packaging layer by adopting a laser processing mode to form a first through hole. According to the fan-out packaging method, chips with different thicknesses do not need to be thinned, the process is simple, the cost is low, and a three-dimensional packaging structure can be achieved.

The utility model discloses a chip stacking packaging structure combined by multiple connection modes. The chip stacking packaging structure comprises a bare chip, a conductive column, a conductive bump, a rewiring layer and a packaging body, the bare crystal comprises a third bare crystal, a second bare crystal stacked on the third bare crystal in a staggered manner, and a first bare crystal stacked on the second bare crystal in a staggered manner; the conductive column corresponds to an electrode of the second bare crystal and is supported between an electrode surface of the second bare crystal and a bonding pad on the front surface of the rewiring layer; the conductive salient point corresponds to the electrode of the third bare crystal and is supported between the electrode surface of the third bare crystal and the bonding pad of the rewiring layer; a bonding wire electrically connected with the second bare crystal electrode and the first bare crystal electrode is arranged between the second bare crystal and the first bare crystal; the packaging body integrally wraps the bare crystal, the conductive columns and the conductive bumps; the back surface of the rewiring layer is provided with a welding pin which is electrically connected with a bonding pad on the rewiring layer. The chip stacking packaging structure is thin in thickness and low in cost.

The invention provides a chip stacking packaging structure and a manufacturing method thereof. The manufacturing method of the chip stacking packaging structure comprises the following steps: providing a bearing plate, and sequentially forming a first wiring layer and a first column on the bearing plate; forming a laminated structure comprising a first stacking structure and a second stacking structure which are stacked on the upper surface of the first wiring layer, wherein the first stacking structure and the second stacking structure respectively comprise a first chip and a first electrode column which are stacked in a staggered manner and a second chip and a second electrode column which are stacked in a staggered manner; providing a transfer plate with a second column formed on the bottom surface, electrically connecting the first column and the second column, and removing the transfer plate; forming a packaging layer, and thinning the packaging layer; forming a second wiring layer on the upper surface of the packaging layer; and forming a protective layer covering the exposed upper surface of the second wiring layer, and removing the bearing plate and the conductive bumps. According to the invention, the first chip and the second chip in the laminated structure are stacked in a staggered manner, and are combined with the first wiring layer, the second wiring layer, the first column and the second column, so that interconnection among the chips is realized, and meanwhile, the process difficulty and the manufacturing cost are reduced.

This relaxes the constraints on the layout of the stacked structure of semiconductor chips on which logarithmic transformation transistors and current-voltage transformation transistors used for event detection are formed. [Solution] The imaging device comprises a photoelectric conversion element, a logarithmic transistor that generates an optical voltage by logarithmically converting the optical current output from the photoelectric conversion element, and a current-voltage conversion transistor that converts the optical current into an output voltage based on the optical voltage generated by the logarithmic transistor. A second chip is stacked on a first chip on which the photoelectric conversion element is formed, and at least one of the logarithmic transistor and the current-voltage conversion transistor is formed on the first chip.

The invention provides a three-dimensional chip packaging structure and a manufacturing method, and relates to the technical field of integrated circuit manufacturing. The display device at least comprises a first substrate; the second substrate is arranged on the first substrate, and an accommodating space is formed between the second substrate and the first substrate; and the chip stacking structure is arranged in the accommodating space between the first substrate and the second substrate, and the chip stacking structure is electrically connected with the second substrate and the first substrate. According to the invention, the integrated three-dimensional integration of multiple chips can be realized, the integration level of the transistor and the function unit is obviously improved, the interconnection density and the space utilization rate are optimized, the problems of insufficient interconnection density, bottleneck of electrical interconnection performance and the like of the traditional packaging are solved, and the packaging efficiency is improved. The chip size is reduced, the data transmission rate and the overall efficiency of the system are effectively improved, and high-speed and low-delay data interaction is achieved.

This disclosure belongs to the field of semiconductor technology and addresses the problem of complex signal interconnections between memory chips and logic chips in three-dimensional chip stacking structures. It provides a memory chip, a logic chip, a chip stacking structure, and a memory. The memory chip includes 2A channel signal regions arranged sequentially along a first direction. Each channel signal region includes a first data signal region and a second data signal region arranged along the first direction. The first data signal region in the i-th channel signal region is symmetrical to the first data signal region in the (2A-i+1)-th channel signal region about a second axis, and the second data signal region in the i-th channel signal region is symmetrical to the second data signal region in the (2A-i+1)-th channel signal region about the second axis. Thus, after forming a three-dimensional chip stacking structure, the positions of the first and second data signal regions of the memory chip and the logic chip are aligned along a third direction, reducing the complexity of signal routing.

This invention relates to the field of stator chip processing technology, specifically to an automatic stator chip stacking device, comprising a frame, a positioning stacking module, a pressing module, an ejection module, and a mechanical transmission module. The positioning stacking module includes a mandrel and a straightening sleeve. The stator chips are inserted into the mandrel through their central holes to achieve stacking. Both the pressing module and the ejection module are connected to the mechanical transmission module. The pressing module descends as the mechanical transmission module rotates, applying a circumferential flattening action to the warped stator chips. Simultaneously, after pressing, the ejection module pushes the stator chips coaxially along the mandrel to complete the stacking feed. This invention synchronously drives the pressing and ejection actions through a shared mechanical transmission module, and uses a cam-rocker mechanism to coordinate the timing of flattening and pushing. The structure is simple and effectively avoids stacking misalignment or jamming.

A method for separating semiconductor die stacks of a chip-on-wafer assembly is disclosed herein. In one example, divider walls are arranged in a pattern on a first surface of a device wafer such that regions between the divider walls define mounting sites. Die stacks are mounted to the device wafer, wherein individual die stacks are located at a corresponding mounting site between the divider walls. The device wafer is cut through from a second surface that is opposite the first surface of the device wafer, and the divider walls are removed from between the die stacks to form a vacant lane between adjacent die stacks.