1061 results about "Chip carrier" patented technology

A process for fabricating a leadless plastic chip carrier includes selectively etching at least a first surface of a leadframe strip to partially define at least a plurality of contact pads and a die attach pad; selectively plating at least one layer of metal on a second surface of the leadframe strip, on an undersurface of at least the plurality of contact pads and the die attach pad; mounting a semiconductor die on the first surface, on the partially defined die attach pad; wire bonding the semiconductor die to ones of the contact pads; encapsulating the wire bonds and the semiconductor die in a molding material such that the molding material covers a first portion of the die attach pad and first portions of the contact pads; selectively etching a second surface of the leadframe strip to define a second portion of the contact pads and a second portion of the die attach pad by etching the second surface with the at least one layer of metal resisting etching; and singulating the leadless plastic chip carrier from the leadframe strip.

A process for fabricating a leadless plastic chip carrier includes laminating a first metal strip to a second metal strip to form a leadframe strip, selectively etching the first metal strip to define at least a row of contact pads, mounting a semiconductor die to either a die attach pad or the second metal strip and wire bonding the semiconductor die to ones of the contact pads, encapsulating a top surface of the leadframe strip in a molding material, removing the second metal strip, thereby exposing the die attach pad and the at least one row of contact pads, and singulating the leadless plastic chip carrier from the leadframe strip.

A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.

A leadless plastic chip carrier is fabricated by selectively etching a leadframe strip to reduce a thickness of the strip at a portion thereof. Selectively masking the surface of the leadframe strip using a mask, follows selectively etching, to provide exposed areas of the surface at the portion and contact pad areas on leadframe the strip. At least one layer of metal is deposited on the exposed areas to define a die attach pad on the portion of the leadframe strip with reduced thickness and to define contact pads on the surface of the strip. At least one semiconductor die is mounted to the die attach pad, followed by wire bonding the at least one semiconductor die to ones of the contact pads. The at least one semiconductor die, the wire bonds, and the contact pads are covered with an overmold material and the leadframe strip is etched to thereby remove the leadframe strip. The leadless plastic chip carrier is singulated from the leadframe strip.

Nanotube ESD protective devices and corresponding nonvolatile and volatile nanotube switches. An electrostatic discharge (ESD) protection circuit for protecting a protected circuit is coupled to an input pad. The ESD circuit includes a nanotube switch electrically having a control. The switch is coupled to the protected circuit and to a discharge path. The nanotube switch is controllable, in response to electrical stimulation of the control, between a de-activated state and an activated state. The activated state creates a current path so that a signal on the input pad flows to the discharge path to cause the signal at the input pad to remain within a predefined operable range for the protected circuit. The nanotube switch, the input pad, and the protected circuit may be on a semiconductor chip. The nanotube switch may be on a chip carrier. The deactivated and activated states may be volatile or non-volatile depending on the embodiment. The ESD circuit may be repeatedly programmed between the activated and deactivated states so as to repeatedly activate and deactivate ESD protection of the protected circuit. The nanotube switch provides protection based on the magnitude of the signal on the input pad.

This invention provides a semiconductor package and a method for fabricating the same. The method includes: forming a first resist layer on a metal carrier; forming a plurality of openings penetrating the first resist layer; forming a conductive metal layer in the openings; removing the first resist layer; covering the metal carrier having the conductive metal layer with a dielectric layer; forming blind vias in the dielectric layer to expose a portion of the conductive metal layer; forming conductive circuit on the dielectric layer and conductive posts in the blind vias, such that the conductive circuit is electrically connected to the conductive metal layer via the conductive posts; electrically connecting at least one chip to the conductive circuit; forming an encapsulant for encapsulating the chip and the conductive circuit; and removing the metal carrier, thereby allowing a semiconductor package to be formed without a chip carrier. Given the conductive posts, both the conductive circuit and conductive metal layer are efficiently coupled to the dielectric layer to prevent delamination. Further, downsizing the blind vias facilitates the fabrication process and cuts the fabrication cost.

An automated inspection system particularly adapted for detection and discrimination of surface irregularities of specularly reflecting and other materials, such as are employed in laminate chip carriers and printed circuit boards, includes an area scan image sensor allowing illumination sources to surround an area of a surface being inspected. The illumination source preferably provides either or both bright field and dark field illumination of the surface; developing generally complementary images of surface irregularities. A self-registering rules-driven process for developing inspection masks reduces alignment operations and improves performance. Image enhancement and morphological operations to detect surface irregularities are performed by digital signal processing, preferably using a dedicated vision processor. Masks screen potential defects to critical mounting and bonding surfaces accurately without requiring alignment of data or reference images to acquired images. Since potential defects are copied from acquired images and stored, verification of defects may be performed without further access to the inspected part and without removal of the part to another specialized apparatus, simplifying processing and increasing throughput and operator efficiency.

A quad flat no-lead chip carrier for a wire-bonded chip package is provided. The chip carrier comprises a conductive plate, a plurality of conductive columns and a plurality of dielectric walls. A chip is attached to the conductive plate. The conductive plate furthermore has a plurality of columnar through holes distributed around a chip-bonding region. The conductive columns are set up within the columnar through holes. The dielectric walls are set up between the sidewall of the conductive columns and the inner surface of the columnar through holes. The chip is electrically connected to the conductive columns via conductive wires. The bottom end of the conductive columns serves as input/output contacts for connecting with external contacts. The chip carrier is able to increase overall density of the input/output contacts and improve the electrical performance of the chip package.

A packaged semiconductor chip includes features such as a chip carrier having a large thermal conductor which can be solder-bonded to a circuit board so as to provide enhanced thermal conductivity to the circuit board and electromagnetic shielding and a conductive enclosure which partially or completely surrounds the packaged chip to provide additional heat dissipation and shielding. The packaged unit may include both an active semiconductor chip and a passive element, desirably in the form of a chip, which includes resistors and capacitors. Inductors may be provided in whole or in part on the chip carrier. A module includes two circuits and an enclosure with a medial wall between the circuits to provide electromagnetic shielding between the circuits.

A heat sink in a heat transfer relationship with a substrate such as an integrated chip, chip carrier, or other electronic package. The heat sink is connected to a frame which is connected to a printed circuit board or other suitable support on which the substrate is positioned. The heat sink, which extends through an aperture in the frame is coupled to a surface of the substrate. The heat sink is mechanically decoupled from the substrate. Large heat sinks may be thermally connected to surface mount substrates mounted using technologies such as ceramic ball or column grid arrays, plastic ball or column grid arrays, or solder balls or columns. The heat sink is attached coaxially through the aperture to the substrate. After assembly and lead/tin or other metallic surface mount interconnects are relaxed such that the substrate and is completely supported by the frame and the heat sink imparts zero or nearly zero downward force. Because the heat sink moves freely within the aperture during assembly, the heat sink package is useful for a variety of different substrates. Preferably, the frame is a plate and a plurality of studs. The plate material are selected to match the thermal expansion of the underlying support, and the stud material matched the thermal expansion of the substrate. Thus, the frame construction allows matching expansion and contraction of the assembly to the underlying substrate and support.

Integrated circuit (IC) packages employing two-phase microchannel heat exchangers for cooling the packages' IC dies and cooling systems employing the same are disclosed. The heat exchangers include thermal masses having a plurality of microchannels formed therein. In one set of configurations, the IC die is thermally coupled to a pair of microchannel heat exchangers disposed on opposite sides of the die. Top-side microchannel heat exchangers include a thermal mass having a plurality of open microchannels having wall bases that are hermetically sealed with the top surface of the die, thus forming a plurality of closed microchannels. Alternatively, a separate microchannel heat exchanger is thermally coupled to an IC die and operatively coupled to the IC die via coupling to a substrate on which the IC die is mounted. Bottom-side heat exchangers include substrates and chip carriers having microchannels formed therethrough that are thermally coupled to the IC die. The cooling systems employ a plurality of microchannel heat exchangers to cool selected electronic components.

Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

A carrier for a sweep-type fingerprint sensor and a method of operation are disclosed. The carrier has a recess for receiving and mounting the fingerprint sensor and one or more tactile elements for assisting the user in positioning a finger, and in correctly moving the finger across the sensor being read. In one embodiment the tactile element consists of an oval ridge, or a portion thereof, defining a major axis which is lies in the sweep direction. The tip of the finger is initially positioned in the arcuate portion of the oval ridge and is moved across the sensor, generally along the axis of the oval. The side walls of the ridge assist the user in correctly moving the finger across the sensor.

An efficient cooling mechanism for a multi-chip carrier can be provided while conserving board surface area. Flexible circuitized material is used to form multi-chip carriers with air baffle capability. The flex is folded or curved into the desired shape and held in position with a support structure. Bonding sites for chips are located on regions through the carrier. Shapes which provide air baffle capabilities include coils, spring-like coils and serpentines.

A multi-chip lighting module is disclosed for maximizing luminous flux output and thermal management. In one embodiment, a multi-chip module device comprises a substantially thermally dissipative substrate with a dark insulating layer deposited on a surface of the substrate. A plurality of light emitting devices is also provided. An electrically conductive layer is applied to a surface of the substrate, with the conductive layer comprising a plurality of chip carrier parts each having a surface for carrying at least one of the light emitting devices. Each light emitting device has a first and a second electrical terminal. A reflective layer is also provided that at least partially covers the conductive layer.

The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and solder pads corresponding to the holes so as to form a through silicon via (TSV) structure; forming at least one groove on a second surface of each of the first chips to expose the metal posts of the TSV structure so as to allow at least one second chip to be stacked on the first chip, received in the groove and electrically connected to the metal posts exposed from the groove; filling the groove with an insulating material for encapsulating the second chip; mounting conductive elements on the solder pads of the first surface of each of the first chips and singulating the wafer; and mounting and electrically connecting the stacked first and second chips to a chip carrier via the conductive elements. The wafer, which is not totally thinned but includes a plurality of first chips, severs a carrying purpose during the fabrication process and thereby solves problems, namely a complicated process, high cost, and adhesive layer contamination, facing the prior art that entails repeated use of a carrier board and an adhesive layer for vertically stacking a plurality of chips and mounting the stacked chips on a chip carrier.

A stacked multichip package comprises a first chip having a first active surface and a first rear surface, a first chip carrier having a first opening and being configured to carrier the first active surface, a plurality of first conductive leads passing through the first opening and being configured to electrically connect the first active surface and the first chip carrier, a second chip having a second active surface and a second rear surface, an adhesive layer configured to enclose the first conductive leads and to electrically couple the first chip carrier to the second rear surface, a second chip carrier having a second opening and being electrically connected to the second active surface, and a plurality of conductive leads passing through the second opening and being configured to electrically connect the second active surface and the second chip carrier.

A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art. In still another embodiment, at least two spaced-apart conductors may be formed within a metal layer deposited on a dielectric layer, these conductors defining a channel there-between. The capacitive dielectric material may then be deposited (e.g., using lamination) within the channels.

A method for temporary chip attach to determine known good die using a reworkable conductive adhesive interconnection between the chip carrier and die. The die is easily separated from the chip carrier after test, without the use of potentially damaging shear forces, by subjecting the TCA assembly to a rework solution.

The equipment for transporting chips carrying coded information includes a movable structure carrying chips with an electronic circuit arranged in columns in stacked racks and a docking station for the carrier structure in the place of storage of the chips, for example the vault of the casino, or at their place of use, for example a gaming table. The carrier structure includes a plane base divided by a partition with a handle for carrying two stacks of racks of chips and a lid. The docking station integrates part of an RFID contactless radio-frequency reading station for reading the coded information carried by the chips of at least one column to determine or verify the content of at least one batch of chips present in the carrier structure, in particular to draw up or to check an inventory thereof. The read station includes a read unit with a digital section and an analog section provided with a wide-loop antenna with three loops respectively integrated into the walls of the lid and the median partition fixed to the plane base.