333 results about "Chip carrier" patented technology

The invention provides an optical anti-shake assembly and a long-focus camera module, the optical anti-shake assembly is suitable for driving a photosensitive assembly of the camera module to move, the optical anti-shake assembly comprises a base and a support, and the support is fixed on the base; the chip carrier is movably arranged on the base and is suitable for driving the chip carrier to move relative to the base and the bracket; the driving assembly is configured to drive a chip carrier to move in the horizontal direction, the driving assembly comprises at least one first driving mechanism and at least one second driving mechanism, the first driving mechanism is arranged between the chip carrier and the support, and the second driving mechanism is arranged between the chip carrier and the support. The driving chip carrier moves along a first horizontal direction relative to the bracket; the second driving mechanism is arranged between the chip carrier and the base and drives the chip carrier to move relative to the support in the second horizontal direction.

The embodiment of the invention provides a chip carrier plate and a manufacturing method thereof, a chip packaging structure, and a manufacturing method of the chip carrier plate, and the method comprises the steps: forming a first protection layer on a first surface of a glass substrate, forming a plurality of first through holes in the first protection layer, carrying out the laser induction of the glass substrate through the first through holes, and forming a plurality of induction regions, and in the induction area, etching the glass substrate to form a plurality of second through holes penetrating through the glass substrate, and forming conductive connection parts in the second through holes. The first protection layer with the first through hole is manufactured on one side of the glass substrate, the first protection layer exposes the area, needing laser induction, on the glass substrate, the area, not needing laser induction, on the glass substrate is protected, and it is avoided that when the glass substrate is etched subsequently, etching damage is caused to other positions of the surface of the glass substrate. Therefore, the thickness of the glass substrate can be ensured, and the surface quality such as roughness of the surface of the glass substrate can be ensured.

The invention discloses chip appearance detection equipment which comprises a marble carrying table, a chip carrier supply device, a chip visual detection device, a chip carrier output line and a chip carrier turnover device, wherein the chip carrier supply device, the chip visual detection device, the chip carrier output line and the chip carrier turnover device are arranged on the marble carrying table; the chip carrier supply device comprises a chip carrier bearing mechanism; the chip visual detection device comprises a detection bearing mechanism and an image acquisition mechanism, the detection bearing mechanism comprises a horizontal carrying table and a reset detection part, the image acquisition mechanism comprises an image carrying seat and a position degree monitoring sensor, and the image carrying seat is provided with a macro camera shooting end; the macro camera shooting end is connected with a correction module which is in communication connection with the location degree monitoring sensor; the chip carrier turnover device comprises a turnover mechanical arm. The micro-chip appearance micro-distance detection requirement is met, the detection image quality is ensured through correction of the relative position degree of the machine position and the platform, defect detection and recognition are accurate and comprehensive, the detection precision maintaining period is long, and frequent manual calibration is not needed. And automatic operation is efficient and smooth.

A method of manufacturing a chip structure is provided. The method includes attaching a chip to a chip carrier using a chip attachment layer, where the chip attachment layer includes a metal having a first melting point, where the chip includes a solder layer, and the chip carrier includes a further solder layer, where the solder layer includes a metal having a second melting point. The solder layer and / or the further solder layer comprises a respective solder material having a second melting point lower than the first melting point; and forming an intermetallic phase between the solder material and the metal of the die attach layer by melting the solder material having the second melting point.

According to the chip testing method provided by the invention, the single bare chip is tested after the wafer is cut, so that defects or unqualified products which may not be found in a wafer level test can be identified more accurately. The defects may be introduced in the wafer cutting process, such as cutting damage, pollution and the like. Therefore, the test method can effectively improve the yield of final products, and reduces resource waste and cost increase caused by the fact that unqualified bare chips flow into subsequent production links. The bare chips are placed in the chip carriers, then the chip carriers are placed on the tray, batch testing is carried out through the tray, the design enables the testing process to be more flexible, different chip carriers can be designed according to different bare chips, different chip carriers can be placed in the tray, and testing of different bare chips can be compatible. Moreover, the distance between the detection bonding pads of the chip carrier is relatively large, so that a tester can test the bare chip through the detection bonding pads.

A torsional micro-electro-mechanical systems (MEMS) mirror module provides for thermally-stable ancillary modes of mirror oscillation (e.g., vertical, horizontal, and rocking) by utilizing MEMS die packaging techniques that implement a cantilevered (i.e., fixed-free) die package in which one end of the die is partially fixedly-attached to a die carrier substrate while the non-attached end of the die is free from the die carrier substrate and unsupported. The cantilevered die package with fixed-free architecture effectively decouples the effects of coefficient of thermal expansion (CTE) mismatch of the MEMS die, die-bond adhesive, and die carrier substrate on temperature-dependent MEMS flexure stress. Ancillary mode oscillation frequencies changes with temperatures are thus limited to a smaller range relative to those experienced with conventional package designs.

The invention discloses an FA coupling device of a PLC optical chip and a coupling method thereof, and the FA coupling device of the PLC optical chip comprises a PLC optical chip carrier mechanism, and a left six-axis FA clamping mechanism 1, a right six-axis FA clamping mechanism and a left six-axis FA clamping mechanism 2 which are arranged at the periphery of the PLC optical chip carrier mechanism. The upper UV mechanism and the upper visual mechanism are located above the PLC optical chip carrier mechanism; and one side of the PLC optical chip carrier mechanism is also provided with a side visual detection mechanism. The invention discloses a PLC optical chip FA coupling device which is convenient to operate and high in coupling stability and a coupling method of the PLC optical chip FA coupling device. The flexibility of spatial position alignment of the FA optical fiber and the PLC optical chip is improved, the positioning of the light emitting position of the PCL optical chip is flexible, the clamping mode of the FA facilitates the realization of coupling and the angle adjustment of dispensing, and the dispensing of the upper part and the bottom part is facilitated.

The invention discloses feeding and discharging equipment of a chip carrier and a chip testing system, and relates to the technical field of semiconductor chip testing, and the feeding and discharging equipment comprises a rack, a positioning mechanism, a material box and a transfer mechanism; feeding and discharging stations are arranged on the two sides of the machine frame. The positioning mechanism is arranged at the top of the rack; the material box is arranged at the top of the positioning mechanism; the transfer mechanism is installed on the rack, a plurality of sensors are arranged on the transfer mechanism, and the plurality of sensors are used for obtaining the number information and the position information of the chip carriers placed in the material box; the transferring mechanism is used for taking out the chip carrier in the material box, transferring the chip carrier to the positioning mechanism for positioning, and transferring the positioned chip carrier to a feeding and discharging station; the transferring mechanism is further used for transferring the chip carriers on the feeding and discharging station to the positioning mechanism to be positioned, and the positioned chip carriers are placed in the material box. The loading and unloading equipment can realize automatic loading and unloading of the two external probe testing machines, and is higher in efficiency.

An on-board computer includes a microprocessor chip with a lower face and an upper face, a chip carrier having an upper face on which the microprocessor chip is mounted, and a casing configured to discharge heat generated by the microprocessor chip in operation. An interposer is disposed between the upper face and the casing. The interposer diffuses the heat transmitted by the upper face of the microprocessor chip towards the casing. The interposer has an upper surface for heat exchange with the casing that is twice or more greater than the surface area of the upper face of the microprocessor chip. The interposer has on one or more sides a peripheral wedging rim coming into contact with a side wall of the chip carrier, and has no more than two peripheral wedging rims, in order to leave the other sides of the interposer free.

The invention discloses a chip carrier plate flexible leveling system and a control method, and relates to the technical field of photoetching machine parts and chip production. According to the scheme provided by the invention, a parallelism detection device constructed based on a strain detection device is utilized, and a mapping relation between a strain value and an inter-plate distance is established; during use, a plurality of parallelism detection devices are arranged between a chip carrier plate and a target substrate, high-precision parallelism measurement and feedback adjustment are realized through a mapping relation between strain values and inter-plate distances and based on numerical value differences of strain measurement values, accurate inter-plate parallelism adjustment is realized, and the accuracy of the inter-plate parallelism is improved. The technical problem that an existing leveling system is large in parallelism detection and leveling effect error is solved.

A method for manufacturing an optoelectronic device comprises steps for providing a chip carrier having a top surface on which an optoelectronic semiconductor chip is arranged, for providing a protective film having a top surface and a bottom surface, for arranging a silicone layer on the top surface of the chip carrier, wherein the optoelectronic semiconductor chip is embedded in the silicone layer, and for laminating the bottom surface of the protective film onto the silicone layer.

Diagnostic chip devices, and methods and devices for assembly and manufacture, are described. Such chip device includes a chip carrier device that includes a frame having a fluidic interface, one or more fluidic channels and a gasket that forms a flowcell sealed against an active surface of a diagnostic chip. The gasket can be overmolded into the frame, or can be separately applied and compressed by the chip, which can be secured to the frame by cold swaging, hot swaging or heat staking, adhesive or any suitable means. The chip carrier device can further include a window over the flowcell to allow for optical detection of the active face of the chip. The window can be formed by a transparent lid or glass insert attached to the frame by laser welding, overmolding, adhesive or any suitable means. The carrier and lid can also be formed as a single integral component.

The invention relates to the technical field of semiconductor device packaging, in particular to an LED light-emitting chip packaging method. The method comprises the following steps: S1, selecting an LED light-emitting chip according to a user demand; s2, carrying out cleaning and wafer expansion treatment on the chip bearing piece; s3, fixing the LED light-emitting chip on the bonding pad of the chip bearing piece; s4, the LED light-emitting chip is covered with fluorescent glue; and S5, carrying out curing treatment on the fluorescent glue. According to the invention, the optical effect of an LED product can be improved.

The invention relates to a key management method and device based on a quantum security chip carrier, and relates to the technical field of quantum computing, a unique UID is generated through a quantum random number generator in combination with a PUF technology, a mapping relation is established, sub-keys are derived in a layered mode and stored in a partitioned mode, and the key management efficiency is improved. A ternary binding mechanism of a chip unique identity, a quantum random entropy source and a storage environment fingerprint is constructed, through integrity verification, bidirectional identity authentication and a quantum secure transmission channel, key full-life-cycle security control is realized, quantum attacks and security threats are effectively resisted, and the security, credibility, traceability and suitability of key management are improved.

The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

The present invention discloses a Micro-LED chip carrier substrate and a manufacturing method thereof. The Micro-LED chip carrier substrate includes a substrate, a connection layer connected to the front surface of the substrate on the back surface, and a plurality of microstructures disposed on the front surface of the connection layer. The microstructures have elasticity, and each microstructure is arranged in an array on the front surface of the connection layer. The Micro-LED chip carrier substrate of the present invention is used for temporarily bonding with a Micro-LED chip. When the Micro-LED chip is peeled off from a sapphire substrate by using a laser lift-off technology (LLO), the Micro-LED chip carrier substrate can effectively prevent the Micro-LED chip from cracking and / or shifting in position.

The invention provides an FCBGA chip support plate process parameter optimization method, system and device and a medium, and belongs to the technical field of PCB production, the method comprises the following steps: collecting and preprocessing a historical data set in the FCBGA chip support plate production process, and screening data subsets with correlation greater than a preset threshold based on target features of a to-be-optimized production task; training a machine learning prediction model capable of mapping the process parameters to the quality indexes; constructing a multi-objective optimization function by taking a machine learning prediction model as a core; a multi-objective optimization algorithm is adopted to search in the process parameter constraint space, and a Pareto optimal solution set is solved; and selecting a final optimal process parameter according to a preset decision strategy, applying the final optimal process parameter to an actual production line of the FCBGA chip carrier plate, then collecting actual production result data, and feeding back the actual production result data to a historical data set. The method is based on historical data machine learning multi-objective optimization, incremental learning dynamically adapts to production line changes, and quality and efficiency are improved.

The utility model provides a chip dismounting clamp and a dismounting assembly, the chip dismounting clamp comprises a clamp main body, a dismounting part, a force application part and an inclined part, the clamp main body is provided with a positioning part, the positioning part is provided with an opening part, and the positioning part is used for accommodating at least part of an ink box so as to position the ink box; the dismounting part is installed on the clamp body and used for dismounting a chip assembly on the ink box. The force application part is installed on the clamp body and used for receiving external force to drive the ink box to move in the direction close to the dismounting part so that the dismounting part can dismount the chip assembly on the ink box. The ink box is pushed by the force application part to move towards the direction of the disassembly part, so that the disassembly part can disassemble the chip assembly on the ink box, the disassembly mode can avoid damage to the ink box, and meanwhile, the disassembled chip bearing part is small and is convenient to recycle and install again.

The present invention discloses a method for preparing a thick biaxially oriented liquid crystal polymer film, which is characterized by: adding LCP resin to a drying tank, drying it, and then putting it into a melt extrusion device for melt extrusion; the molten LCP resin is extruded through a T-die, and the formed LCP sheet flows onto a steel belt below, and the temperature of the steel belt is controlled by a hot air plate below; the LCP sheet runs on the steel belt, and then a circulating needle-punched belt is brought into contact with both sides of the LCP, and the LCP sheet is extended in the horizontal direction by the uniform movement of the needle-punched belt, and then peeled off from the steel belt after natural cooling; the LCP film is subjected to high-temperature heat setting and then cooled to obtain a thick biaxially oriented liquid crystal polymer film. The liquid crystal polymer film prepared by the present invention has the characteristics of high mechanical strength, uniform longitudinal and transverse tensile strength, and relatively thick thickness, and can be widely used in the fields of rigid high-frequency and high-speed copper-clad laminates, high-temperature resistant sheets, wireless charging insulation sheets, flame-retardant sheets, chip carriers, etc.

The invention relates to a jet type liquid cooling heat dissipation device for an electronic chip and a working method of the jet type liquid cooling heat dissipation device. The device comprises a chip carrier provided with an electronic chip, a base, a jet flow guide plate, a backflow collection plate, a cover plate and a connector, the base is installed on the chip carrier in a sealed mode, and the jet flow guide plate, the backflow collecting plate and the cover plate are sequentially stacked and mutually connected in a sealed mode and are integrally fixed to the base. A first through hole and a second through hole are formed in the position, above the electronic chip, of the jet flow guide plate, a cooling liquid through hole and a cooling liquid guide hole are formed in the backflow collection plate, and a first cooling liquid connector and a second cooling liquid connector are formed in the cover plate. Compared with the prior art, through the collaborative design of the jet flow guide plate and the backflow collection plate, cooling liquid directly impacts the surface of an electronic chip in a high-speed jet flow mode, and therefore the local heat exchange efficiency is remarkably improved; and meanwhile, a backflow path is optimized, flowing resistance is reduced, high heat exchange performance and low pressure drop are both considered, and the heat dissipation device is suitable for efficient heat dissipation of high-heat-flux electronic chips.

A method for producing an optoelectronic component comprises steps of: providing a chip carrier (100) having a top side (101) on which an optoelectronic semiconductor chip (110) is positioned; providing a protective film (200) having a top side (201) and a bottom side (202); positioning a silicone layer (120) on the top side of the chip carrier (100), such that the optoelectronic semiconductor chip (110) is embedded in the silicone layer (120); and laminating the bottom side of the protective film (200) onto the silicone layer (120).

This invention relates to the field of semiconductor technology, and more particularly to a packaging frame, packaging structure, and heat dissipation device for SiC MOS applications. It includes: a first frame comprising a heat dissipation island and a first pin portion connected in sequence; the top surface of the heat dissipation island is located above the first pin portion, and a chip carrier area is provided at its bottom; a stepped area is provided at the edge of the top surface of the heat dissipation island; a chamfered step is provided between the stepped area and the first pin portion; the thickness of the heat dissipation island is greater than the thickness of the first pin portion; and a second frame is spaced apart and disposed on the side of the first frame. This invention achieves decoupling of electrical connections and heat conduction paths, significantly improving thermal management capabilities, enhancing heat dissipation capabilities, and reducing system thermal resistance. The top heat dissipation design improves Rth(j-a) by approximately 20% and Rth(j-h) by approximately 50% compared to traditional bottom heat dissipation; it also addresses the requirement of achieving a maximum operating junction temperature of 175~200℃ for SiC chips.

The present application relates to a kind of anti-shake camera module, it includes: module shell;Intermediate support seat, it is arranged in module shell and the space in module shell is divided into upper chamber and lower chamber;Optical lens, it is set in the upper chamber;Lens OIS carrier, the optical lens is installed in the lens OIS carrier;Photosensitive chip, it is set in the lower chamber;Chip OIS carrier, the photosensitive chip is fixed in the chip OIS carrier;Lens OIS ball, it is arranged between the bottom surface of the lens OIS carrier and the upper surface of the intermediate support seat;And chip OIS ball, it is arranged between the top surface of the chip OIS carrier and the lower surface of the intermediate support seat.The anti-shake camera module of the present application is easy to assemble, can effectively control module height, has big anti-shake stroke and has AF function.

The utility model discloses a chip carrier device for biochemical synthesis and a biochemical synthesis system. The chip carrying table device comprises a carrying table main body which is provided with a cavity with a downward opening, the top of the cavity is provided with a chip installation area, and the chip installation area is provided with a plurality of through holes; the carrying table support is positioned below the carrying table main body; the carrying table support is connected with the carrying table main body through a rotating pin; an angle adjusting assembly is arranged on the carrying table support, and the carrying table body has the freedom degree of horizontally rotating around the center of the rotating pin under the adjusting effect of the angle adjusting assembly. A sealing assembly matched with the cavity is arranged on the carrying table support; a negative pressure adsorption assembly is arranged below the sealing assembly and communicates with the cavity through a pipeline. And the cavity forms a negative pressure environment facing the plurality of through holes under the action of the negative pressure adsorption assembly so as to adsorb the chip covering the chip mounting area. The device can meet different requirements of positioning, position adjusting, fixing and the like of the chip, and precise positioning and precise sealing of the chip are achieved.

The invention discloses a batch automatic test method and system for flip chip interconnection connection conditions. The method comprises the steps of performing calibration setting on target adjustment parameters according to a preset alignment position and a preset needle insertion position; sending a starting signal to the control device, so that the control device generates a test signal in response to the received starting signal; the following steps are iteratively executed until all the alternative chips to be tested in the chip carrier are tested: a test signal sent by the control device is received, the test signal comprises information of a target chip to be tested, and the target chip to be tested is any one of the batch of alternative chips to be tested; according to a pre-generated automatic identification template, the target to-be-tested chip information and the target adjustment parameters, moving until a reading circuit bonding pad of the target to-be-tested chip is in contact with a probe on the probe card to obtain electrical connection test data of the target to-be-tested chip; and sending the test data to the control device. The test efficiency can be greatly improved, the time cost is saved, and the test consistency is improved.

The invention provides a temperature control testing device for a high-temperature chip. The temperature control testing device comprises an inner-layer temperature control structure and an outer-layer temperature control structure, the outer-layer temperature control structure comprises an air isolation cover and a bottom substrate, and the air isolation cover is fixed on the upper surface of the bottom substrate to define a high-temperature inner cavity; the inner-layer temperature control structure is provided with a chip carrying table which is arranged in the high-temperature inner cavity, the upper surface of the chip carrying table carries a chip, and a vacuum adsorption device with a plurality of adsorption holes is integrated. The inner layer temperature control structure and the outer layer temperature control structure are connected through a plurality of low-heat-conductivity connecting columns. An inner-outer double-layer temperature control structure design is adopted, and heat conduction is weakened through the low-heat-conductivity connecting columns. The outer layer forms a closed high-temperature inner cavity through an air isolation cover, and is integrated with a high-boron glass observation window and a slidable partition plate; the temperature of the inner layer is controlled through a chip carrier, and a vacuum adsorption device is integrated to fix a chip. The outer layer isolates outside airflow, the inner layer reduces the temperature difference between the chip and the cavity, closed-loop temperature control is achieved through the inner heating element, the outer heating element and the temperature sensor, the problem that temperature fluctuation of single-layer temperature control is large is solved, and stable temperature control is achieved.

The application provides a chip carrier plate, a preparation method thereof and a chip packaging structure. The chip carrier plate comprises a core layer, a conductive column, a first wiring layer and a second wiring layer. The core layer is provided with a conductive hole, and the cross-sectional shape of the conductive hole parallel to the plane where the core layer is located comprises a ring shape. The conductive column is arranged in the conductive hole, and the cross-sectional shape of the conductive column parallel to the plane where the core layer is located comprises a ring shape. The first wiring layer and the second wiring layer are arranged on both sides of the core layer and are electrically connected with the conductive column. The application designs the conductive hole and the conductive column as a ring structure, thereby increasing the contact area between the conductive column and the core layer, reducing the pressure intensity borne by the core layer in the chip packaging process, and greatly reducing the risk of cracks in the core layer.

This invention provides an anomaly tracing system and method for chip carrier tray damage, belonging to the field of semiconductor chip testing technology. The system includes: a cabinet storage detection system for acquiring and sending six-sided images of the damaged tray to a tray damage tracing system; the tray damage tracing system compares the six-sided images of the damaged tray with the six-sided images of the corresponding normal tray. If the deviation of any region on any face is greater than or equal to a preset value, the region is marked as a candidate damage region, and feature point coordinates are extracted to construct a polygon; the smallest bounding polygon covering all vertices of the polygon is compared with the rectangular region of the corresponding contact position of the mechanism. If there is a spatial intersection between the two, the mechanism is determined to be a highly correlated suspected mechanism causing the tray damage. This invention achieves automated identification and accurate correlation between damaged areas and interference points.

A semiconductor device is disclosed. The semiconductor device includes a chip carrier having a first cavity and a second cavity. A semiconductor die is mounted in the first cavity. The semiconductor die includes a patterned top metallization layer having a first electrical contact pad. An insulating layer is arranged inside the second cavity. A first end of a first electrical conductor is arranged over the insulating layer and a second end of the first electrical conductor is arranged on the first electrical contact pad of the semiconductor die. An encapsulant encapsulates the semiconductor die, both ends of the first electrical conductor, and parts of the chip carrier. A method for manufacturing the semiconductor device is also disclosed.

The invention discloses a packaging structure design and a packaging process of a multi-channel driving circuit, and relates to the technical field of microelectronic device packaging. Which comprises a ceramic base, a metal wall, a chip carrier and an outer lead electrode, and is characterized in that the ceramic base is of a stepped structure and is made of an Al2O3 multilayer ceramic material; the metal wall on the first step is fixedly connected with the ceramic base through a sintering process, and nine inner electrode bonding pads are arranged on the second step; the chip carrier on the third step is fixedly connected with the ceramic base through a sintering process; and an outer lead electrode is welded and fixed at the bottom of the ceramic base. The heat conductivity of the ceramic material is obviously higher than that of the plastic packaging material, heat generated by the chip can be efficiently conducted to the external environment, and a lighter and smaller packaging appearance is achieved through internal structure optimization. And secondly, the loss of the high-frequency signal in the ceramic material is lower, so that the loss of a finished product device can be reduced.