416 results about "Wafer-level packaging" patented technology

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

The invention provides a preparation method of an inertial sensor and the sensor. The preparation method comprises the following steps: sequentially forming a first cavity and a first oxide layer on a first silicon wafer; bonding the first silicon wafer and a second silicon wafer, wherein the second silicon wafer is a low-resistance silicon wafer; forming an inertia sensitive structure in the second silicon wafer; correspondingly forming a second cavity on a third silicon wafer, wherein the third silicon wafer is a low-resistance silicon wafer; bonding the third silicon wafer and the second silicon wafer; an isolation groove penetrating through the third silicon wafer is formed through etching, a conductive silicon column and an electric signal isolation ring are formed, and the conductive silicon column is connected with the inertia sensitive structure; and forming a sealing insulating layer on the surface of the third silicon wafer, and forming a signal lead-out pin in the sealing insulating layer. According to the scheme, thermal stress caused by thermal expansion coefficient mismatch among the three layers of wafers is reduced through an all-silicon wafer level packaging process, and the full-temperature characteristic of the device is greatly enhanced; and the preparation process flow is optimized, the process control difficulty is reduced, and the preparation cost is reduced.

A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; a carrier substrate on the MLI structure; a first through substrate via (TSV) structure extending though the carrier substrate and configured to provide an electrical connection between the MLI structure and a separate die; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; and a microfluidic channel cap structure attached to the buried oxide layer.

The invention relates to the technical field of photoresist coating of wafer level packaging, in particular to a fine atomization resonant cavity structure and a gluing method.The fine atomization resonant cavity structure comprises a resonant cavity, a spherical resonant cavity is arranged in the resonant cavity, and the diameter of the spherical resonant cavity is integer multiples of the half-wavelength of ultrasonic excitation; the top end of the resonant cavity is provided with an opening for ultrasonic excitation input, and the bottom end of the resonant cavity is provided with an acoustic resonance resonant cavity; and the liquid supply needle is inserted into the acoustic resonance cavity from the resonance cavity. According to the structure and the method, the uniformity of photoresist spraying and the quality of a film layer can be improved, accurate sound field regulation and control are utilized, a micro-channel is not needed to provide fluid flow, and the potential problem of spray hole blockage is avoided; the acoustic wave is focused in the resonant cavity, and liquid drops can be broken in an extremely short time, so that the atomization particle size is small, the concentration ratio is high, and the film thickness of the photoresist is uniform and controllable; and the film layer uniformity is high, the film layer defects are few, the conformal coating of the complex three-dimensional microstructure can be realized without being limited by the surface morphology of the wafer.

A wafer-level package module includes a first substrate having a first bulk acoustic wave (BAW) device mounted thereon with a first aluminum nitride piezoelectric layer. The wafer-level package module further includes a second substrate having a second BAW device mounted thereon with a second aluminum nitride piezoelectric layer. The first BAW device has a electromechanical coupling coefficient (kt2) different from the second BAW device.

The invention provides a wafer-level and board-level combined packaging method and packaging structure, and the method comprises the steps: A1, enabling the front surface of a whole wafer to face upwards, and forming a conductive connection layer on the front surface of the wafer; a2, the back face of the wafer is temporarily attached to a supporting carrier plate; a3, performing plastic package on the front surface and the side surface of the wafer to form a first protection layer; step A4, removing the supporting carrier plate; a5, grinding the first protection layer on the front surface of the wafer to expose the top surface of the conductive connection layer; and A6, cutting the wafer to form a single packaging structure. According to the invention, a structure and a process of combining wafer-level packaging and board-level packaging are adopted, a packaging process which is easy to implement and can be standardized is formed, the problem that the side surface of the wafer-level packaging is exposed and the alignment precision of the board-level packaging is low is solved, the packaging efficiency is improved, and the product cost is reduced.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

The invention relates to the technical field of failure evaluation, and discloses a TSV-RDL wafer level package electro-failure reliability evaluation system, which comprises an upper computer, a precision power supply, an editable controller, a direct current voltmeter and a relay array, the upper computer is connected with the precise power supply, the programmable controller and the direct-current voltmeter through a communication bus; the programmable controller is connected with the direct-current voltmeter and the relay array, the programmable controller responds to a control instruction and controls the on-off state of a current path at the connecting end of the TSV sample through the relay array, and the TSV sample receives current and voltage and responds to the current and the voltage in real time; the direct current voltmeter is used for measuring the voltage change of the TSV sample; the programmable controller judges whether a set condition is met or not based on data fed back by the direct-current voltmeter in real time, and then the on-off state of the relay is controlled. According to the invention, the current-voltage-resistance characteristics of the TSV sample can be comprehensively recorded, and the automation level of the test is improved, so that the requirements of the TSV electromigration failure test are met.

The invention discloses a novel wafer-level packaging structure and a manufacturing method, and belongs to the technical field of semiconductors, and the method comprises the steps: 1, preparing a wafer to be processed, and enabling the wafer to comprise a welding pad; step 2, coating a dielectric material above the wafer, forming a dielectric layer through exposure and development, curing the dielectric layer, and exposing the dielectric layer out of the welding pad; 3, forming a metal seed layer above the dielectric layer and the welding pad for realizing electrical interconnection; and 4, coating a photoresist I on the metal seed layer, exposing and developing the photoresist I, electroplating on the exposed metal seed layer after developing, and removing the photoresist I to form a metal layer I. The thickened copper layer II in the metal layer I serves as a sputtering seed layer of the metal layer II, and the sputtering seed layer below the metal layer I is utilized, so that an additional sputtering seed layer does not need to be sputtered on the metal layer I, the cost is saved, and the technological process is simplified.

The invention relates to the technical field of semiconductor packaging detection, in particular to a semiconductor packaging micro welding spot three-dimensional shape intelligent detection system which comprises a sample placing frame, an imaging module, an image processing unit, a detection module and a result display module. The image processing unit constructs a unified curvature field expression by fusing three-dimensional information of three different imaging principles of a spherical mirror model, a light-sectioning microscopic three-dimensional reconstruction algorithm and stripe structured light, and adopts adaptive mesh refinement to process a curvature change violent region; the detection module identifies welding spot defects such as pseudo soldering, bridging and poor connection based on differential invariants and singularity analysis, the system realizes high-precision detection of various semiconductor packaging forms such as BGA, QFN packaging and wafer-level packaging, the measurement precision is improved by 35%-40%, the processing efficiency is improved by about 50%, the defect omission ratio is reduced from 15% to below 3%, and the detection accuracy is greatly improved. And a brand new solution is provided for semiconductor packaging quality control.

Provided are a wafer-level packaged resonator and a preparation method therefor, as well as an electronic device, relating to the technical field of resonators. The electronic device includes a wafer-level packaged resonator. The wafer-level packaged resonator includes a wafer top cover, a wafer base, and a blank. The blank includes: a resonant part; an assembling part sleeved on the periphery of the resonant part, where the blank is bonded and packaged between the wafer top cover and the wafer base through the assembling part; and at least two connecting parts, connected between the resonant part and the assembling part, respectively, where each connecting part includes at least one continuous bend.

The invention discloses an image sensing chip board-level packaging structure and a manufacturing method thereof.The packaging structure comprises a cofferdam type chip unit, the cofferdam type chip unit comprises a transparent substrate, a cofferdam structure and an image sensing chip, the front face of the image sensing chip is provided with a photosensitive area and a bonding pad, the transparent substrate covers the photosensitive area, and the cofferdam structure covers the bonding pad; a cofferdam structure is arranged between the transparent substrate and the image sensing chip, and the cofferdam structure surrounds the photosensitive area to form a closed area; the plastic package body wraps the side surface and the back surface of the cofferdam type chip unit; the first rewiring layer is arranged on one side, close to the front surface of the image sensing chip, of the plastic package body and is electrically connected with a bonding pad of the image sensing chip; the second rewiring layer penetrates through the plastic package body and is electrically connected with the first rewiring layer; and the external interconnection structure is electrically connected with the second rewiring layer. The packaging structure has excellent electrical quality and reliability, the packaging size is larger than the size of a bare chip, and the problem that the heat dissipation capacity is limited due to miniaturization of wafer-level packaging can be solved.

Encapsulated MEMS devices and methods of fabrication with wafer-level fabrication processes are described which address small molecule diffusion into hermetically sealed cavities. In some configurations a small molecule barrier layer, or hydrogen barrier layer, is formed during a back-end-of-the-line (BEOL) processing over a cap wafer including a planarized surface formed during a via reveal griding operation. In some configurations a small molecule barrier layer is not formed over the planarized surface during BEOL processing in order to allow an escape path for small molecules. In some configurations a small molecule barrier layer, or hydrogen barrier layer, is formed on a bottom side of a cap wafer prior to bonding the cap wafer to a device wafer during wafer-level fabrication.

The invention discloses a wafer-level packaging method and a chip structure of a slotted filling support material, comprising the following steps: providing a wafer-level packaging structure which comprises a first wafer, a second wafer and a connecting part for bonding the first wafer and the second wafer, a cutting channel cavity communicated with the outside is formed between at least part of adjacent connecting parts; cutting the wafer-level packaging structure to form a through groove along the thickness direction of the wafer-level packaging structure, wherein the through groove is communicated with the cutting channel cavity along the thickness direction; and the cutting channel cavity is filled with a supporting material through the through groove. The cutting channel cavity is good in supporting effect, and the wafer-level packaging structure is not prone to being broken and damaged.

The invention discloses a semiconductor wafer-level packaging method and a packaging structure, and in the semiconductor wafer-level packaging method, through the arrangement of an annular projection and the cooperation of a gluing mode, the air tightness and reliability of the packaging structure are improved while the packaging bonding strength is maintained, and meanwhile, bonding glue can be prevented from influencing a functional area.

A method for debonding a wafer from a bonded wafer stack is disclosed. Initially, a light-absorbing layer is placed on a carrier. A wafer is then attached to the light-absorbing layer of the carrier via an adhesive layer to form a bonded wafer stack. After processing the wafer has been processed, a light pulse from a flashlamp is applied to a non-wafer side of the carrier to heat the light-absorbing layer and the adhesive layer in order to loosen the wafer from the bonded wafer stack. Finally, the wafer is removed from the bonded wafer stack.

The invention relates to the technical field of microelectronics and MEMS manufacturing, in particular to a bulk acoustic resonator with a double-layer piezoelectric film and a preparation method thereof, according to the method, a heterogeneous integrated key structure is formed by a first piezoelectric layer and a second piezoelectric layer which are deposited on the two sides of a middle electrode layer respectively, the physical and process limits of a single-layer piezoelectric film FBAR are broken through, the high-frequency band is improved, and the high-frequency band is improved. A wider bandwidth is realized; middle electrode layer tuning is combined with back silicon through hole leading-out, front routing inductance is eliminated, and the low-loss characteristic of the filter under high frequency is guaranteed; the self-heating problem under large bandwidth and high power is effectively inhibited through heat dissipation integrated packaging, and the power bearing capacity is improved; the method is compatible with a CMOS (complementary metal oxide semiconductor) process and can be directly embedded into an existing production line, so that the volume is further reduced while the bulk acoustic wave resonator with the double-layer piezoelectric film can effectively cover a frequency band of more than 3GHz, and the problem that a single-layer piezoelectric film and a matched process thereof cannot meet the requirements of a next-generation radio frequency front end on high frequency, large bandwidth, high power and wafer-level packaging is solved.

The invention provides an integrated multichannel pulse modulation type power switch control technology, and a power switch control device with high integration level and high performance is created through a heterogeneous integration technology, a multichannel PWM (Pulse Width Modulation) architecture and an intelligent protection mechanism. Wafer level packaging (WLP) and flip-chip bonding technologies are adopted, a PWM control chip and a GaN / SiC field effect transistor of a CMOS technology and a driver and a protection circuit of a Bipolar technology are integrated in single surface-mounted packaging, the number of external elements is greatly reduced, the space utilization rate of a circuit board is improved, and the overall size is reduced. By optimizing a multi-layer PCB structure and separating a high-frequency signal path from a power supply network, parasitic inductance is effectively suppressed, and the problem of packaging stress caused by difference of thermal expansion coefficients among heterogeneous processes is relieved.

The application discloses a kind of through superimposed photoresist layer the method for manufacturing wafer level packaging product, and the application belongs to wafer level packaging field, including step one: preparation glass wafer, release layer and sputtering layer are coated on the glass wafer top;Step two: the first heavy wiring layer is formed on the sputtering layer top;Step three: metal seed layer is set on the first heavy wiring layer top;Step four: photoresist is coated on the first heavy wiring layer top to form photoresist one;Step five: the photoresist one is carried out alignment exposure operation to photoresist one by mask one;Step six: photoresist one is developed to form opening structure one.The application utilizes the way of high tackiness wet film photoresist to manufacture silicon through hole bump, can solve the technical problem of silicon through hole bump preparation in advanced packaging field, effectively improve the product quality and production yield of chip, suitable for advanced packaging silicon through hole bump whole process preparation link.

A semiconductor device and a method of manufacturing the semiconductor device are provided. The method may include forming semiconductor sub-packages by performing a fan-out wafer level packaging process; singulating the semiconductor sub-packages from at least one wafer; and reconstituting the semiconductor sub-packages into a fan-out panel level package (FOPLP).

The invention provides a wafer-level packaging structure of a heterogeneous chip and a preparation method of the wafer-level packaging structure. According to the preparation method, the first chip is inversely stacked on the second chip, and the electrodes of the first chip and the second chip are led out through the metal interconnection layer. The occupation rate of the area of the mainboard is reduced, the integration density is improved, a glass carrier plate does not need to be prepared, the preparation cost is reduced, the process efficiency is improved, and the process effects of 2.5 D packaging and 3D packaging are achieved on the basis of 2D packaging. Besides, under the condition that the first chip is inverted, an opening of the cavity in the first chip is covered by the bonding area in the metal interconnection layer, and sealing is achieved through the plastic packaging adhesive layer. Therefore, an expensive dry film does not need to be used for covering the opening of the cavity in the process of preparing the first chip, the preparation cost is further reduced, and the process efficiency is improved.

The application discloses a surface acoustic wave filter wafer level packaging structure and a manufacturing method thereof. The surface acoustic wave filter wafer level packaging structure comprises a wafer, a first surface of the wafer is provided with a surface acoustic wave filter, wherein the surface acoustic wave filter comprises an interdigital transducer and at least two electrodes, and a part of the electrodes protrudes from the edge of the wafer; a cofferdam layer is located between the interdigital transducer and the electrodes and surrounds the interdigital transducer, and the thickness of the cofferdam layer is greater than the thickness of the interdigital transducer; a shielding layer is located on the side of the cofferdam layer away from the wafer; a packaging layer is located on the side of the shielding layer away from the wafer, the packaging layer covers the first surface of the wafer, the surface of the electrode away from the wafer, the cofferdam layer and the shielding layer, and the packaging layer is provided with a groove adjacent to the surface of the wafer, and the side wall of the groove exposes the side surface of the electrode. The packaging structure and the manufacturing method thereof provided in the embodiment can improve the sealing performance of the wafer and the reliability of the surface acoustic wave filter wafer level packaging structure.

A fan-out wafer-level packaging (FOWLP) unit including a substrate, at least one first die, a first dielectric layer, a plurality of first conductive circuits, a second dielectric layer, a plurality of second conductive circuits, and at least one second die is provided. A range perpendicular to a second surface of the first die is defined as a chip area. The second dielectric layer is provided with a plurality of second slots allowing the second conductive circuit to expose and form bonding pads. The bonding pads located around the chip area are first bonding pads. The second die is disposed over the second dielectric layer by flip chip and electrically connected to the first die which is electrically connected with the outside by the first bonding pads. Thereby problems of conventional FOWLP generated during manufacturing of the conductive circuits including higher manufacturing cost and less environmental benefit can be solved.

The invention provides a wafer-level packaging method and packaging structure of an OLED chip, and relates to the technical field of semiconductor packaging. The wafer-level packaging method of the OLED chip comprises the following steps: providing a light-transmitting cover plate and a wafer; wherein the wafer is provided with a plurality of light-emitting areas, the peripheries of the light-emitting areas are provided with electrodes, and preset intervals are arranged between the electrodes and the light-emitting areas. A plurality of grooves are formed in one side of the light-transmitting cover plate, and the depth of the grooves is smaller than the thickness of the light-transmitting cover plate; and mounting parts are formed among the plurality of grooves. Bonding the wafer and the light-transmitting cover plate; wherein the light-emitting areas and the surface-mounting parts are in one-to-one correspondence and are in press fit. Cutting the light-transmitting cover plate along the edge of the mounting part, and removing the groove structure to form a wafer with a light-transmitting patch; and the projection of the light-transmitting patch on the wafer does not coincide with the electrode. And slitting the wafer to form a single chip. The method is beneficial for improving the packaging efficiency and the packaging yield.

An integrated circuit (IC) package, the integrated circuit (IC) package including: an integrated circuit (IC) die including an input / output (I / O) pad; and a vertical thin film inductor (TFI) extending substantially vertically from the I / O pad to the solder bump.

The embodiment of the present invention provides a wafer-level packaging structure of a MEMS microphone, comprising: a first silicon substrate, a second silicon substrate and an ASIC chip; the first silicon substrate is sealed and connected to the second silicon substrate; the ASIC chip is arranged on a side of the second silicon substrate away from the first silicon substrate; the second silicon substrate comprises a first region and a second region surrounding the first region; the first region comprises a plurality of blind holes; the first silicon substrate comprises a through-hole region, the through-hole region is arranged opposite to the first region; a back electrode and a diaphragm are arranged on a side of the first silicon substrate adjacent to the second silicon substrate, the back electrode and the diaphragm at least cover the through-hole region, and the back electrode is arranged on a side of the diaphragm adjacent to the second silicon substrate; the back electrode is electrically connected to the ASIC chip via a first lead arranged in the second region, and the diaphragm is electrically connected to the ASIC chip via a second lead arranged in the second region. The wafer-level packaging structure of a MEMS microphone provided by the embodiment of the present invention can reduce the packaging area of ​​the MEMS microphone, and meet the market demand for miniaturized packaging of MEMS microphones.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

The invention provides a wafer level packaged backlight image sensor chip, and relates to the technical field of chips, the wafer level packaged backlight image sensor chip comprises a wafer, the wafer comprises a plurality of chip bodies, a cutting channel is arranged between the adjacent chip bodies, the chip bodies are accommodated in the support frame, the support frame is bonded with a non-light-sensitive surface, and the cutting channel is arranged between the adjacent chip bodies. The plurality of light-transmitting cover plates are adhered to the supporting frame and directly face the light-sensitive surface, the supporting frame is provided with mounting windows of which the number is in one-to-one correspondence with that of the chip bodies, the light-transmitting cover plates are in one-to-one correspondence with the mounting windows, and the light-transmitting cover plates are used for sealing and covering the corresponding mounting windows; the protection carrier plate is installed on the outer surface of the supporting frame in an attached mode, the light-transmitting cover plate is located between the protection carrier plate and the chip body, the wafer-level packaging method is applied to the wafer-level packaging technology, and the problems that an existing wafer-level packaging method of the backlight image sensor chip is complex in process and low in process efficiency are solved.

The utility model discloses a fan-out type wafer level packaging unit. The fan-out type wafer level packaging unit comprises a carrier plate, at least one bare chip, a first dielectric layer, at least one conductive column, a second dielectric layer, a plurality of first conductive connection lines, a first outer protective layer, a third dielectric layer, a plurality of second conductive connection lines and a second outer protective layer, wherein the die can be electrically connected to the outside by at least one first bonding pad around a chip region on the second side of the die; wherein the die can be electrically connected to the outside through a second bonding pad in at least one opening of the second outer protective layer; wherein each first conductive connection line and each second conductive connection line are manufactured by a technology of filling metal paste into the grooves and then grinding and forming the conductive connection lines, so that the problems that the manufacturing cost is high and environmental protection is not facilitated when each conductive connection line is manufactured by the existing fan-out packaging technology are solved.

The invention provides a wafer-level packaging structure and a preparation method thereof. The wafer-level packaging structure comprises an insulating layer, a chip arranged on the insulating layer, a plastic packaging layer wrapping the chip, and a rewiring layer, wherein the side surface of the plastic packaging layer and the interior of the insulating layer are provided with communicated gaps, and the rewiring layer extends into the gaps and is connected and conducted with the chip; the rewiring layer comprises a side surface connecting part formed in the gap and an L connecting part connected between the side surface connecting part and the chip; the chips are connected and conducted with an external circuit through the L connecting parts, and every two adjacent chips are connected and conducted through the side face connecting parts at the corresponding positions. According to the invention, multi-surface signal conduction of the chip can be realized, the packaging flexibility is improved, and the chip density is increased.