117 results about "Wafer-level packaging" patented technology

The invention discloses a novel wafer-level packaging structure and a manufacturing method, and belongs to the technical field of semiconductors, and the method comprises the steps: 1, preparing a wafer to be processed, and enabling the wafer to comprise a welding pad; step 2, coating a dielectric material above the wafer, forming a dielectric layer through exposure and development, curing the dielectric layer, and exposing the dielectric layer out of the welding pad; 3, forming a metal seed layer above the dielectric layer and the welding pad for realizing electrical interconnection; and 4, coating a photoresist I on the metal seed layer, exposing and developing the photoresist I, electroplating on the exposed metal seed layer after developing, and removing the photoresist I to form a metal layer I. The thickened copper layer II in the metal layer I serves as a sputtering seed layer of the metal layer II, and the sputtering seed layer below the metal layer I is utilized, so that an additional sputtering seed layer does not need to be sputtered on the metal layer I, the cost is saved, and the technological process is simplified.

The invention discloses an image sensing chip board-level packaging structure and a manufacturing method thereof.The packaging structure comprises a cofferdam type chip unit, the cofferdam type chip unit comprises a transparent substrate, a cofferdam structure and an image sensing chip, the front face of the image sensing chip is provided with a photosensitive area and a bonding pad, the transparent substrate covers the photosensitive area, and the cofferdam structure covers the bonding pad; a cofferdam structure is arranged between the transparent substrate and the image sensing chip, and the cofferdam structure surrounds the photosensitive area to form a closed area; the plastic package body wraps the side surface and the back surface of the cofferdam type chip unit; the first rewiring layer is arranged on one side, close to the front surface of the image sensing chip, of the plastic package body and is electrically connected with a bonding pad of the image sensing chip; the second rewiring layer penetrates through the plastic package body and is electrically connected with the first rewiring layer; and the external interconnection structure is electrically connected with the second rewiring layer. The packaging structure has excellent electrical quality and reliability, the packaging size is larger than the size of a bare chip, and the problem that the heat dissipation capacity is limited due to miniaturization of wafer-level packaging can be solved.

The invention relates to the technical field of microelectronics and MEMS manufacturing, in particular to a bulk acoustic resonator with a double-layer piezoelectric film and a preparation method thereof, according to the method, a heterogeneous integrated key structure is formed by a first piezoelectric layer and a second piezoelectric layer which are deposited on the two sides of a middle electrode layer respectively, the physical and process limits of a single-layer piezoelectric film FBAR are broken through, the high-frequency band is improved, and the high-frequency band is improved. A wider bandwidth is realized; middle electrode layer tuning is combined with back silicon through hole leading-out, front routing inductance is eliminated, and the low-loss characteristic of the filter under high frequency is guaranteed; the self-heating problem under large bandwidth and high power is effectively inhibited through heat dissipation integrated packaging, and the power bearing capacity is improved; the method is compatible with a CMOS (complementary metal oxide semiconductor) process and can be directly embedded into an existing production line, so that the volume is further reduced while the bulk acoustic wave resonator with the double-layer piezoelectric film can effectively cover a frequency band of more than 3GHz, and the problem that a single-layer piezoelectric film and a matched process thereof cannot meet the requirements of a next-generation radio frequency front end on high frequency, large bandwidth, high power and wafer-level packaging is solved.

The invention provides an integrated multichannel pulse modulation type power switch control technology, and a power switch control device with high integration level and high performance is created through a heterogeneous integration technology, a multichannel PWM (Pulse Width Modulation) architecture and an intelligent protection mechanism. Wafer level packaging (WLP) and flip-chip bonding technologies are adopted, a PWM control chip and a GaN / SiC field effect transistor of a CMOS technology and a driver and a protection circuit of a Bipolar technology are integrated in single surface-mounted packaging, the number of external elements is greatly reduced, the space utilization rate of a circuit board is improved, and the overall size is reduced. By optimizing a multi-layer PCB structure and separating a high-frequency signal path from a power supply network, parasitic inductance is effectively suppressed, and the problem of packaging stress caused by difference of thermal expansion coefficients among heterogeneous processes is relieved.

The application discloses a kind of through superimposed photoresist layer the method for manufacturing wafer level packaging product, and the application belongs to wafer level packaging field, including step one: preparation glass wafer, release layer and sputtering layer are coated on the glass wafer top;Step two: the first heavy wiring layer is formed on the sputtering layer top;Step three: metal seed layer is set on the first heavy wiring layer top;Step four: photoresist is coated on the first heavy wiring layer top to form photoresist one;Step five: the photoresist one is carried out alignment exposure operation to photoresist one by mask one;Step six: photoresist one is developed to form opening structure one.The application utilizes the way of high tackiness wet film photoresist to manufacture silicon through hole bump, can solve the technical problem of silicon through hole bump preparation in advanced packaging field, effectively improve the product quality and production yield of chip, suitable for advanced packaging silicon through hole bump whole process preparation link.

The invention discloses a Micro-OLED (Organic Light Emitting Diode) chip packaging structure, a Micro-OLED chip packaging method and a Micro-OLED display device. The packaging structure comprises a semiconductor wafer which is provided with a conductive through hole penetrating to a metal bonding pad on the front surface of the semiconductor wafer; the plurality of metal bumps are formed on the back surface of the semiconductor wafer and are electrically connected with the metal bonding pads on the front surface through the conductive through holes and the metal rewiring layer on the back surface; the Micro-OLED light emitting layer is formed on the front surface of the semiconductor wafer; and the transparent cover plate is bonded with the front surface of the semiconductor wafer through a supporting wall. According to the invention, the wafer-level chip size packaging process sequence of the Micro-OLED is optimized as follows: the through holes and the salient points are firstly manufactured on the back surface, and then the OLED is manufactured on the front surface. According to the method, the metal bonding pads are allowed to be led out from the two sides, three sides or four sides of the chip, and particularly, the large-current power supply / ground bonding pads are arranged at the four corners of the chip, so that the internal current distribution of the chip is remarkably optimized, the IR voltage drop is reduced, and thinner and smaller Micro-OLED wafer-level packaging with better electrical performance is realized.

A fan-out wafer level packaging (FOWLP) unit which includes a substrate, a first dielectric layer, at least one antenna, at least one die, a second dielectric layer, at least one conductive pillar, a plurality of first conductive circuits, a third dielectric layer, a plurality of second conductive circuits, and an outer protective layer is provided. The first conductive circuits and the second conductive circuits are produced by filling a metal paste into slots and grinding the metal paste. The die is electrically connected with the antenna. The die is electrically connected to the outside through bonding pads around a chip area on a second surface of the die. Thereby the FOWLP unit is formed and problems of the FOWLP module or technology available now generated during manufacturing of the respective conductive circuits including higher manufacturing cost and less environmental benefit can be solved.

The application provides a via hole forming method, a wafer level packaging structure, a method and a communication device. The via hole forming method comprises the following steps: providing a cover plate, wherein the cover plate comprises a first surface and a second surface arranged opposite to the first surface; forming a blind hole on the first surface of the cover plate; forming a protective layer in the blind hole; performing a thinning treatment on the second surface of the cover plate to expose the protective layer at the bottom of the blind hole; and removing the protective layer to convert the blind hole into a via hole. The technical solution provided by the application improves the yield of forming the via hole in the cover plate.

A wafer-level package is described. In an embodiment, the wafer-level package (100) comprises: a substrate (102) having electrically conductive interconnects embedded within the substrate (102), the substrate (102) having a top substrate surface and a bottom substrate surface opposite to the top substrate surface, the bottom substrate surface being adapted to be provided on a printed circuit board (PCB); a first integrated circuit die (104) having an active surface wherein the first integrated circuit die is provided adjacent to an edge portion of a perimeter of the substrate (102); a mold (108) adapted to hold the first integrated circuit die (104) and the substrate (102) so that the active surface of the first integrated circuit die (104) is in a same plane as the top substrate surface; a first redistribution layer (110) having electrically conductive interconnects embedded within the first redistribution layer (110), the first redistribution layer (110) being formed on the active surface of the first integrated circuit die (104) and the top substrate surface; and a second integrated circuit die (112) provided on the first redistribution layer (110), the second integrated circuit die (112) being electrically connected to the first integrated circuit die (104) via the first redistribution layer (110). Embodiments in relation to a method (200) for forming the wafer-level package are also described.

The invention discloses a fan-out type wafer level packaging unit which comprises a carrier plate, at least one bare chip, a first dielectric layer, at least one conductive column, a second dielectric layer, a plurality of first conductive connection lines, a first outer protection layer, a third dielectric layer, a plurality of second conductive connection lines and a second outer protection layer. Wherein the die can be electrically connected to the outside by at least one first bonding pad around a chip region on the second side of the die; wherein the die can be electrically connected to the outside through a second bonding pad in at least one opening of the second outer protective layer; wherein each first conductive connection line and each second conductive connection line are manufactured by a technology of filling metal paste into the grooves and then grinding and forming the conductive connection lines, so that the problems that the manufacturing cost is high and environmental protection is not facilitated when each conductive connection line is manufactured by the existing fan-out packaging technology are solved.

An advanced 2.5D panel-level packaging structure and a forming method thereof, the forming method comprising: forming a plurality of chip structures; forming a panel-level packaging body, the panel-level packaging body comprising a plurality of packaging units; bonding and connecting the plurality of chip structures and the plurality of packaging units correspondingly; and performing cutting processing on the panel-level packaging body to form a plurality of packaging units. By fully utilizing the advantage of the panel-level packaging body in size specification, the fixed limitation of wafer-level packaging in area utilization and cost control is broken. By performing cutting processing on the panel-level packaging body to form a plurality of packaging units, a plurality of packaging structures can be processed in parallel on the same panel, which significantly improves the production efficiency and reduces the unit manufacturing cost. In addition, the unified preparation of the panel-level packaging body provides a standardized platform for the subsequent integration of diversified chips, which is conducive to realizing the high-density heterogeneous integration of different functional chips and meeting the development needs of advanced packaging technology in system-level integration and multi-functional fusion.

A fan-out wafer-level packaging (FOWLP) unit is provided. The FOWLP unit includes a substrate, a first dielectric layer, a plurality of first conductive circuits, at least one first die, a second dielectric layer, at least one conductive pillar, a plurality of second conductive circuits, a third dielectric layer, a plurality of third conductive circuits, and at least one second die. The first die and the second die are electrically connected with the outside through first die pads around a chip area on a second surface of the first die. The first conductive circuits, the second conductive circuits, and the third conductive circuits are produced by filling of metal pastes into slots and grinding of the metal paste. Thereby problems of FOWLP technology available now generated during manufacturing of the respective conductive circuits including higher manufacturing cost and environmental unfriendly can be solved.

This invention relates to the field of semiconductor technology, providing a wafer-level packaging method and structure. The method includes: providing a MEMS suspended structure and a cover plate structure; etching trenches and electrode patterns on the bonding surface of the cover plate structure; directly bonding the MEMS suspended structure and the cover plate structure; etching the front side of the cover plate structure to achieve trench penetration; bonding the cover plate structure to a glass anode to form a glass sealing layer; melting the glass of the glass sealing layer at high temperature and reflowing it into the trenches to form an electrode isolation layer that isolates the through-penetrating electrodes; and thinning and polishing the glass sealing layer. This invention utilizes direct bonding technology combined with a glass reflow scheme to achieve wafer-level packaging of chips. The glass, as an isolation and sealing material, exists only in extremely fine trenches, solving the problem of poor temperature performance and low temperature linearity of devices caused by thermal stress mismatch when other materials are introduced.

A surface acoustic wave device including a piezoelectric layer, an interdigital transducer electrode over the piezoelectric layer, and a polymeric roof layer arranged over the piezoelectric layer and interdigital transducer electrode. The polymeric roof layer is spaced apart from the piezoelectric layer to define a cavity to accommodate the interdigital transducer electrode. The polymeric roof layer is supported along a span of the polymeric roof layer by at least one pillar. The thermal conductivity of the pillar is greater than the thermal conductivity of the polymeric roof layer. Related wafer-level packages, radio frequency modules and wireless communication devices are also provided.

A wafer level package (1) comprises: a lower substrate (22); an upper substrate (23) facing the lower substrate (22); a plurality of elements (20) arranged in an array, the plurality of elements (20) being formed on at least one of the lower substrate (22) and the upper substrate (23), or being mounted between the lower substrate (22) and the upper substrate (23); a first eutectic material f formed on the surface of the lower substrate (22) facing the upper substrate (23); a second eutectic material f' formed on the surface of the upper substrate (23) facing the lower substrate (22); a plurality of frame bodies (24) surrounding the plurality of elements (20) respectively; and connection parts (26) that connect parts of the frame bodies (24) respectively surrounding adjacent elements (20) from among the plurality of elements (20). The frame bodies (24) and the connection parts (26) are formed by eutectically bonding the first eutectic material f and the second eutectic material f'. The eutectic material ratio between the first eutectic material f and the second eutectic material f' is different between at least the frame bodies (24) and a part of the connection parts (26).

The invention discloses a fan-out type wafer level packaging unit which comprises a carrier plate, a first dielectric layer, at least one antenna, at least one bare chip, a second dielectric layer, at least one conductive column, a plurality of first conductive connection lines, a third dielectric layer, a plurality of second conductive connection lines and an outer protection layer. Wherein each first conductive connection line and each second conductive connection line are formed by a technology of filling metal paste into the groove and then grinding and forming the conductive connection lines; wherein each die is electrically connected with each antenna; wherein the bare crystal can be electrically connected with the outside through each welding pad around the chip area on the second surface of the bare crystal, so that the fan-out type wafer level packaging unit is formed, and the problems that high manufacturing cost is easily generated and environmental protection is not facilitated when each conducting circuit is manufactured by the existing fan-out type packaging technology are solved.

This invention relates to the field of temperature control, specifically to a method for optimizing simulation parameters of photonic debonding for wafer-level packaging. The method includes: obtaining the value range of simulation parameters for photonic debonding; dividing the data into a grid disk based on the value range, where each node of the grid disk corresponds to a parameter set; constructing an objective function for an ant colony algorithm; for each iteration of the ant colony algorithm, calculating the dynamic pheromone evaporation coefficient of the node where each ant is located to control the pheromone decay rate in the next iteration; filtering all parameter sets during the iteration process to obtain a globally optimal parameter set; and completing parameter optimization. The globally optimal parameter set is used for temperature control of photonic debonding. This invention can obtain optimal simulation parameters through an ant colony algorithm to improve the accuracy of controlling the temperature of photonic debonding.

The invention belongs to the technical field of reflow soldering, and particularly relates to a wafer-level packaging reflow soldering anti-warping self-adaptive reinforcing device and a wafer-level packaging reflow soldering anti-warping self-adaptive reinforcing method. Comprising a supporting platform used for bearing a wafer-level substrate assembly to be subjected to reflow soldering; the spring floating supporting mechanisms are arranged in the concave cavity of the supporting platform in a multi-point manner, are used for supporting the wafer-level substrate assembly to be subjected to reflow soldering, and have a certain floating stroke; each spring floating supporting mechanism is composed of elastic elements arranged in a multi-point mode. And the grating type pressing mechanism is positioned above the supporting platform, consists of a plurality of orthogonal rigid pressing rods, and forms a latticed pressing surface covering the effective area of the substrate. The method aims at effectively restraining buckling deformation of the wafer-level substrate caused by thermal stress in the reflow soldering process, and the coplanarity and stability of a soldering interface are ensured.

The application discloses a wafer level packaging method, comprising the following steps: a substrate marking step: etching at least one set of foolproof marks and position marks on one surface of a substrate; a wafer marking step: forming alignment marks same as the position marks on each wafer, the alignment marks being aligned with the position marks, and wafer flat edges or notches being aligned with the foolproof marks; a packaging processing step: forming protrusions on an active surface of the wafer, the protrusions being matched with the foolproof marks and the position marks; after encapsulation, transferring the marks at the protrusions to the package to form plastic packaging marks, and wiring; and then, according to the plastic packaging marks, dividing and cutting the wafer into single finished products. The wafer position is accurately positioned through the position marks, the foolproof marks, the multi-ball combined feature shape and the plastic packaging marks on the substrate, cutting injury is prevented, a plurality of wafers can be operated under the same process, small-size wafers can also be compatible on the equipment, the processing time is shortened, and the production cost is reduced.

The invention discloses an MEMS (Micro Electro Mechanical System) thermal acceleration sensor for realizing wafer-level packaging by utilizing a silicon structure in glass and a preparation method. The sensor adopts a three-layer stacked structure, and comprises a silicon sealing cover in glass, an acceleration sensor body and a sealing laminated wafer. Wherein a silicon conductive through column which is electrically insulated from the glass medium is arranged in the glass-in-silicon sealing cover, so that electric signal transmission in the vertical direction is realized; the acceleration sensor body comprises a heating and temperature measuring module manufactured on a supporting layer; the sealing bonding wafer and the sealing cover jointly form a sealed cavity to package the working fluid. The preparation method comprises the following steps: preparing a silicon-in-glass sealing cover through two times of deep silicon etching, anodic bonding and a glass backflow process, manufacturing a sensor functional structure on a silicon substrate and forming a back cavity, and finally completing wafer-level integrated packaging through a surface mounting process. The wafer-level batch preparation and packaging complete solution of the thermal acceleration sensor is realized, and the problems of high packaging cost and low efficiency of a non-standard process are solved.

This invention discloses a wafer-level packaged III-V flexible thin-film solar cell and its fabrication method, comprising an epitaxial layer, a front functional layer, a back functional layer, and a front electrode; at least one first extension and a second extension are formed at the edge of the back functional layer, and an insulating dielectric layer is disposed on the first extension; the grid lines of the front electrode are disposed between the epitaxial layer and the front functional layer, and the front electrode pads are disposed on the first extension, forming a first interconnect structure composed of the first extension, the insulating dielectric layer, and the front electrode pads; a back electrode pad is disposed on the second extension, forming a second interconnect structure composed of the second extension and the back electrode pads. This invention achieves wafer-level CIC packaging and testing of large-size single-cell cells, eliminating the traditional CIC module processing steps, reducing the use of cell interconnect solder ribbons, improving the utilization rate of the effective wafer area, and effectively reducing costs while improving the manufacturing quality and reliability of solar cells.

The application discloses a kind of negative photosensitive resin, photosensitive resin composition and its preparation method and application.The preparation method of the negative photosensitive resin of the application includes: (1) tetracarboxylic dianhydride is esterified with unsaturated double bond alcohol compound in organic solvent, and aromatic diester diacid containing unsaturated side chain is generated;(2) aromatic diamine solution is added to the above-mentioned pre-esterification product to carry out polycondensation reaction;(3) active reagent is added to the product of above-mentioned step (2), then add alcohol compound containing unsaturated double bond to carry out deep esterification.The negative photosensitive resin composition of the application can be cured at 200 DEG C, and the formed cured film has excellent heat resistance and adhesion, and also has excellent photoetching performance, can meet the use demand of wafer level packaging, and has good application prospect in the field of semiconductor manufacturing and packaging.

The invention discloses a silicon through hole sandwich cavity MEMS wafer level packaging method and a packaging body thereof, and belongs to the technical field of semiconductor chip packaging. Comprising an MEMS chip, an ASIC carrier plate chip, a cap wafer chip, an embedded interconnection mechanism, an upper silicon wafer bonding layer, a lower silicon wafer bonding layer, a silicon through hole, a step, a step bonding pad, a substrate, a plastic package shell, a plastic package shell cavity and an MEMS chip cavity. Through silicon via, wafer-level silicon-silicon bonding, lead bonding, SMT surface mounting technology, dry etching, chip inner cavity preparation and other technologies are comprehensively adopted, and low-cost and high-feasibility three-dimensional and miniaturized integration of the inertial MEMS chip is achieved. The problems that in an existing inertial MEMS chip three-dimensional integration technology, a wafer level scheme is complex in technology, high in initial cost, expensive in technology and equipment, poor in mechanical stress sensitivity, difficult in calibration test and low in maintainability are solved. The method is widely applied to the technical field of high-integration-density and high-power 3D packaging.

The invention relates to the technical field of optoelectronic device packaging, in particular to an OE mold combination packaging method which comprises the following steps: S1, obtaining a silicon substrate to be used and an activated PIC substrate to be used, and cleaning and activating the PIC substrate to obtain the PIC substrate to be used; s2, in the photosensitive area of the to-be-used PIC substrate, enabling the cleaning surface of the to-be-used silicon substrate to be in contact with the activation surface of the to-be-used PIC substrate, and then bonding to obtain a preliminary product; s3, an EIC module is arranged on the other side, opposite to the standby silicon substrate, of the standby PIC substrate; and S4, carrying out plastic packaging and thinning on the secondary product until the photosensitive area is exposed, and obtaining a sealed OE module. According to the invention, wafer-level packaging is carried out by using the integrated model, so that the problems of yield, efficiency and cost existing in traditional packaging can be solved, and reliable support can be provided for next-generation high-speed optical communication, silicon photon integration, intelligent sensing and other applications.

The present disclosure provides a wafer level packaged electric field sensor, an electric field detection method, a preparation method and a sensor, and is applied to the technical field of electric field sensors. The wafer level packaged electric field sensor comprises: a substrate for supporting a sensitive structure and a wafer level packaged cover plate; the sensitive structure is fixed above the substrate through an anchor point, the sensitive structure comprises an electric field sensing electrode unit and a displacement reference electrode unit, and is used for generating an induced electric signal by the electric field sensing electrode unit and a displacement reference electric signal by the displacement reference electrode unit in the case of applying an excitation to the sensitive structure, so as to compensate for a common mode error of the wafer level packaged electric field sensor according to the induced electric signal and the displacement reference electric signal, and improve the output sensitivity of the wafer level packaged electric field sensor; the wafer level packaged cover plate is arranged above the sensitive structure and is used for forming a sealed chamber together with the substrate, so that the sensitive structure in the sealed chamber is in a vacuum working environment, and the quality factor of the sensor is improved.

Procedure (200), comprising: Receiving (202) a processed wafer of an integrated circuit; Forming a metal plate (108, 308) on the machined wafer of an integrated circuit; Forming (206) a first dielectric layer (110, 310) on at least a partial area of ​​the wafer of an integrated circuit and at least a partial area of ​​the metal plate (108, 308); Forming (208) a rewiring layer structure at least on a partial area of ​​the metal plate (108, 308) and the first dielectric layer (110, 310); Forming (210) a second dielectric layer (114, 314) on the first dielectric layer (110, 310) and a sub-region of the rewiring layer structure; Forming (212) a pillar structure on the rewiring layer structure; Forming (216) a cast layer on the second dielectric layer (114, 314) and a part of the pillar structure (116, 316); Forming (214) a pier layer (120, 320) on the pier structure (116, 316) and a portion of the cast layer, wherein the pier layer (120, 320) extends from a first pier structure (116, 316) to a further pier structure (116, 316); and Forming (218) a metallization layer on the pillar layer (120, 320) and further comprising singling (220) the processed wafer of an integrated circuit, which includes cutting along a saw path (124, 324) that crosses the metallization layer, wherein the singling of the processed integrated circuit results in a wafer-level package component (100, 300) with terminal surface contacts exposed on at least two sides of the wafer-level package component (100, 300).

This invention belongs to the field of chip packaging, specifically relating to a high-reliability wafer-level packaged thin-film bulk acoustic wave device structure and its fabrication method. The structure includes a functional wafer and a capping wafer. The functional wafer has opposing first and second surfaces and a communicating first sidewall surface. The capping wafer has opposing third and fourth surfaces and a communicating second sidewall surface. The capping wafer has metallized vias penetrating the third and fourth surfaces and metal pillars completely filling the metallized vias. The edge of the third surface is bonded to the edge of the second surface via a sealing ring of a certain thickness. A communicating metal deposition layer is provided on the first surface, the first sidewall surface, and part of the second sidewall surface, covering the outer sidewall of the sealing ring. An electroplated thickening layer is provided on the surface of the metal deposition layer. This invention encapsulates the wafer-level packaged thin-film bulk acoustic wave device, blocking gas from entering and exiting from the side, thus improving the hermeticity of the wafer-level package.

The application discloses a kind of electrical detection methods in packaging process, comprising: forming circuit on the active surface of semiconductor wafer, there are multiple semiconductor chips on semiconductor wafer;Forming re-formation passivation layer one on effective chip, forming re-formation passivation layer two on ineffective chip;Re-formation passivation layer one forms opening one at the electrode of effective chip, and re-formation passivation layer two forms opening two at the electrode of ineffective chip;Forming rewiring metal layer one on re-formation passivation layer one, forming metal rewiring one and metal rewiring two on re-formation passivation layer two, and forming metal rewiring electrode one and metal rewiring electrode two;Implementing leakage current detection and contact resistance detection;Forming re-formation passivation layer three on rewiring metal layer one;Forming rewiring metal layer two on re-formation passivation layer three, forming metal wiring on ineffective chip;Delivery.The application can make up the deficiency of optical detection in wafer level packaging process.

The invention discloses a vertical power device packaged by a metal-based circuit board. The vertical power device comprises a vertical diode or a field effect transistor wafer, a boss is arranged on the top surface of the metal substrate, and the top surface of the boss is flush with the top surface of the wafer; a hole matched with the boss on the metal substrate is formed in the insulating plate layer, and a hole for accommodating a wafer is also formed in the insulating plate layer; the insulating plate layer is bonded on the metal substrate, the boss of the metal substrate penetrates out of a hole, matched with the boss on the metal substrate, in the insulating plate layer, and the top surface of the boss is flush with the top surface of the insulating plate; the wafer is welded on the top surface of the metal substrate through a bottom surface bonding pad and is located in a hole for accommodating the wafer of the insulating plate layer; and the insulating rubber material is filled in the gaps between the wafer and the edges of the holes of the insulating plate layer for accommodating the wafer, and is filled at the horizontal periphery of the wafer. The packaging of the vertical power device with high cost performance is realized by optimizing a thermoelectric separation circuit board process and combining a chip wafer level packaging method.