1290 results about "Wafer-level packaging" patented technology

A method of forming a package structure with reduced damage to semiconductor dies is provided. The method includes providing a die comprising bond pads on a top surface of the die; forming bumps on the bond pads of the die, wherein the bumps have top surfaces higher than the top surface of the die; mounting the die on a chip carrier, wherein the bumps are attached to the chip carrier; molding the die onto the chip carrier with a molding compound; de-mounting the chip carrier from the die; and forming redistribution traces over, and electrically connected to, the bumps of the die.

The present invention relates to semiconductor device manufacturing techniques, and specifically to a field of device packaging techniques at wafer level. More specifically, it relates to a cap wafer for wafer bonding application that is bonded to top part of a device wafer. The method of the present invention excludes the use of deep reactive ion etching of silicon to form a through silicon via. The present invention provides a method for the preparation of cap wafer for wafer bonding application with a simple process of through silicon via interconnection and a wafer level packaging method using the same.

A semiconductor chip package includes a semiconductor chip having a through hole extending there through from an active first surface to an inactive second surface. A first conductive pad at least partially surrounds the through hole on the active first surface of the semiconductor chip. The package also includes a printed circuit board having a first surface attached to the inactive second surface of the semiconductor chip, and a second conductive pad aligned with the through hole of the semiconductor chip. A conductive material fills the through hole and contacts the first and second conductive pads.

Methods and apparatus are disclosed to form a WLP device that comprises a first chip made of a first technology, and a second chip made of a second technology different from the first technology packaged together by a molding material encapsulating the first chip and the second chip. A post passivation interconnect (PPI) line may be formed on the molding material connected to a first contact pad of the first chip by a first connection, and connected to a second contact pad of the second chip by a second connection, wherein the first connection and the second connection may be a Cu ball, a Cu via, a Cu stud, or other kinds of connections.

A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.

A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.

A surface mount LED package having a tight footprint and small vertical image size is fabricated by a method comprising: forming light emitting diode chips each having a substrate and a plurality of layers configured to emit electroluminescence responsive to electrical energizing; forming electrical vias in a sub mount, the electrical vias passing from a front side of the sub-mount to a back-side of the sub-mount; flip chip bonding the light emitting diode chips on the front-side of the sub mount such that each light emitting diode chip electrically contacts selected electrical vias; thinning or removing the substrates of the flip-chip bonded light emitting diode chips; and after the thinning, disposing a phosphor over the flip chip bonded light emitting diode chips.

An integrally packaged imaging module includes an integrated circuit (IC), including an image sensing device formed on a semiconductor substrate, and wafer level packaging enclosing the IC. The wafer level packaging includes a transparent enclosure portion adapted to permit image acquisition of an image by the image sensing device over a desired range of wavelengths, and a first spacing structure providing a cavity between an inner surface of the transparent enclosure portion and the image sensing device. A depth of the cavity is configurable along an axis perpendicular to the semiconductor substrate to control a distance between an outer surface of the transparent enclosure portion and the image sensing device.

This invention provides an image sensor module with a three-dimensional die-stacking structure. By filling a conductive material into through silicon vias within at least one image sensor die, and into via holes within an insulating layer, vertical electrical connections are formed between the image sensor die and an image processor buried in the insulating layer. A plurality of solder bumps is formed on a backside of the image sensor module so that the module can be directly assembled onto a circuit board. The image sensor module of this invention is characterized by a wafer-level packaging architecture and a three-dimensional die-stacking structure, which reduces electrical connection lengths within the module and thus reduces an area and height of the whole packaged module.

A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input / output pads. The castellation blocks and input / output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input / output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

The present invention relates to a package for semiconductor device and the fabrication method for integrally encapsulating a whole semiconductor chip within a molding compound. In the semicondcutor device package, bonding pads distributed on the top of the chip are redistributed into an array of redistributed bonding pads located in an dielectric layer by utilizing the redistribution technique. The electrodes or signal terminals on the top of the semiconductor chip are connected to an electrode metal segment on the bottom of the chip by conductive materials filled in through holes formed in a silicon substrate of a semiconductor wafer. Furthermore, the top molding portion and the bottom molding portion seal the semiconductor chip completely, thus providing optimum mechanical and electrical protections.

The invention provides a wafer-level package for a micromirror array. The wafer-level package includes a substrate including a wafer having a substrate surface with a plurality of actuatable micromirrors coupled to the substrate surface. An optical window is attached to the substrate surface to form at least one sealed cavity between an inner surface of the optical window and the substrate surface. A beam of light transmitted through the optical window is redirected by at least one actuatable micromirror within the sealed cavity.

Apparatus and methods are provided for enabling wafer-scale encapsulation of microelectromechanical (MEM) devices (e.g., resonators, filters) to protect the MEMs from the ambient and to provide either a controlled ambient or a reduced pressure. In particular, methods for wafer-scale encapsulation of MEM devices are provided, which enable encapsulation of MEM devices under desired ambient conditions that are not determined by the deposition conditions of a sealing process in which MEM release via holes are sealed or pinched-off, and which prevent sealing material from being inadvertently deposited on the MEM device during the sealing process.

A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.

A device comprising a first die enclosed in a wafer scale package, said first die adapted to mate with a printed circuit board (“PCB”) via solder bumps. The device further comprises a second die enclosed in a wafer scale package and electrically connected to a surface of the first die facing the PCB to form a die stack.

A wafer-level package comprises: a first substrate; an electric element provided on the first substrate; a second substrate; an internal electrode pad; a well; and an external electrode pad. The second substrate is opposed to the first substrate with a predetermined gap therebetween. The electric element is provided between the first and second substrates. The internal electrode pad extends onto a first surface of one of the first and the second substrates. The inner electrode pad is connected to the electric element. The well penetrates the one of the first and the second substrates to the internal electrode. The external electrode pad is provided on a second surface of the one of the first and the second substrates and extends onto an inner wall of the well and being connected with the internal electrode pad.

There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a temperature compensated microelectromechanical resonator as well as fabricating, manufacturing, providing and / or controlling microelectromechanical resonators having mechanical structures that include integrated heating and / or temperature sensing elements. In another aspect, the present invention is directed to fabricate, manufacture, provide and / or control microelectromechanical resonators having mechanical structures that are encapsulated using thin film or wafer level encapsulation techniques in a chamber, and including heating and / or temperature sensing elements disposed in the chamber, on the chamber and / or integrated within the mechanical structures. Other aspects of the inventions will be apparent from the detailed description and claims herein.

An integrated MEMS system in which CMOS and MEMS devices are provided to form an integrated CMOS-MEMS system. The system can include a silicon substrate layer, a CMOS layer, MEMS and CMOS devices, and a wafer level packaging (WLP) layer. The CMOS layer can form an interface region, one which any number of CMOS MEMS devices can be configured.

Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.

The present invention provides systems, devices and methods for fabricating miniature low-power light sensors. With the present invention, a light sensitive component, such as a diode, is fabricated on the front side of a silicon wafer. Connectivity from the front side of the wafer to the back side of the wafer is provided by a through silicon via. Solder bumps are then placed on the back side of the wafer to provide coupling to a printed circuit board. The techniques described in the present invention may also be applied to other types of semiconductor devices, such as light-emitting diodes, image sensors, pressure sensors, and flow sensors.

A carrier for use in a chip-scale package, including a semiconductor substrate, such as a semiconductor wafer, with a plurality of apertures formed therethrough. The present invention also includes a chip-scale package including the carrier. When the carrier is employed in such a package, a semiconductor device or a wafer including a plurality of semiconductor devices thereon is invertedly aligned with and disposed over the carrier so that bond pads of the semiconductor device or semiconductor devices substantially align with apertures through the semiconductor substrate. The chip-scale package also includes conductive material disposed in each of the apertures of the semiconductor substrate to form vias through the semiconductor substrate. Conductive traces may extend substantially laterally from selected vias. The chip-scale package may also include a contact or conductive bump disposed in communication with each via. An intermediate layer may be disposed between the semiconductor device and the semiconductor substrate. The intermediate layer may secure the semiconductor device to the semiconductor substrate and insulate structures of the semiconductor device. An insulative layer may be disposed on the semiconductor substrate opposite the semiconductor device. If the chip-scale package includes an intermediate layer or an insulative layer, the electrically conductive vias that extend through the semiconductor substrate are preferably exposed through such layers. The present invention also includes methods of fabricating the semiconductor substrate and assembling a chip-scale package of the invention, including substantially simultaneously assembling semiconductor devices and carrier substrates on a wafer-scale and singulating individual chip-scale packages from the assembled wafers.

The present invention provides a structure of package comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and a through hole structure formed there through, wherein a terminal pad is formed under the through hole structure and the substrate includes a conductive trace formed on a lower surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. A re-distribution metal layer (RDL) is formed on the dielectric layer and coupled to the die and the through hole structure. Conductive bumps are coupled to the terminal pad.

A method of manufacturing a wafer level package includes forming a semiconductor wafer including semiconductor chips, and forming a package body on the sides of each semiconductor chip. The package body is formed by forming a space between each semiconductor chip and potting a package material in the space, which can be a mold resin. The wafer is then separated into separate semiconductor chips by cutting through the package body.

The present invention relates to a wafer level package and a method of manufacturing the same and a method of reusing a chip and provides a wafer level package including a chip; a removable resin layer formed to surround side surfaces and a lower surface of the chip; a molding material formed on the lower surface of the removable resin layer; a dielectric layer formed over the removable resin layer including the chip and having via holes to expose portions of the chip; redistribution lines formed on the dielectric layer including insides of the via holes to be connected to the chip; and a solder resist layer formed on the dielectric layer to expose portions of the redistribution lines. Also, the present invention provides a method of manufacturing a wafer level package and a method of reusing a chip.

To pick and place standard dice on a new base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type wafer level package. Moreover, the die may be packaged with passive components or other dice with a side by side structure or a stacking structure.