195 results about "Wafer-level packaging" patented technology

The invention provides a preparation method of an inertial sensor and the sensor. The preparation method comprises the following steps: sequentially forming a first cavity and a first oxide layer on a first silicon wafer; bonding the first silicon wafer and a second silicon wafer, wherein the second silicon wafer is a low-resistance silicon wafer; forming an inertia sensitive structure in the second silicon wafer; correspondingly forming a second cavity on a third silicon wafer, wherein the third silicon wafer is a low-resistance silicon wafer; bonding the third silicon wafer and the second silicon wafer; an isolation groove penetrating through the third silicon wafer is formed through etching, a conductive silicon column and an electric signal isolation ring are formed, and the conductive silicon column is connected with the inertia sensitive structure; and forming a sealing insulating layer on the surface of the third silicon wafer, and forming a signal lead-out pin in the sealing insulating layer. According to the scheme, thermal stress caused by thermal expansion coefficient mismatch among the three layers of wafers is reduced through an all-silicon wafer level packaging process, and the full-temperature characteristic of the device is greatly enhanced; and the preparation process flow is optimized, the process control difficulty is reduced, and the preparation cost is reduced.

The invention discloses a novel wafer-level packaging structure and a manufacturing method, and belongs to the technical field of semiconductors, and the method comprises the steps: 1, preparing a wafer to be processed, and enabling the wafer to comprise a welding pad; step 2, coating a dielectric material above the wafer, forming a dielectric layer through exposure and development, curing the dielectric layer, and exposing the dielectric layer out of the welding pad; 3, forming a metal seed layer above the dielectric layer and the welding pad for realizing electrical interconnection; and 4, coating a photoresist I on the metal seed layer, exposing and developing the photoresist I, electroplating on the exposed metal seed layer after developing, and removing the photoresist I to form a metal layer I. The thickened copper layer II in the metal layer I serves as a sputtering seed layer of the metal layer II, and the sputtering seed layer below the metal layer I is utilized, so that an additional sputtering seed layer does not need to be sputtered on the metal layer I, the cost is saved, and the technological process is simplified.

The invention relates to the technical field of semiconductor packaging detection, in particular to a semiconductor packaging micro welding spot three-dimensional shape intelligent detection system which comprises a sample placing frame, an imaging module, an image processing unit, a detection module and a result display module. The image processing unit constructs a unified curvature field expression by fusing three-dimensional information of three different imaging principles of a spherical mirror model, a light-sectioning microscopic three-dimensional reconstruction algorithm and stripe structured light, and adopts adaptive mesh refinement to process a curvature change violent region; the detection module identifies welding spot defects such as pseudo soldering, bridging and poor connection based on differential invariants and singularity analysis, the system realizes high-precision detection of various semiconductor packaging forms such as BGA, QFN packaging and wafer-level packaging, the measurement precision is improved by 35%-40%, the processing efficiency is improved by about 50%, the defect omission ratio is reduced from 15% to below 3%, and the detection accuracy is greatly improved. And a brand new solution is provided for semiconductor packaging quality control.

The invention discloses an image sensing chip board-level packaging structure and a manufacturing method thereof.The packaging structure comprises a cofferdam type chip unit, the cofferdam type chip unit comprises a transparent substrate, a cofferdam structure and an image sensing chip, the front face of the image sensing chip is provided with a photosensitive area and a bonding pad, the transparent substrate covers the photosensitive area, and the cofferdam structure covers the bonding pad; a cofferdam structure is arranged between the transparent substrate and the image sensing chip, and the cofferdam structure surrounds the photosensitive area to form a closed area; the plastic package body wraps the side surface and the back surface of the cofferdam type chip unit; the first rewiring layer is arranged on one side, close to the front surface of the image sensing chip, of the plastic package body and is electrically connected with a bonding pad of the image sensing chip; the second rewiring layer penetrates through the plastic package body and is electrically connected with the first rewiring layer; and the external interconnection structure is electrically connected with the second rewiring layer. The packaging structure has excellent electrical quality and reliability, the packaging size is larger than the size of a bare chip, and the problem that the heat dissipation capacity is limited due to miniaturization of wafer-level packaging can be solved.

Encapsulated MEMS devices and methods of fabrication with wafer-level fabrication processes are described which address small molecule diffusion into hermetically sealed cavities. In some configurations a small molecule barrier layer, or hydrogen barrier layer, is formed during a back-end-of-the-line (BEOL) processing over a cap wafer including a planarized surface formed during a via reveal griding operation. In some configurations a small molecule barrier layer is not formed over the planarized surface during BEOL processing in order to allow an escape path for small molecules. In some configurations a small molecule barrier layer, or hydrogen barrier layer, is formed on a bottom side of a cap wafer prior to bonding the cap wafer to a device wafer during wafer-level fabrication.

The invention relates to the technical field of microelectronics and MEMS manufacturing, in particular to a bulk acoustic resonator with a double-layer piezoelectric film and a preparation method thereof, according to the method, a heterogeneous integrated key structure is formed by a first piezoelectric layer and a second piezoelectric layer which are deposited on the two sides of a middle electrode layer respectively, the physical and process limits of a single-layer piezoelectric film FBAR are broken through, the high-frequency band is improved, and the high-frequency band is improved. A wider bandwidth is realized; middle electrode layer tuning is combined with back silicon through hole leading-out, front routing inductance is eliminated, and the low-loss characteristic of the filter under high frequency is guaranteed; the self-heating problem under large bandwidth and high power is effectively inhibited through heat dissipation integrated packaging, and the power bearing capacity is improved; the method is compatible with a CMOS (complementary metal oxide semiconductor) process and can be directly embedded into an existing production line, so that the volume is further reduced while the bulk acoustic wave resonator with the double-layer piezoelectric film can effectively cover a frequency band of more than 3GHz, and the problem that a single-layer piezoelectric film and a matched process thereof cannot meet the requirements of a next-generation radio frequency front end on high frequency, large bandwidth, high power and wafer-level packaging is solved.

The invention provides an integrated multichannel pulse modulation type power switch control technology, and a power switch control device with high integration level and high performance is created through a heterogeneous integration technology, a multichannel PWM (Pulse Width Modulation) architecture and an intelligent protection mechanism. Wafer level packaging (WLP) and flip-chip bonding technologies are adopted, a PWM control chip and a GaN / SiC field effect transistor of a CMOS technology and a driver and a protection circuit of a Bipolar technology are integrated in single surface-mounted packaging, the number of external elements is greatly reduced, the space utilization rate of a circuit board is improved, and the overall size is reduced. By optimizing a multi-layer PCB structure and separating a high-frequency signal path from a power supply network, parasitic inductance is effectively suppressed, and the problem of packaging stress caused by difference of thermal expansion coefficients among heterogeneous processes is relieved.

The application discloses a kind of through superimposed photoresist layer the method for manufacturing wafer level packaging product, and the application belongs to wafer level packaging field, including step one: preparation glass wafer, release layer and sputtering layer are coated on the glass wafer top;Step two: the first heavy wiring layer is formed on the sputtering layer top;Step three: metal seed layer is set on the first heavy wiring layer top;Step four: photoresist is coated on the first heavy wiring layer top to form photoresist one;Step five: the photoresist one is carried out alignment exposure operation to photoresist one by mask one;Step six: photoresist one is developed to form opening structure one.The application utilizes the way of high tackiness wet film photoresist to manufacture silicon through hole bump, can solve the technical problem of silicon through hole bump preparation in advanced packaging field, effectively improve the product quality and production yield of chip, suitable for advanced packaging silicon through hole bump whole process preparation link.

The application discloses a surface acoustic wave filter wafer level packaging structure and a manufacturing method thereof. The surface acoustic wave filter wafer level packaging structure comprises a wafer, a first surface of the wafer is provided with a surface acoustic wave filter, wherein the surface acoustic wave filter comprises an interdigital transducer and at least two electrodes, and a part of the electrodes protrudes from the edge of the wafer; a cofferdam layer is located between the interdigital transducer and the electrodes and surrounds the interdigital transducer, and the thickness of the cofferdam layer is greater than the thickness of the interdigital transducer; a shielding layer is located on the side of the cofferdam layer away from the wafer; a packaging layer is located on the side of the shielding layer away from the wafer, the packaging layer covers the first surface of the wafer, the surface of the electrode away from the wafer, the cofferdam layer and the shielding layer, and the packaging layer is provided with a groove adjacent to the surface of the wafer, and the side wall of the groove exposes the side surface of the electrode. The packaging structure and the manufacturing method thereof provided in the embodiment can improve the sealing performance of the wafer and the reliability of the surface acoustic wave filter wafer level packaging structure.

A fan-out wafer-level packaging (FOWLP) unit including a substrate, at least one first die, a first dielectric layer, a plurality of first conductive circuits, a second dielectric layer, a plurality of second conductive circuits, and at least one second die is provided. A range perpendicular to a second surface of the first die is defined as a chip area. The second dielectric layer is provided with a plurality of second slots allowing the second conductive circuit to expose and form bonding pads. The bonding pads located around the chip area are first bonding pads. The second die is disposed over the second dielectric layer by flip chip and electrically connected to the first die which is electrically connected with the outside by the first bonding pads. Thereby problems of conventional FOWLP generated during manufacturing of the conductive circuits including higher manufacturing cost and less environmental benefit can be solved.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

The utility model discloses a fan-out type wafer level packaging unit. The fan-out type wafer level packaging unit comprises a carrier plate, at least one bare chip, a first dielectric layer, at least one conductive column, a second dielectric layer, a plurality of first conductive connection lines, a first outer protective layer, a third dielectric layer, a plurality of second conductive connection lines and a second outer protective layer, wherein the die can be electrically connected to the outside by at least one first bonding pad around a chip region on the second side of the die; wherein the die can be electrically connected to the outside through a second bonding pad in at least one opening of the second outer protective layer; wherein each first conductive connection line and each second conductive connection line are manufactured by a technology of filling metal paste into the grooves and then grinding and forming the conductive connection lines, so that the problems that the manufacturing cost is high and environmental protection is not facilitated when each conductive connection line is manufactured by the existing fan-out packaging technology are solved.

The invention provides a wafer-level packaging structure and a preparation method thereof. The wafer-level packaging structure comprises an insulating layer, a chip arranged on the insulating layer, a plastic packaging layer wrapping the chip, and a rewiring layer, wherein the side surface of the plastic packaging layer and the interior of the insulating layer are provided with communicated gaps, and the rewiring layer extends into the gaps and is connected and conducted with the chip; the rewiring layer comprises a side surface connecting part formed in the gap and an L connecting part connected between the side surface connecting part and the chip; the chips are connected and conducted with an external circuit through the L connecting parts, and every two adjacent chips are connected and conducted through the side face connecting parts at the corresponding positions. According to the invention, multi-surface signal conduction of the chip can be realized, the packaging flexibility is improved, and the chip density is increased.

The invention discloses a Micro-OLED (Organic Light Emitting Diode) chip packaging structure, a Micro-OLED chip packaging method and a Micro-OLED display device. The packaging structure comprises a semiconductor wafer which is provided with a conductive through hole penetrating to a metal bonding pad on the front surface of the semiconductor wafer; the plurality of metal bumps are formed on the back surface of the semiconductor wafer and are electrically connected with the metal bonding pads on the front surface through the conductive through holes and the metal rewiring layer on the back surface; the Micro-OLED light emitting layer is formed on the front surface of the semiconductor wafer; and the transparent cover plate is bonded with the front surface of the semiconductor wafer through a supporting wall. According to the invention, the wafer-level chip size packaging process sequence of the Micro-OLED is optimized as follows: the through holes and the salient points are firstly manufactured on the back surface, and then the OLED is manufactured on the front surface. According to the method, the metal bonding pads are allowed to be led out from the two sides, three sides or four sides of the chip, and particularly, the large-current power supply / ground bonding pads are arranged at the four corners of the chip, so that the internal current distribution of the chip is remarkably optimized, the IR voltage drop is reduced, and thinner and smaller Micro-OLED wafer-level packaging with better electrical performance is realized.

A fan-out wafer level packaging (FOWLP) unit which includes a substrate, a first dielectric layer, at least one antenna, at least one die, a second dielectric layer, at least one conductive pillar, a plurality of first conductive circuits, a third dielectric layer, a plurality of second conductive circuits, and an outer protective layer is provided. The first conductive circuits and the second conductive circuits are produced by filling a metal paste into slots and grinding the metal paste. The die is electrically connected with the antenna. The die is electrically connected to the outside through bonding pads around a chip area on a second surface of the die. Thereby the FOWLP unit is formed and problems of the FOWLP module or technology available now generated during manufacturing of the respective conductive circuits including higher manufacturing cost and less environmental benefit can be solved.

The application discloses an LED wafer-level packaging method, and steps are as follows: S1, preparing a substrate; S2, making and forming a conductive path through the substrate on the substrate; S3, making and forming an optical coupling layer on the inner bottom surface of the accommodating cavity; S4, assembling a light source chip in the accommodating cavity, and the light emitting surface of the light source chip faces the optical coupling layer; S5, making and forming an optical structure on the second surface of the substrate, and the optical structure is in optical path communication with the optical coupling layer; and S6, making and forming a conductive terminal electrically connected with one end of the conductive path on the second surface of the substrate. The substrate has three functions of bearing, light transmission and optical shaping, three independent structure layers of a plastic shell, a copper embedded base and an independent lens in the prior art are cancelled, and therefore the total thickness of the LED packaging structure can be controlled to be less than 0.5 mm.

The application provides a via hole forming method, a wafer level packaging structure, a method and a communication device. The via hole forming method comprises the following steps: providing a cover plate, wherein the cover plate comprises a first surface and a second surface arranged opposite to the first surface; forming a blind hole on the first surface of the cover plate; forming a protective layer in the blind hole; performing a thinning treatment on the second surface of the cover plate to expose the protective layer at the bottom of the blind hole; and removing the protective layer to convert the blind hole into a via hole. The technical solution provided by the application improves the yield of forming the via hole in the cover plate.

The invention discloses a wafer packaging structure and a wafer packaging method.The wafer packaging structure comprises a cap and a wafer which are oppositely arranged, a device structure is arranged on the wafer, a sealing ring is arranged between the cap and the wafer, and therefore a sealing cavity is defined by a metal layer and an organic material layer in the cap, the sealing ring and the wafer; the metal layer in the cap comprises a first metal region and a plurality of second metal regions which are insulated from each other, the second metal regions are electrically connected with the device structure through metal bumps, and metal balls electrically connected with an external power supply are arranged on the second metal regions; therefore, the device structure obtains the electric energy of an external power supply through the metal bumps, the second metal regions and the metal balls, breaks through the existing MEMS wafer level packaging mode, optimizes the process flow, shortens the process time, reduces the cost, and improves the production efficiency. In addition, the metal protruding block is located in the sealing cavity and can support the cap structure, so that the cap structure is firm and stable.

A wafer-level package is described. In an embodiment, the wafer-level package (100) comprises: a substrate (102) having electrically conductive interconnects embedded within the substrate (102), the substrate (102) having a top substrate surface and a bottom substrate surface opposite to the top substrate surface, the bottom substrate surface being adapted to be provided on a printed circuit board (PCB); a first integrated circuit die (104) having an active surface wherein the first integrated circuit die is provided adjacent to an edge portion of a perimeter of the substrate (102); a mold (108) adapted to hold the first integrated circuit die (104) and the substrate (102) so that the active surface of the first integrated circuit die (104) is in a same plane as the top substrate surface; a first redistribution layer (110) having electrically conductive interconnects embedded within the first redistribution layer (110), the first redistribution layer (110) being formed on the active surface of the first integrated circuit die (104) and the top substrate surface; and a second integrated circuit die (112) provided on the first redistribution layer (110), the second integrated circuit die (112) being electrically connected to the first integrated circuit die (104) via the first redistribution layer (110). Embodiments in relation to a method (200) for forming the wafer-level package are also described.

The invention relates to the technical field of semiconductor packaging, in particular to a wafer level packaging structure and packaging method.The wafer level packaging structure comprises a chip and a window, the chip comprises a reading circuit and an MEMS structure, the opposite faces of the reading circuit and the window are a first bonding face and a second bonding face respectively, and the MEMS structure is arranged on the first bonding face; a high-flowability solder is arranged between the first bonding surface and the second bonding surface, and the high-flowability solder is respectively bonded with the first bonding surface and the second bonding surface; the high-fluidity solder is made of tin, indium silver alloy or SAC305. According to the method, the high-fluidity solder is adopted to replace gold-tin solder to realize bonding of the window and the chip, stress change can be better adapted in the bonding process, the stress concentration phenomenon generated in the bonding process is effectively relieved, the problem of relatively large bonding stress is improved, the chip MEMS structure damage caused by relatively large bonding stress is effectively avoided, and the service life of the chip is prolonged. And the product yield is improved.

An aspect relates to a method of forming an integrated circuit (IC) package, including: forming a thin-film inductor (TFI) over a first dummy carrier wafer; attaching an integrated circuit (IC) die to and over the TFI; attaching a second dummy carrier wafer to and over the IC die; removing the first dummy carrier wafer from the TFI; attaching at least one solder bump to and under the TFI; and removing the second dummy carrier wafer from the IC die. Another aspect relates to a method of forming an IC package, including forming a first redistribution layer (RDL) over a through-silicon via (TSV); forming a second RDL under the TSV; forming a thin-film inductor (TFI) over the first RDL; and attaching at least one integrated circuit (IC) die to the second RDL or the TFI.

The invention discloses a fan-out type wafer level packaging unit which comprises a carrier plate, at least one bare chip, a first dielectric layer, at least one conductive column, a second dielectric layer, a plurality of first conductive connection lines, a first outer protection layer, a third dielectric layer, a plurality of second conductive connection lines and a second outer protection layer. Wherein the die can be electrically connected to the outside by at least one first bonding pad around a chip region on the second side of the die; wherein the die can be electrically connected to the outside through a second bonding pad in at least one opening of the second outer protective layer; wherein each first conductive connection line and each second conductive connection line are manufactured by a technology of filling metal paste into the grooves and then grinding and forming the conductive connection lines, so that the problems that the manufacturing cost is high and environmental protection is not facilitated when each conductive connection line is manufactured by the existing fan-out packaging technology are solved.

An advanced 2.5D panel-level packaging structure and a forming method thereof, the forming method comprising: forming a plurality of chip structures; forming a panel-level packaging body, the panel-level packaging body comprising a plurality of packaging units; bonding and connecting the plurality of chip structures and the plurality of packaging units correspondingly; and performing cutting processing on the panel-level packaging body to form a plurality of packaging units. By fully utilizing the advantage of the panel-level packaging body in size specification, the fixed limitation of wafer-level packaging in area utilization and cost control is broken. By performing cutting processing on the panel-level packaging body to form a plurality of packaging units, a plurality of packaging structures can be processed in parallel on the same panel, which significantly improves the production efficiency and reduces the unit manufacturing cost. In addition, the unified preparation of the panel-level packaging body provides a standardized platform for the subsequent integration of diversified chips, which is conducive to realizing the high-density heterogeneous integration of different functional chips and meeting the development needs of advanced packaging technology in system-level integration and multi-functional fusion.

A fan-out wafer-level packaging (FOWLP) unit is provided. The FOWLP unit includes a substrate, a first dielectric layer, a plurality of first conductive circuits, at least one first die, a second dielectric layer, at least one conductive pillar, a plurality of second conductive circuits, a third dielectric layer, a plurality of third conductive circuits, and at least one second die. The first die and the second die are electrically connected with the outside through first die pads around a chip area on a second surface of the first die. The first conductive circuits, the second conductive circuits, and the third conductive circuits are produced by filling of metal pastes into slots and grinding of the metal paste. Thereby problems of FOWLP technology available now generated during manufacturing of the respective conductive circuits including higher manufacturing cost and environmental unfriendly can be solved.

This invention relates to the field of semiconductor technology, providing a wafer-level packaging method and structure. The method includes: providing a MEMS suspended structure and a cover plate structure; etching trenches and electrode patterns on the bonding surface of the cover plate structure; directly bonding the MEMS suspended structure and the cover plate structure; etching the front side of the cover plate structure to achieve trench penetration; bonding the cover plate structure to a glass anode to form a glass sealing layer; melting the glass of the glass sealing layer at high temperature and reflowing it into the trenches to form an electrode isolation layer that isolates the through-penetrating electrodes; and thinning and polishing the glass sealing layer. This invention utilizes direct bonding technology combined with a glass reflow scheme to achieve wafer-level packaging of chips. The glass, as an isolation and sealing material, exists only in extremely fine trenches, solving the problem of poor temperature performance and low temperature linearity of devices caused by thermal stress mismatch when other materials are introduced.

The method comprises the steps that a silicon wafer with the size larger than 12 inches is provided, the silicon content proportion of the silicon wafer is larger than 80%, a TSV hole is formed in the silicon wafer with the size larger than 12 inches, an interposer with the size larger than 12 inches is obtained, the TSV hole is preprocessed, a UBM layer is formed on the surface of the interposer with the size larger than 12 inches, and the UBM layer is formed on the surface of the interposer with the size larger than 12 inches. And bonding a chip on the UBM layer, and carrying out plastic package processing on the surface of the interposer with the chip to obtain a plastic package wafer greater than 12 inches. According to the wafer-level packaging method of the integrated chip provided by the embodiment of the invention, the silicon wafer greater than 12 inches is used as the interposer to increase the packaging area of the integrated chip and accommodate the packaging of more processors or storage chips, so that the requirement on high-speed operation in the field of artificial intelligence is met, the utilization rate of the interposer is improved, and the packaging efficiency of the integrated chip is improved. And the problems of insufficient integrated packaging capacity and high cost of the current artificial intelligence chip are better solved.

This invention relates to a wafer-level packaging structure for multiple heterogeneous chips, comprising interconnected first and second remolded wafers. The first remolded wafer includes multiple first chips, and the second remolded wafer includes multiple second chips, wherein the first and second chips are different. By molding the first and second chips into two remolded wafers and bonding the two remolded wafers, up to dozens of heterogeneous chips can be connected between the two remolded wafers. Moreover, the heterogeneous chips are directly connected through electrodes on the chips, greatly increasing the number of interconnections between computing chips and interface chips, improving bandwidth, and shortening communication links.

The application discloses a wafer-level chip packaging method and a packaging structure. The method comprises the following steps: providing a wafer-level substrate; forming a re-distribution layer on the upper surface of the wafer-level substrate, wherein the re-distribution layer comprises a metal layer, a passive device is arranged in the re-distribution layer, and the passive device is electrically connected with the metal layer; providing a chip, wherein the chip has a sensing area and a bonding pad electrically coupled with the sensing area; flip-chip mounting the chip on the re-distribution layer, and electrically connecting the bonding pad with the metal layer; filling plastic packaging material to package the chip and the re-distribution layer; peeling off the wafer-level substrate, and forming an external protrusion on the surface of the re-distribution layer, wherein the external protrusion is electrically connected with the metal layer; and cutting the formed wafer-level packaging structure to obtain a plurality of independent chip packaging structures. The wafer-level chip packaging method can improve the packaging efficiency and reduce the packaging volume.

The application discloses a semiconductor wafer-level packaging method and a packaging structure. In the semiconductor wafer-level packaging method, the ring-shaped protrusion is arranged, and the glue coating mode is used, so that the packaging bonding strength is maintained, the air tightness and reliability of the packaging structure are improved, and the bonding glue can prevent the functional area from being affected.

A surface acoustic wave device including a piezoelectric layer, an interdigital transducer electrode over the piezoelectric layer, and a polymeric roof layer arranged over the piezoelectric layer and interdigital transducer electrode. The polymeric roof layer is spaced apart from the piezoelectric layer to define a cavity to accommodate the interdigital transducer electrode. The polymeric roof layer is supported along a span of the polymeric roof layer by at least one pillar. The thermal conductivity of the pillar is greater than the thermal conductivity of the polymeric roof layer. Related wafer-level packages, radio frequency modules and wireless communication devices are also provided.