18 results about "Solder wetting" patented technology

The invention provides a circuit board welding spot quality evaluation method based on machine learning, and the method comprises the steps: collecting the three-dimensional point cloud data of welding spots on the surface of a circuit board, analyzing the height difference and height distribution uniformity of the welding spots, and obtaining the height abnormal mode feature vectors of the uneven welding flux distribution and the abnormal welding spot shape; according to the height abnormal mode feature vector, the welding spot volume abnormal position is judged, and a welding spot abnormal position set is generated; according to the height gradient distribution diagram, dividing a height gradient mutation and surface flatness deviation region, and determining a circuit board welding spot height abnormal region boundary containing poor solder wetting; for the circuit board welding spot height anomaly region boundary, the welding spot contact area and the welding flux flowing direction are obtained, the height anomaly judgment standard is adjusted in a self-adaption threshold value mode, and a dynamic height detection rule is generated; and extracting height consistency characteristics of the welding spots from the dynamic height detection rule, analyzing weak links of mechanical strength of the welding spots in combination with local stress concentration data, and judging a signal transmission delay risk.

The invention discloses a SnSb8 soldering lug welding process which is characterized in that a preformed hexagonal soldering lug is adopted as a soldering lug, the preformed soldering lug and a welded substrate are directly welded in a local vacuum reflow soldering mode, and the welding process mainly comprises the steps of vacuumizing, nitrogen filling, vacuumizing, formic acid filling, air blowing, first heating, second heating, cooling, vacuumizing and nitrogen filling. A multi-stage gas environment control process is innovatively introduced, a low-oxygen environment is constructed through a double-vacuumizing-double-inflating process (nitrogen and formic acid), and formic acid gas is decomposed at high temperature to generate reducing substances to replace traditional scaling powder; the composite process of gradient temperature control and gas purging is developed, formic acid purging is implemented in a specific temperature window, the oxide removal and solder wetting processes are synchronously completed, scaling powder does not need to be additionally added during welding, the technological process is simplified, and cavities are reduced.

The invention relates to the technical field of circuit board manufacturing, and discloses a circuit board manufacturing method suitable for an Msap process and a circuit board, and the method comprises the steps: S100, pasting a dry film at a position corresponding to an etching line on one side or two sides of a laminated board; s200, pattern electroplating is conducted on the laminated board till the difference value between the height of the laminated board and the height of the dry film is within a preset value range; s300, the surface, subjected to pattern electroplating, of the laminated board is leveled, and the horizontal plane of the leveled laminated board coincides with the end face of the leveled dry film; and S400, removing the dry film attached to the surface of the laminated board, and carrying out surface treatment to obtain a finished product carrier board. According to the method, the electroplated layer is removed through leveling with the dry film, so that the electroplated layer is overlapped with the end face of the dry film, the micro step difference between the electroplated layer and the dry film is eliminated, defects formed on the surface of the electroplated layer are removed, and secondary defects such as uneven solder infiltration and blind hole deviation can be fundamentally eliminated.

To provide a laminated resistor that is low in height and suppresses a short circuit caused by solder wetting.SOLUTION: A multilayer resistor includes a thin plate-shaped resistor having a first plane and a second plane in the thickness direction, a first electrode formed on the first plane, and a second electrode formed on the second plane, the resistor contains a nickel-chromium or iron-chromium metal material, the second electrode faces a circuit pattern when mounted on a circuit board, and the thickness of the resistor is configured to be between three and eight times the thickness of the second electrode.SELECTED DRAWING: Figure 1

The invention discloses a tin-zinc-copper powder ultrafine powder batch preparation process, and relates to the technical field of metal powder preparation, and the tin-zinc-copper powder ultrafine powder batch preparation process comprises the following steps: dissolving tin salt, zinc salt and copper salt in deionized water, adding a complexing agent, and uniformly mixing to obtain a mixed metal salt aqueous solution; dissolving a rosin-based polyamine hyperbranched dispersant in an organic solvent to serve as an oil phase; slowly adding a mixed metal salt aqueous solution into the oil phase, and uniformly dispersing to obtain a water-in-oil microemulsion system; dropwise adding a reducing agent solution, and continuously carrying out heat preservation reaction for 0.5-3 hours after dropwise adding is finished, so as to obtain slurry containing alloy particles; and carrying out demulsification treatment, centrifugal separation, repeated washing and drying to obtain the surface-modified tin-zinc-copper superfine powder. Superfining of particles is achieved through confinement growth, synchronous co-deposition of multi-component elements is guaranteed, a homogeneous alloy phase is formed, component segregation is avoided, and a protective layer formed on the surface of the powder in situ endows the material with excellent oxidation resistance and good weld-aid wettability.

Provided is a layered resistor that has a low profile but still suppresses short circuiting caused by solder wetting.　A layered resistor according to the present invention includes a resistance element that has a thin plate shape and has a first flat surface and a second flat surface in the thickness direction, a first electrode that is formed on the first flat surface, and a second electrode that is formed on the second flat surface. The resistance element includes a nickel / chromium or iron / chromium metal material, the second electrode is opposite a circuit pattern when the layered resistor is mounted on a circuit board, and the thickness of the resistance element is 3–8 times the thickness of the second electrode.

A semiconductor package includes: a substrate having a metallic surface; a semiconductor die metallurgically bonded to the metallic surface of the substrate by a first solder joint; and a solder wetting structure metallurgically welded to the metallic surface of the substrate outside a perimeter of the semiconductor die and adjacent to one or more side faces of the semiconductor die. Excess solder squeezed out from under the semiconductor die is metallurgically bonded to the solder wetting structure. Methods of producing the semiconductor package and solder wetting structure are also described.

A method of manufacturing a semiconductor device interconnect structure is provided. The method includes forming a copper pillar on a semiconductor die by way of a plating process. A proximal portion of the copper pillar has a first width dimension, and a distal portion of the copper pillar has a second width dimension. The second width dimension of the distal portion of the copper pillar is configured to be smaller than the first width dimension of the proximal portion of the copper pillar. Sidewalls of the distal portion of the copper pillar are selectively roughened. The roughened sidewalls of the distal portion of the copper pillar are configured to promote solder wetting.

Provided is a semiconductor device in which solder spreading due to excessive wetting is suppressed. A semiconductor device is provided with: an insulating circuit board (1) having an insulating substrate (11), and an upper conductor layer (12a) and an upper conductor layer (12b) provided on the upper surface of the insulating substrate (11) so as to be separated from each other; a semiconductor chip (3) mounted on the upper conductor layer (12a) via solder; an external terminal (4) having a bonding portion (41) bonded to a first bonding region (14), which is one region of the upper surface of the upper conductor layer (12b), via solder (2b); a printed circuit board (6) disposed above the semiconductor chip (3); a pin terminal (51) that is inserted into the printed circuit board (6), and that is bonded to a second bonding region (15), which is the other region of the upper surface of the upper conductor layer (12b), via solder (9a); and a solder resist part (7) provided on the upper surface side of the upper conductor layer (12b) and adjacent to the first bonding region (14).

We propose a technology that effectively suppresses unwanted solder wetting and spreading when soldering semiconductor substrates. [Solution] The semiconductor device comprises a semiconductor substrate and a metal layer provided on the surface of the semiconductor substrate. The metal layer has a first metal layer and a second metal layer that covers the surface of the first metal layer and has higher solder wettability than the first metal layer. The second metal layer is exposed on the main surface of the metal layer. The first metal layer is exposed on the side surface of the metal layer. A projection is provided on the main surface of the metal layer. The projection extends in a circular manner along the outer edge of the main surface.

The application provides a photovoltaic active solder, a grid line-free heterojunction cell and a module and a preparation method, wherein the photovoltaic active solder comprises a first component and a matrix, the first component can increase the solder wetting performance of the matrix and strengthen the beta-Sn phase / In phase / Zn phase grains in the solder matrix, the soldering strength is improved, the risk of grid breakage of the module is reduced after the module is prepared, and the reliability of the module is enhanced. The ultra-fine active solder wire prepared by using the aforementioned photovoltaic active solder replaces the grid line in the prior art, printing and curing of the grid line are not required in the cell manufacturing process, the slurry and the printing and curing process and equipment thereof are omitted, in addition, the transmission resistance and the contact resistance on the current output path of the cell after soldering are small, and the electrical performance of the cell can be improved.

The invention provides a multilayer ceramic capacitor capable of suppressing wetting and climbing of solder to a surface opposite to a mounting surface during mounting. A laminated ceramic capacitor (10) according to the present invention is provided with: a laminated body having a first surface and a second surface facing each other in a lamination direction, a third surface and a fourth surface facing each other in a first direction orthogonal to the lamination direction, and a fifth surface and a sixth surface facing each other in a second direction orthogonal to the lamination direction and the first direction; a first external electrode disposed on the first surface and the third surface; a second external electrode disposed on the first surface and the fourth surface; a third external electrode disposed on the first surface and the third surface; and a fourth external electrode disposed on the first surface and the fourth surface. The laminate includes a first internal electrode and a second internal electrode. The first external electrode includes: a first base layer connected to the first internal electrode; a first thin film layer disposed on the first surface; and a first surface plating layer. The first external electrode has a first recess located on the inner side of the laminate, and the dimension of the first recess in the second direction is longer than the dimension in the first direction.

This invention discloses a double-sided gold spraying device for thin-film capacitor cores, belonging to the field of capacitor core gold spraying. The device includes two support plates forming a conveying channel, a fixed plate fixed to the outer wall of the support plates, a carrier plate capable of reciprocating up and down on the fixed plate, and a spraying support block slidably mounted on the carrier plate; a spraying pipe mounted on the spraying support block, with a material conveying pipe attached to the spraying pipe; an air jet pipe mounted on the spraying support block; and a spraying disc connected to the spraying pipe and the air jet pipe. This invention can quickly blow away and remove loose, unbonded metal dross and oxide impurities adhering to the end face of the thin-film capacitor core after gold spraying, leaving a dense and uniform gold layer on the end face. This avoids dross obstructing solder wetting and contact, thereby ensuring the firmness and reliability of subsequent soldering.

This invention provides a method, apparatus, and electronic device for determining the solder penetration rate of a semiconductor. The method includes: acquiring an image of a semiconductor to be inspected under the action of an X-ray inspection device; inputting the image to be inspected into a pre-trained semiconductor via pin segmentation model for analysis and processing, to output a first segmented region image containing at least one via pin region and a second segmented region image containing a via solder wetting region; and determining the solder penetration rate corresponding to the via pin region in the semiconductor to be inspected based on the region information corresponding to the first and second segmented region images. This technical solution improves the segmentation effect of semiconductor image segmentation, thereby improving the accuracy of solder penetration rate detection for X-ray semiconductor images.

The present invention provides a multilayer ceramic capacitor (1) which exhibits excellent solder wetting during mounting and which causes few soldering failures. This multilayer ceramic capacitor (1) comprises: a multilayer body (2) including a dielectric layer (20), a first internal electrode layer (31), and a second internal electrode layer (32); a first external electrode (41); and a second external electrode (42). The first external electrode (41) and the second external electrode (42) each have a Ni plating layer (63), and an Sn plating layer (66) positioned on the Ni plating layer (63). The number of Sn deposition particles 300 exposed from the surface of the Sn plating layer (66) is 1-10 inclusive, in a range of 30 μm within the surface.

The invention relates to a semiconductor device interconnect structure and a method thereof. A method of fabricating a semiconductor device interconnect structure is provided. The method includes forming a copper pillar over a semiconductor die by means of a plating process. A proximal portion of the copper pillar has a first width dimension and a distal portion of the copper pillar has a second width dimension. The second width dimension of the distal portion of the copper pillar is configured to be less than the first width dimension of the proximal portion of the copper pillar. A sidewall of the distal portion of the copper pillar is selectively roughened. A roughened sidewall of the distal portion of the copper pillar is configured to promote solder wetting.

The vertically stacked semiconductor device provided by the embodiment of the utility model comprises an intermediate redistribution circuit layer connecting pad positioned below a plurality of bump structures. The intermediate redistribution layer pad is located between the first semiconductor substrate and the plurality of bump structures. The bump structure includes a metal layer and a barrier layer having lower solder wettability between the metal layer and the intermediate redistribution layer pad. The barrier layer may limit solder wetting along sidewalls of the bump structure to minimize solder bridging and other defects. In some embodiments, the intermediate redistribution layer pads may have relatively low solder wettability to minimize solder defects. Characteristics of the intermediate redistribution layer pads and the bump structures may be controlled to improve flatness characteristics of the bump structures.

Vertically stacked semiconductor devices and methods of fabrication thereof include intermediate redistribution layer (RDL) pads underlying a plurality of bump structures. A plurality of intermediate RDL pads may be formed over a first device structure, and at least one bump structure may be formed over each of the intermediate RDL pads. The bump structures include a metal layer and a barrier layer having a lower solder wettability located between the metal layer and the underlying intermediate RDL pad. The barrier layer may constrain solder wetting along the sidewall of the bump structure to minimize solder bridging and other defects. In some embodiments, the intermediate RDL pads may have a relatively lower solder wettability to minimize solder defects. Characteristics of the intermediate RDL pads and the bump structures may be controlled to improve the flatness characteristics of bump structures.