Integrated circuit device and packaging assembly

Abstract

The invention discloses an integrated circuit device and a packaging assembly. The integrated circuit device comprises a semiconductor substrate; a first bump bottom metal layer formed on the semiconductor substrate; a second bump bottom metal layer formed on the first bump bottom metal layer and equipped with a side surface; a conductive column formed on the second bump metal layer and equipped with a side surface and a top surface and a protection structure formed on the side surfaces of the conductive column and the second bump bottom metal layer. The protective structure is made of non-metallic material and the conductive column is formed of a copper-containing layer. The protection technology for the sidewall of copper stud bumps is adopted by the invention, wherein the side surface of a copper stud bump is equipped with a protective structure formed by at least one non-metallic material film layer selected from a dielectric material layer, a polymer layer or the combination of the above layers. According to the invention, the stress force on a substrate can be adjusted and the solder wetting condition of surrounding copper studs is avoided.

Description

technical field [0001] The present invention relates to integrated circuit fabrication, and more particularly to bump structures used in integrated circuit devices. Background technique [0002] Today's integrated circuits are formed from millions of devices such as transistors or capacitors. These devices are initially separated, but are then interconnected with each other to form a functional circuit. The interconnection structure generally includes horizontal interconnection such as metal wires (connection lines) and vertical interconnection such as vias and contacts. These interconnect scenarios are increasingly setting the performance and density limits of today's integrated circuits. On top of the interconnect structure, bond pads are formed and expose the surface of each chip. The pads can be used to form an electrical connection between the chip and the substrate or another chip. The bonding pads can be used for bonding situations such as wire bonding or flip-chi...

AI Technical Summary

Problems solved by technology

Therefore, a sidewall protection layer is required to avoid oxidation of copper, but known methods for fabricating copper pillar sidewalls suffer from high manufacturing cost and interface peeling.

At present, the immersion tin process is used to form a tin layer on the sidewall of the copper pillar. However, the above-mentioned technology still has problems related to manufacturing cost, adhesion between tin and primer, and solder wetting on the sidewall. , the above problems are a major challenge for the fine-pitch packaging technology in the new generation of chips

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