33 results about "Solder interconnect" patented technology

A package comprising a first substrate, a first integrated device coupled to the first substrate, a second substrate coupled to the first substrate through a first plurality of solder interconnects such that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate includes a first surface and a second surface, an electrical device coupled to a second surface of the second substrate such that the electrical device is located between the first substrate and the second substrate, and an encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the electrical device.

A package, the package comprising: an integrated device; and a substrate coupled to the integrated device through at least a plurality of solder interconnects. The substrate includes: at least one dielectric layer; a frame at least partially located in the at least one dielectric layer; and a plurality of interconnects at least partially located in the at least one dielectric layer. The frame may be an embedded frame.

A package comprising: a package substrate; a first integrated device bonded to the package substrate through a plurality of first solder interconnects; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnects located within the sealing layer; a metallization portion bonded to the plurality of post interconnects; a second integrated device bonded to the metallization portion through a plurality of second solder interconnects; an optical integrated device bonded to the package substrate; and an optical fiber bonded to the optical integrated device.

A package comprising a substrate comprising at least one dielectric layer and a plurality of interconnects; a first integrated device coupled to the substrate through a first plurality of solder interconnects, wherein the first plurality of solder interconnects includes a first plurality of inner solder interconnects and a first plurality of perimeter solder interconnects; and a second integrated device coupled to the substrate through a second plurality of solder interconnects. The first integrated device is configured to be electrically coupled to the second integrated device through an electrical path. The electrical path comprises an inner solder interconnect from the first plurality of inner solder interconnects, at least one interconnect from the plurality of interconnects, and a solder interconnect from the second plurality of solder interconnects.

A package includes: a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of pillar interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of pillar interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

In one embodiment, a device includes (i) a first device portion including: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects located at least in the first encapsulation layer; (ii) a second device portion comprising: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects at least in the second encapsulation layer; and (iii) a first plurality of solder interconnects coupled to the first device portion and the second device portion, where the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects, and the second plurality of via interconnects are configured to operate as inductors.

A package comprising: a package substrate; a first integrated device coupled to the package substrate via a plurality of first solder interconnects; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnects at least partially located within the sealing layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion via a plurality of second solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

Modularized construction of a structure is used for a multi-die integration package. Segregation of complex devices into substructures (sub-modules) are tested and verified as functional before final reconstitution into the multi-die integration package. The thermal coefficient of sub-modules can be fine-tuned for low chip module warpage. The sub-modules can be made with a glass interposer tuned with a certain coefficient of thermal expansion (GTE) and modulus to provide favorable warpage performance. Solder interconnects at high stress locations may be used to further reduce via and polyimide (PI) stresses. A minimal redistributed layer (RDL) comprising conductive metal patterns with a plurality of metal contacts thereon is formed on a polyimide (PI) or glass carrier and electrically interconnects the sub-modules together.

An integrated device (e.g., flip chip) (100) includes a die portion (102) including a plurality of pads (107a, 107b) and a plurality of under bump metallization interconnects (109a, 109b) coupled to the plurality of pads (107a, 107b); and a plurality of pillar interconnects (104a, 104b) including a first pillar interconnect (104a) including a first cavity (209) and a second pillar interconnect (104b) including a second cavity (209). The cavity (209) can extend partially through a height of the pillar interconnect (104a, 104b). A planar cross-section of the cavity (209) extending through the pillar interconnect (104a, 104b) can include an O-shape. A plurality of solder interconnects (106a, 106b) can be coupled to the plurality of pillar interconnects (104a, 104b) and can include a solder interconnect (106a, 106b) located in the cavity (209) of the pillar interconnect (104a, 104b). The pillar interconnect (104a, 104b) can include a first pillar interconnect portion (204) including a first width and a second pillar interconnect portion (206) including a second width different from (e.g., smaller than) the first width, where the cavity (209) of the pillar interconnect (104a, 104b) can be located in the second pillar interconnect portion (206). The pillar interconnect (104a, 104b) can include a shape of a top hat. A method (700) for manufacturing an integrated device (100) can include providing a die portion (102) and forming a plurality of pillar interconnects (104). Forming the plurality of pillar interconnects (104) can include forming and patterning a first photoresist layer (600) over the die portion (102); forming a first pillar interconnect portion (602) (e.g., ring-shaped); removing the first photoresist layer (600); forming and patterning a second photoresist layer (610) (e.g., having a circular pattern with a diameter between an inner diameter and an outer diameter of the ring-shaped first interconnect portion (602)) over the die portion (102); and forming a second pillar interconnect portion over the first pillar interconnect portion (602) such that a first cavity (209) is formed in the second pillar interconnect portion. Forming the plurality of pillar interconnects (104) can also include forming a solder interconnect (106) over the cavity (209) of the pillar interconnect (104). The second photoresist layer (610) can be removed after forming the first solder interconnect (106). Portions of the under bump metallization layer (109) can then be removed, and the plurality of solder interconnects (106) can be reflowed. A package (400) includes a substrate (402) and an integrated device (100) coupled to the substrate (402) by a plurality of pillar interconnects (104a, 104b) and a plurality of solder interconnects (106a, 106b).The solder interconnects (106a, 106b) can include intermetallic compounds (IMCs) (406a, 406b) that can be formed when metals from the substrate interconnects (422a, 422b) and / or the post interconnects (104a, 104b) diffuse in the solder interconnects (106a, 106b) upon a solder reflow process used to couple the integrated device (100) to the substrate (402). The cavities (209) allow more surface area of the solder interconnects (106a, 106b) to couple, providing a more robust and reliable bond between the integrated device (100) and the substrate (402). The cavities (209) also allow more solder interconnects (106a, 106b) to be located between the post interconnects (104a, 104b) and the substrate (402) without causing shorts between adjacent interconnects (104a, 104b) of the substrate (402).

Modularized construction of a structure is used for a multi-die integration package. Segregation of complex devices into substructures (sub-modules) are tested and verified as functional before final reconstitution into the multi-die integration package. The thermal coefficient of sub-modules can be fine-tuned for low chip module warpage. The sub-modules can be made with a glass interposer tuned with a certain coefficient of thermal expansion (CTE) and modulus to provide favorable warpage performance. Solder interconnects at high stress locations may be used to further reduce via and polyimide (PI) stresses. A minimal redistributed layer (RDL) comprising conductive metal patterns with a plurality of metal contacts thereon is formed on a polyimide (PI) or glass carrier and electrically interconnects the sub-modules together.

A package comprising a first substrate; an integrated device coupled to the first substrate, wherein the integrated device comprises a plurality of back side metallization interconnects; and a second substrate coupled to the first substrate through a first plurality of solder interconnects, wherein the second substrate is coupled to the plurality of back side metallization interconnects through the second plurality of solder interconnects.

A package comprising a first substrate, a first integrated device coupled to the first substrate, and a second substrate, and a plurality of solder interconnects coupled to the first substrate and the second substrate. The first substrate comprises at least one first dielectric layer; a first plurality of interconnects, wherein the first plurality of interconnects include a first plurality of post interconnects; and a first solder resist layer coupled to a first surface of the first substrate. The second substrate comprises a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects comprises a second plurality of post interconnects; and a second solder resist layer coupled to the second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer includes a cavity.

The invention relates to the technical field of solar cell manufacturing, in particular to a space silicon solar cell and a solar cell array, which comprise a silicon-based solar cell piece and a metalized interconnection electrode, the metalized interconnection electrodes are symmetrically arranged on the front face and the back face of the silicon-based solar cell piece, a plurality of metalized interconnection electrodes are arranged on each face, and the cross section of each metalized interconnection electrode is in a trapezoid shape. And one surface, far away from the silicon-based solar cell, of the section serves as a welding surface and is used for being connected with an interconnection welding strip. According to the space silicon solar cell and the cell array thereof provided by the invention, by adopting the trapezoidal metallization interconnection electrodes, a full-penetration lamination welding interconnection mode and an optimized packaging structure design, the reliability of the solar cell array in a space extreme environment is remarkably improved on the premise that the photoelectric conversion efficiency is maintained; and meanwhile, the cost is effectively reduced.

A microelectronic assembly is provided, comprising: a first IC die coupled to a surface with first interconnects having a first pitch; and a second IC die coupled to the surface with second interconnects having a second pitch. The second pitch is greater than the first pitch, and the first pitch is less than 10 micrometers. In another embodiment, a microelectronic assembly is provided, comprising: a first stack coupled to a surface, the first stack comprising a first number of IC dies; and a second stack coupled to the surface, the second stack comprising a second number of IC dies, in which: the first stack and the second stack are laterally surrounded by a dielectric, the first stack and the second stack have a same thickness, and the first number is less than the second number.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die surrounded by an insulating material, the die having a first conductive contact at a first surface and a second conductive contact at a second surface opposite the first surface, a first redistribution layer (RDL), on the first surface of the die, including a first conductive pathway through a first dielectric material electrically coupled to the first conductive contact of the die by a first solderless metal-metal interconnect; and a second RDL, on second surface of the die, including a second conductive pathway through a second dielectric material electrically coupled to the second conductive contact of the die by a second solderless metal-metal interconnect, wherein a thickness of the die is between 20 microns and 45 microns. In some embodiments, a thickness of the die is between 60 microns and 75 microns.

A package comprising a substrate, an integrated device coupled to a first surface of the substrate through at least a first plurality of solder interconnects; and an antenna device coupled to a second surface of the substrate through at least a second plurality of solder interconnects. The antenna device comprises an antenna device dielectric layer; at least one antenna located on a first surface of the antenna device dielectric layer; a shield located on at least one lateral surface of the antenna device; and a slot opening on the first surface of the antenna device.

A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; a first encapsulation layer at least partially encapsulating the first integrated device; a plurality of through molding encapsulation layer via interconnects located in the first encapsulation layer; wherein the plurality of through molding encapsulation layer via interconnects are configured to provide an electrical path for ground; a seed layer coupled to and touching the first encapsulation layer, the plurality of through molding encapsulation layer via interconnects and a back side of the first integrated device; and a first heat sink coupled to the seed layer.

A package comprising an integrated device and a substrate coupled to the integrated device through a plurality of solder interconnects. The integrated device comprises a die substrate; a die interconnection portion coupled to the die substrate; a plurality of pad interconnects coupled to the die interconnection portion; a plurality of pillar interconnects coupled to the plurality of pad interconnects; and a plurality of interconnects coupled to the plurality of pillar interconnects, wherein at least one pad interconnect from the plurality of pad interconnects, at least one pillar interconnects from the plurality of pillar interconnects and at least one interconnect from the plurality of interconnects are configured as an inductor.

A package, the package comprising: a substrate; an integrated device coupled to the first surface of the substrate through at least a first plurality of solder interconnects; and an antenna device coupled to the second surface of the substrate through at least a second plurality of solder interconnects. The antenna device includes: an antenna device dielectric layer; at least one antenna located on the first surface of the antenna device dielectric layer; a shield on at least one lateral surface of the antenna device; and a slot on the first surface of the antenna device.

A package, the package comprising an interposer, the interposer comprising: a silicon substrate, the silicon substrate comprising a porous portion; and a plurality of via interconnects extending through the porous portion of the silicon substrate. The package includes a first integrated device coupled to an interposer through a first plurality of solder interconnects.

A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device, wherein the encapsulation layer includes a cavity; a metallization portion coupled to the first integrated device; and a first passive device coupled to the metallization portion through at least a second plurality of solder interconnects, wherein the first passive device is located at least partially in the cavity of the encapsulation layer.

A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

Microelectronic assemblies, related apparatus, and methods are disclosed. In some embodiments, a microelectronic assembly can include a wafer surrounded by an insulating material, the wafer having a first conductive contact at a first surface and a second conductive contact at a second surface opposite the first surface; a first redistribution layer (RDL) on the first surface of the wafer including a first conductive path electrically coupled to the first conductive contact of the wafer by a first dielectric material through a first solderless metal-metal interconnect; and a second RDL on the second surface of the wafer including a second conductive path electrically coupled to the second conductive contact of the wafer by a second dielectric material through a second solderless metal-metal interconnect, wherein a thickness of the wafer is between 20 microns and 45 microns. In some embodiments, the thickness of the wafer is between 60 microns and 75 microns.

A package comprising a first substrate; an integrated device coupled to the first substrate, wherein the integrated device comprises a plurality of back side metallization interconnects; and a second substrate coupled to the first substrate through a first plurality of solder interconnects, wherein the second substrate is coupled to the plurality of back side metallization interconnects through the second plurality of solder interconnects.

The present invention relates to the technical field of new energy vehicles, and provides a power module, a power conversion device, and an electric vehicle. The power module comprises a substrate, at least one power chip, a heat dissipation base plate, and a soldering layer; the at least one power chip is located on the surface of the substrate; the surface of the substrate facing away from the power chip and / or the surface of the heat dissipation base plate is provided with a crack-retarding structure; the surface of the substrate facing away from the power chip and the surface of the heat dissipation base plate are interconnected by means of the soldering layer, and the crack-retarding structure is located in the soldering layer; an outer edge of the orthographic projection of the crack-retarding structure on the surface of the substrate facing away from the power chip surrounds all the power chips; and a gap between the opposing surfaces of the substrate and the heat dissipation base plate in an area having the crack-retarding structure is unequal to that in an area without the crack-retarding structure. By using the present invention, the long-term reliability and stability of soldering-based interconnection can be improved.

A package comprising an integrated device and a substrate coupled to the integrated device through a plurality of solder interconnects. The integrated device comprises a die substrate; a die interconnection portion coupled to the die substrate; a plurality of pad interconnects coupled to the die interconnection portion; a plurality of pillar interconnects coupled to the plurality of pad interconnects; and a plurality of interconnects coupled to the plurality of pillar interconnects, wherein at least one pad interconnect from the plurality of pad interconnects, at least one pillar interconnects from the plurality of pillar interconnects and at least one interconnect from the plurality of interconnects are configured as an inductor.

Multi-die packages including a glass substrate within a space between adjacent IC dies. Two or more IC die may be placed within recesses formed in a glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. Organic package dielectric material may then be built up on both sides of the IC dies and glass substrate. Metallization features formed within package dielectric material built up on a first side of the IC die may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects. Metallization features formed within package dielectric material built up on a second side of the first and second IC dies may electrically interconnect the first IC die to the second IC die.

An embodiment of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace parallel to the first and second surfaces, and the conductive trace exposed at the third surface; and a second IC die including a fourth surface, where the fourth surface of the second IC die is electrically coupled to the third surface of the first IC die through an interconnect including solder.

This disclosure provides a power module, a power conversion device, and an electric vehicle, belonging to the field of new energy vehicle technology. The power module includes a substrate, at least one power chip, a heat sink, and a solder layer. The at least one power chip is located on the surface of the substrate. The surface of the substrate facing away from the power chip and / or the surface of the heat sink have a crack-resistant structure. The surface of the substrate facing away from the power chip and the surface of the heat sink are interconnected through the solder layer, and the crack-resistant structure is located within the solder layer. The outer edge of the crack-resistant structure's orthographic projection on the surface of the substrate facing away from the power chip surrounds all the power chips. The spacing between the facing surfaces of the substrate and the heat sink is not equal in the region with the crack-resistant structure compared to the region without it. Adopting this disclosure can improve the long-term reliability and stability of post-soldering interconnects.