59 results about "Solder interconnect" patented technology

A device comprising a board; a first package coupled to the board through a plurality of solder interconnects, wherein the first package comprises: a first substrate; a first integrated device coupled to the first substrate; a heat pipe coupled to the first integrated device through a thermal interface material; a second package coupled to the first substrate through a through a plurality of inter substrate interconnects; and an encapsulation layer located between the first substrate and the second package.

A package comprising a first substrate, a first integrated device coupled to the first substrate, a second substrate coupled to the first substrate through a first plurality of solder interconnects such that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate includes a first surface and a second surface, an electrical device coupled to a second surface of the second substrate such that the electrical device is located between the first substrate and the second substrate, and an encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the electrical device.

A package, the package comprising: an integrated device; and a substrate coupled to the integrated device through at least a plurality of solder interconnects. The substrate includes: at least one dielectric layer; a frame at least partially located in the at least one dielectric layer; and a plurality of interconnects at least partially located in the at least one dielectric layer. The frame may be an embedded frame.

A package comprising: a package substrate; a first integrated device bonded to the package substrate through a plurality of first solder interconnects; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnects located within the sealing layer; a metallization portion bonded to the plurality of post interconnects; a second integrated device bonded to the metallization portion through a plurality of second solder interconnects; an optical integrated device bonded to the package substrate; and an optical fiber bonded to the optical integrated device.

A package comprising a substrate comprising at least one dielectric layer and a plurality of interconnects; a first integrated device coupled to the substrate through a first plurality of solder interconnects, wherein the first plurality of solder interconnects includes a first plurality of inner solder interconnects and a first plurality of perimeter solder interconnects; and a second integrated device coupled to the substrate through a second plurality of solder interconnects. The first integrated device is configured to be electrically coupled to the second integrated device through an electrical path. The electrical path comprises an inner solder interconnect from the first plurality of inner solder interconnects, at least one interconnect from the plurality of interconnects, and a solder interconnect from the second plurality of solder interconnects.

A package comprising a substrate; and a passive device coupled to the substrate through at least a first plurality of solder interconnects. The passive device comprises a trench capacitor device; an encapsulation layer; and a metallization portion coupled to the trench capacitor device and the encapsulation layer.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

A package includes: a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of pillar interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of pillar interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

In one embodiment, a device includes (i) a first device portion including: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects located at least in the first encapsulation layer; (ii) a second device portion comprising: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects at least in the second encapsulation layer; and (iii) a first plurality of solder interconnects coupled to the first device portion and the second device portion, where the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects, and the second plurality of via interconnects are configured to operate as inductors.

A package comprising: a package substrate; a first integrated device coupled to the package substrate via a plurality of first solder interconnects; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnects at least partially located within the sealing layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion via a plurality of second solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

A package includes a package substrate and a first integrated device coupled to the package substrate by a first plurality of solder interconnects. The package substrate includes a bridge and / or interposer, an encapsulation portion, a first metallization portion coupled to a first surface of the encapsulation portion, and a second metallization portion coupled to a second surface of the encapsulation portion. The encapsulation portion includes a first interconnect portion block, a second interconnect portion block, a plurality of pillar interconnects, and an encapsulation layer encapsulating the first interconnect portion block, the second interconnect portion block, and the plurality of pillar interconnects. The plurality of pillar interconnects includes a first plurality of pillar interconnects coupled to the first interconnect portion block and a second plurality of pillar interconnects coupled to the second interconnect portion block.

Modularized construction of a structure is used for a multi-die integration package. Segregation of complex devices into substructures (sub-modules) are tested and verified as functional before final reconstitution into the multi-die integration package. The thermal coefficient of sub-modules can be fine-tuned for low chip module warpage. The sub-modules can be made with a glass interposer tuned with a certain coefficient of thermal expansion (GTE) and modulus to provide favorable warpage performance. Solder interconnects at high stress locations may be used to further reduce via and polyimide (PI) stresses. A minimal redistributed layer (RDL) comprising conductive metal patterns with a plurality of metal contacts thereon is formed on a polyimide (PI) or glass carrier and electrically interconnects the sub-modules together.

The application discloses a flip chip preparation method and a flip chip, and belongs to the flip chip technical field. The flip chip preparation method provided by the application forms a first interconnection element on a first substrate, forms a first sub-interconnection element on a first surface of an intermediate substrate and forms a second sub-interconnection element and an action surface limiting element on a second surface of the intermediate substrate, and the height of the second sub-interconnection element is not higher than that of the action surface limiting element; a second interconnection element is formed on a second substrate; and when the first surface of the intermediate substrate is welded and interconnected with the first substrate, since the height of the second sub-interconnection element is not higher than that of the action surface limiting element, the action surface limiting element can bear the pressure applied in the flip welding process, which helps to avoid the circuit structure on the second surface from being damaged or destroyed due to the pressure.

An integrated device (e.g., flip chip) (100) includes a die portion (102) including a plurality of pads (107a, 107b) and a plurality of under bump metallization interconnects (109a, 109b) coupled to the plurality of pads (107a, 107b); and a plurality of pillar interconnects (104a, 104b) including a first pillar interconnect (104a) including a first cavity (209) and a second pillar interconnect (104b) including a second cavity (209). The cavity (209) can extend partially through a height of the pillar interconnect (104a, 104b). A planar cross-section of the cavity (209) extending through the pillar interconnect (104a, 104b) can include an O-shape. A plurality of solder interconnects (106a, 106b) can be coupled to the plurality of pillar interconnects (104a, 104b) and can include a solder interconnect (106a, 106b) located in the cavity (209) of the pillar interconnect (104a, 104b). The pillar interconnect (104a, 104b) can include a first pillar interconnect portion (204) including a first width and a second pillar interconnect portion (206) including a second width different from (e.g., smaller than) the first width, where the cavity (209) of the pillar interconnect (104a, 104b) can be located in the second pillar interconnect portion (206). The pillar interconnect (104a, 104b) can include a shape of a top hat. A method (700) for manufacturing an integrated device (100) can include providing a die portion (102) and forming a plurality of pillar interconnects (104). Forming the plurality of pillar interconnects (104) can include forming and patterning a first photoresist layer (600) over the die portion (102); forming a first pillar interconnect portion (602) (e.g., ring-shaped); removing the first photoresist layer (600); forming and patterning a second photoresist layer (610) (e.g., having a circular pattern with a diameter between an inner diameter and an outer diameter of the ring-shaped first interconnect portion (602)) over the die portion (102); and forming a second pillar interconnect portion over the first pillar interconnect portion (602) such that a first cavity (209) is formed in the second pillar interconnect portion. Forming the plurality of pillar interconnects (104) can also include forming a solder interconnect (106) over the cavity (209) of the pillar interconnect (104). The second photoresist layer (610) can be removed after forming the first solder interconnect (106). Portions of the under bump metallization layer (109) can then be removed, and the plurality of solder interconnects (106) can be reflowed. A package (400) includes a substrate (402) and an integrated device (100) coupled to the substrate (402) by a plurality of pillar interconnects (104a, 104b) and a plurality of solder interconnects (106a, 106b).The solder interconnects (106a, 106b) can include intermetallic compounds (IMCs) (406a, 406b) that can be formed when metals from the substrate interconnects (422a, 422b) and / or the post interconnects (104a, 104b) diffuse in the solder interconnects (106a, 106b) upon a solder reflow process used to couple the integrated device (100) to the substrate (402). The cavities (209) allow more surface area of the solder interconnects (106a, 106b) to couple, providing a more robust and reliable bond between the integrated device (100) and the substrate (402). The cavities (209) also allow more solder interconnects (106a, 106b) to be located between the post interconnects (104a, 104b) and the substrate (402) without causing shorts between adjacent interconnects (104a, 104b) of the substrate (402).

Modularized construction of a structure is used for a multi-die integration package. Segregation of complex devices into substructures (sub-modules) are tested and verified as functional before final reconstitution into the multi-die integration package. The thermal coefficient of sub-modules can be fine-tuned for low chip module warpage. The sub-modules can be made with a glass interposer tuned with a certain coefficient of thermal expansion (CTE) and modulus to provide favorable warpage performance. Solder interconnects at high stress locations may be used to further reduce via and polyimide (PI) stresses. A minimal redistributed layer (RDL) comprising conductive metal patterns with a plurality of metal contacts thereon is formed on a polyimide (PI) or glass carrier and electrically interconnects the sub-modules together.

A package comprising a first substrate; an integrated device coupled to the first substrate, wherein the integrated device comprises a plurality of back side metallization interconnects; and a second substrate coupled to the first substrate through a first plurality of solder interconnects, wherein the second substrate is coupled to the plurality of back side metallization interconnects through the second plurality of solder interconnects.

A package includes: a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of pillar interconnects in the encapsulation layer; a metallization portion coupled to the plurality of pillar interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

A package comprising a first substrate; an integrated device coupled to the substrate; a second substrate coupled to the first substrate through at least a plurality of solder interconnects, wherein the second substrate is located over a portion of the integrated device; and a heat sink coupled to a back side of the integrated device through a thermal interface material, wherein the heat sink is located over another portion of the integrated device, wherein the heat sink is located laterally to the second substrate.

A package comprising a first substrate, a first integrated device coupled to the first substrate, and a second substrate, and a plurality of solder interconnects coupled to the first substrate and the second substrate. The first substrate comprises at least one first dielectric layer; a first plurality of interconnects, wherein the first plurality of interconnects include a first plurality of post interconnects; and a first solder resist layer coupled to a first surface of the first substrate. The second substrate comprises a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects comprises a second plurality of post interconnects; and a second solder resist layer coupled to the second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer includes a cavity.

The invention relates to the technical field of solar cell manufacturing, in particular to a space silicon solar cell and a solar cell array, which comprise a silicon-based solar cell piece and a metalized interconnection electrode, the metalized interconnection electrodes are symmetrically arranged on the front face and the back face of the silicon-based solar cell piece, a plurality of metalized interconnection electrodes are arranged on each face, and the cross section of each metalized interconnection electrode is in a trapezoid shape. And one surface, far away from the silicon-based solar cell, of the section serves as a welding surface and is used for being connected with an interconnection welding strip. According to the space silicon solar cell and the cell array thereof provided by the invention, by adopting the trapezoidal metallization interconnection electrodes, a full-penetration lamination welding interconnection mode and an optimized packaging structure design, the reliability of the solar cell array in a space extreme environment is remarkably improved on the premise that the photoelectric conversion efficiency is maintained; and meanwhile, the cost is effectively reduced.

A computer apparatus includes a hierarchy of solder joints in a multi-chip package, with solder joints at different levels of the packaging having different melting temperatures. Interconnections, such as pads or pins, on integrated circuit (IC) die can be electrically coupled to ends of contact pillars with solder joints having a higher melting temperature. The other ends of the contact pillars can electrically couple to another substrate or another device with solder joints having a lower melting temperature. The contact pillars can be, for example, a contact array or through-hole via in a substrate.

A microelectronic assembly is provided, comprising: a first IC die coupled to a surface with first interconnects having a first pitch; and a second IC die coupled to the surface with second interconnects having a second pitch. The second pitch is greater than the first pitch, and the first pitch is less than 10 micrometers. In another embodiment, a microelectronic assembly is provided, comprising: a first stack coupled to a surface, the first stack comprising a first number of IC dies; and a second stack coupled to the surface, the second stack comprising a second number of IC dies, in which: the first stack and the second stack are laterally surrounded by a dielectric, the first stack and the second stack have a same thickness, and the first number is less than the second number.

The invention provides improved techniques for bonding copper to solder or other types of flip chip devices using a passivation coating on copper. The surface of a substrate is cleaned prior to mounting a flip chip device onto the substrate. The substrate is rinsed to remove residual artifacts remaining on the surface subsequent to the cleaning. Subsequent to the rinsing, a protective coating is applied to the surface of the substrate to produce a coated substrate. Copper pillars with solder caps extending from the flip chip device are bonded to metallic features on the surface of the coated substrate.

The invention provides a low-temperature welding interconnection assembly, a welding structure and a preparation method of the low-temperature welding interconnection assembly. The low-temperature welding interconnection assembly comprises a metal bonding pad; the nano particle modified SnBi soldering paste layer is arranged on one side of the metal bonding pad in a laminated mode, and the nano particle modified SnBi soldering paste layer comprises nano particles and SnBi soldering paste; and the SnPb solder ball is adjacent to one side, far away from the metal bonding pad, of the nano particle modified SnBi solder paste layer. The low-temperature welding interconnection assembly is excellent in mechanical performance and good in thermal fatigue resistance at the room temperature, and the hardness, the yield strength, the shear strength, the toughness and the creep resistance are all higher than those of SnPb solder.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die surrounded by an insulating material, the die having a first conductive contact at a first surface and a second conductive contact at a second surface opposite the first surface, a first redistribution layer (RDL), on the first surface of the die, including a first conductive pathway through a first dielectric material electrically coupled to the first conductive contact of the die by a first solderless metal-metal interconnect; and a second RDL, on second surface of the die, including a second conductive pathway through a second dielectric material electrically coupled to the second conductive contact of the die by a second solderless metal-metal interconnect, wherein a thickness of the die is between 20 microns and 45 microns. In some embodiments, a thickness of the die is between 60 microns and 75 microns.

A package comprising a substrate, an integrated device coupled to a first surface of the substrate through at least a first plurality of solder interconnects; and an antenna device coupled to a second surface of the substrate through at least a second plurality of solder interconnects. The antenna device comprises an antenna device dielectric layer; at least one antenna located on a first surface of the antenna device dielectric layer; a shield located on at least one lateral surface of the antenna device; and a slot opening on the first surface of the antenna device.

The invention provides a semiconductor device and a method for forming the semiconductor device. The method includes: providing a semiconductor package, the semiconductor package including a plurality of contact pads formed on a surface of the semiconductor package; providing a template with a plurality of openings; disposing the template on a surface of the semiconductor package, wherein the plurality of openings are respectively aligned with the plurality of contact pads; forming a plurality of solder bumps on the plurality of contact pads and in the plurality of openings, respectively; and irradiating the plurality of solder bumps with a homogenized laser beam to form a solder interconnect between each of the plurality of solder bumps and a respective one of the plurality of contact pads.

The invention relates to the technical field of electronic packaging, in particular to a copper powder-liquid gallium composite low-temperature metal solder and a preparation method and welding application thereof.The copper powder-liquid gallium composite low-temperature metal solder is composed of, by weight, 60-90% of liquid gallium, 10-40% of copper powder, an accelerant and a process additive, and the accelerant and the process additive are both optional components. When welding interconnection needs to be carried out, welding flux is applied to the back face of a metalized substrate or a chip, the chip is mounted, heat preservation is carried out for 10-240 min under the inert or reducing atmosphere at the temperature of 30-260 DEG C and the pressure of 1-5 MPa, and a Cu-Ga intermetallic compound is generated on an interface / bulk phase in situ, and a compact welding seam is formed. Through verification, the solder can generate a stable intermetallic compound and a communication metal network in situ in the assembly process so as to improve the shear strength and the long-term reliability, and meanwhile, the material cost, the manufacturing process cost, the manufacturability and the consistency are considered.