125 results about "Solder interconnect" patented technology

Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace that is parallel to the first and second surfaces, and the conductive trace is exposed at the third surface; and a second IC die including a fourth surface, wherein the fourth surface of the second IC die is electrically coupled to the third surface of the first IC die by an interconnect including solder.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

A method for normalizing the solder interconnects (e.g., normalizing the height of the solder ball interconnects) in a circuit package module (e.g., dual-sided mold grid array package module) after removal from a test board includes receiving in a fixture the circuit package module upside down and removably coupling a stencil to the fixture and over the circuit package module. The stencil has a pattern of apertures that coincides with the pattern of solder interconnects of the circuit package module. The method also includes applying solder paste over the stencil to pass through the apertures to add solder paste to the solder interconnects. The method also includes removing the stencil from over the fixture, and removing the circuit package module from the fixture. The circuit package module can be heated to reflow the solder interconnects with the added solder paste.

A package comprising a first substrate; a first integrated device coupled to the first substrate through at least a first plurality of solder interconnects, wherein the first integrated device comprises a plurality of through substrate vias; an interconnection device coupled to a back side of the first integrated device through a second plurality of solder interconnects; a second substrate coupled to the first substrate through at least a third plurality of solder interconnects; and a second integrated device coupled to the second substrate and the interconnection device.

A device comprising a board; a first package coupled to the board through a plurality of solder interconnects, wherein the first package comprises: a first substrate; a first integrated device coupled to the first substrate; a heat pipe coupled to the first integrated device through a thermal interface material; a second package coupled to the first substrate through a through a plurality of inter substrate interconnects; and an encapsulation layer located between the first substrate and the second package.

A package comprising a first substrate, a first integrated device coupled to the first substrate, a second substrate coupled to the first substrate through a first plurality of solder interconnects such that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate includes a first surface and a second surface, an electrical device coupled to a second surface of the second substrate such that the electrical device is located between the first substrate and the second substrate, and an encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the electrical device.

A package, the package comprising: an integrated device; and a substrate coupled to the integrated device through at least a plurality of solder interconnects. The substrate includes: at least one dielectric layer; a frame at least partially located in the at least one dielectric layer; and a plurality of interconnects at least partially located in the at least one dielectric layer. The frame may be an embedded frame.

The subject matter of the invention is "microelectronic components including solder and non-solder interconnects". Microelectronic assemblies, related devices and methods are disclosed herein. In some embodiments, a microelectronic component may include a first die in a first layer, the first die having a first surface and an opposing second surface; a redistribution layer (RDL) on the first layer, wherein the RDL is electrically coupled to a second surface of the first die through a solder interconnect; and a second die in the second layer on the RDL, wherein the second die is electrically coupled to the RDL by a non-solder interconnect.

Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace that is parallel to the first and second surfaces, and the conductive trace is exposed at the third surface; and a second IC die including a fourth surface, wherein the fourth surface of the second IC die is electrically coupled to the third surface of the first IC die by an interconnect including solder.

A package comprising: a package substrate; a first integrated device bonded to the package substrate through a plurality of first solder interconnects; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnects located within the sealing layer; a metallization portion bonded to the plurality of post interconnects; a second integrated device bonded to the metallization portion through a plurality of second solder interconnects; an optical integrated device bonded to the package substrate; and an optical fiber bonded to the optical integrated device.

A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

A package comprising a substrate comprising at least one dielectric layer and a plurality of interconnects; a first integrated device coupled to the substrate through a first plurality of solder interconnects, wherein the first plurality of solder interconnects includes a first plurality of inner solder interconnects and a first plurality of perimeter solder interconnects; and a second integrated device coupled to the substrate through a second plurality of solder interconnects. The first integrated device is configured to be electrically coupled to the second integrated device through an electrical path. The electrical path comprises an inner solder interconnect from the first plurality of inner solder interconnects, at least one interconnect from the plurality of interconnects, and a solder interconnect from the second plurality of solder interconnects.

A package comprising a first substrate; an integrated device coupled to the first substrate through at least a first plurality of solder interconnects; an inter substrate interconnect structure coupled to the first substrate through at least a second plurality of solder interconnects. The inter substrate interconnect structure comprises an inner interconnect; a dielectric layer coupled to the inner interconnect; and an interconnect coupled to the dielectric layer, wherein the interconnect surrounds the dielectric layer and the inner interconnect; a second substrate coupled to the inter substrate interconnect structure through at least a third plurality of solder interconnects; and an encapsulation layer coupled to the first substrate and the second substrate.

A package comprising a substrate; and a passive device coupled to the substrate through at least a first plurality of solder interconnects. The passive device comprises a trench capacitor device; an encapsulation layer; and a metallization portion coupled to the trench capacitor device and the encapsulation layer.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

A package includes: a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of pillar interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of pillar interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

In one embodiment, a device includes (i) a first device portion including: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects located at least in the first encapsulation layer; (ii) a second device portion comprising: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects at least in the second encapsulation layer; and (iii) a first plurality of solder interconnects coupled to the first device portion and the second device portion, where the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects, and the second plurality of via interconnects are configured to operate as inductors.

A package comprising: a package substrate; a first integrated device coupled to the package substrate via a plurality of first solder interconnects; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnects at least partially located within the sealing layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion via a plurality of second solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

A package comprising a substrate, an integrated device coupled to a first surface of the substrate through at least a first plurality of solder interconnects; and an antenna device coupled to a second surface of the substrate through at least a second plurality of solder interconnects. The antenna device comprises an antenna device dielectric layer; at least one antenna located on a first surface of the antenna device dielectric layer; a shield located on at least one lateral surface of the antenna device; and a slot opening on the first surface of the antenna device.

A package comprising a substrate comprising a first surface and a second surface, wherein the substrate further comprises: at least one dielectric layer; and a plurality of interconnects; an integrated device coupled to the first surface of the substrate through at least a first plurality of solder interconnects; and a passive device coupled to the second surface of the substrate through at least a second plurality of solder interconnects, wherein the passive device comprises at least one through substrate via.

A package includes a package substrate and a first integrated device coupled to the package substrate by a first plurality of solder interconnects. The package substrate includes a bridge and / or interposer, an encapsulation portion, a first metallization portion coupled to a first surface of the encapsulation portion, and a second metallization portion coupled to a second surface of the encapsulation portion. The encapsulation portion includes a first interconnect portion block, a second interconnect portion block, a plurality of pillar interconnects, and an encapsulation layer encapsulating the first interconnect portion block, the second interconnect portion block, and the plurality of pillar interconnects. The plurality of pillar interconnects includes a first plurality of pillar interconnects coupled to the first interconnect portion block and a second plurality of pillar interconnects coupled to the second interconnect portion block.

A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; a second integrated device coupled to the substrate through at least a second plurality of solder interconnects; and a bridge coupled to the substrate, wherein the bridge comprises a plurality of spring pads.

Modularized construction of a structure is used for a multi-die integration package. Segregation of complex devices into substructures (sub-modules) are tested and verified as functional before final reconstitution into the multi-die integration package. The thermal coefficient of sub-modules can be fine-tuned for low chip module warpage. The sub-modules can be made with a glass interposer tuned with a certain coefficient of thermal expansion (GTE) and modulus to provide favorable warpage performance. Solder interconnects at high stress locations may be used to further reduce via and polyimide (PI) stresses. A minimal redistributed layer (RDL) comprising conductive metal patterns with a plurality of metal contacts thereon is formed on a polyimide (PI) or glass carrier and electrically interconnects the sub-modules together.

The package (100) includes a first integrated device (105) having a first plurality of interconnects (254), a plurality of solder interconnects (170a) coupled to the first plurality of interconnects (254), a second integrated device (107a) having a second plurality of interconnects (270a+272a), the second integrated device (107a) coupled to the first integrated device (105) via the second plurality of interconnects (270a+272a), the plurality of solder interconnects (170a), and the first plurality of interconnects (254), a polymer layer (192a) located between the first integrated device (105) and the second integrated device (107a), and a plurality of spacer balls (109a) located between the first integrated device (105) and the second integrated device (107a). The spacer balls (190a) help ensure that variations in the gap between the integrated devices (105, 107a) (e.g., due to tilting of one of the integrated devices (105, 107a) relative to an adjacent integrated device (105, 107a)) are reduced and / or eliminated. The polymer layer (192a) may include an adhesive layer. The spacer balls (190a) may be located at least partially within the polymer layer (192a). The spacer balls (190a) may include monodisperse particles, silica, glass, polymer, ceramic, and / or metal-containing particles, and may include polyethylene polymer particles, in particular. The package (100) may further include an underfill (204a) between the first integrated device (105) and the second integrated device (107a). The first plurality of interconnects (254) may include a first plurality of pillar interconnects, and the second integrated device is coupled to the first integrated device via the second plurality of interconnects (270a+272a), the plurality of solder interconnects (170a), and the first plurality of pillar interconnects. The second integrated device (107a) may include a second die (e.g., a first memory die), and the first integrated device (105) may include a first die (e.g., a logic die or a second memory die).The package (100) may further comprise a third integrated device (107b) having a third plurality of interconnects (270b+272b), a second polymer layer (192b) located between the third integrated device (107b) and the second integrated device (107a), and a second plurality of spacer balls (190b) located between the third integrated device (107b) and the second integrated device (107a), and the third integrated device (107b) may be coupled to the second integrated device (107a) via the third plurality of interconnects (270b+272b) and the second plurality of solder interconnects (170b), and the second integrated device (107a) may include a plurality of through-substrate vias (275a). The first plurality of interconnects (254) may include a first plurality of pillar interconnects and / or a first plurality of pad interconnects (254), and the second plurality of interconnects (270a+272a) may include a second plurality of pillar interconnects (272a) and / or a second plurality of pad interconnects (270a). The first integrated device (105) may include a third plurality of interconnects (250+252), where the first plurality of interconnects (254) is located on a first surface of the first integrated device (105) and the third plurality of interconnects (250+252) is located on a second surface of the first integrated device (105). The package (100) may comprise a substrate (104) and a stack (101) of first and second integrated devices (105, 107a) coupled to the substrate (104) via a further plurality of solder interconnects (150). The first integrated device (105) may be coupled to the second integrated device (107a) via front-to-front bonding, front-to-backside bonding, back-to-front bonding, or back-to-backside bonding.In a method of fabricating a package (100), the second plurality of pad interconnects (370), the second plurality of pillar interconnects (372), and the plurality of solder interconnects (170) are formed on a second wafer (600) including uncut second integrated devices (307a, 307b), and a plurality of spacer balls (190) and a polymer layer (192) are disposed between the uncut second integrated devices (307a, 307b), for example, in a cut region ( 504), an underfill (204) is formed on the uncut second integrated devices (307a, 307b), a first wafer (610) including the uncut first integrated devices (305a, 305b), the first plurality of pad interconnects (350), and the first plurality of pillar interconnects (352) is bonded to the second wafer (600) by a solder reflow process, and the wafers (600, 610) are cut along the cut lines (620).

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL is electrically coupled to the second surface of the first die by solder interconnects, and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by non-solder interconnects.

The application discloses a flip chip preparation method and a flip chip, and belongs to the flip chip technical field. The flip chip preparation method provided by the application forms a first interconnection element on a first substrate, forms a first sub-interconnection element on a first surface of an intermediate substrate and forms a second sub-interconnection element and an action surface limiting element on a second surface of the intermediate substrate, and the height of the second sub-interconnection element is not higher than that of the action surface limiting element; a second interconnection element is formed on a second substrate; and when the first surface of the intermediate substrate is welded and interconnected with the first substrate, since the height of the second sub-interconnection element is not higher than that of the action surface limiting element, the action surface limiting element can bear the pressure applied in the flip welding process, which helps to avoid the circuit structure on the second surface from being damaged or destroyed due to the pressure.

A package comprising an integrated device and a substrate coupled to the integrated device through a plurality of solder interconnects. The substrate comprises at least one magnetic layer, at least one dielectric layer; and a plurality of interconnects. The plurality of interconnects comprise a first set of interconnects that are configured to operate as a first inductor and a second set of interconnects that are configured to operate as a second inductor. The second inductor and the first inductor are configured to operate as inductively coupled inductors.