7results about How to "Reduce package thickness" patented technology

According to the back power supply chip packaging structure and the preparation method thereof provided by the invention, the back power supply logic chip is formed by the first semiconductor substrate, the first transistor layer, the passivation layer, the first signal wiring layer and the first power supply wiring layer, and the storage chip is stacked by using the back power supply logic chip, so that the packaging thickness is effectively reduced, and the size of the packaging structure is reduced; the back power supply logic chip and the metal columns penetrating through the interior of the first transistor layer can effectively shorten the transmission distance and reduce power consumption.

The utility model relates to the technical field of LED packaging, in particular to a side-emitting multi-color integrated LED packaging structure, which comprises a ceramic substrate provided with a common-anode RGBW chip group. The RGBW chip set is directly welded on the ceramic substrate by adopting a flip chip design, the overall thickness of the packaging structure is less than or equal to 1.2 mm, the RGBW chip set is matched with preset solder paste below the RGBW chip set to be mounted on a bonding pad, the RGBW chip set is directly welded on the ceramic substrate by adopting the flip chip design, technologies such as gold wire bonding and matching with a film pasting technology are abandoned, and the packaging structure is simple in structure, convenient to manufacture and high in packaging efficiency. The overall thickness of the packaging structure is smaller than or equal to 1.2 mm, the packaging thickness is greatly reduced, the packaging structure can perfectly adapt to ultrathin application scenes such as side-entry backlight, the problem in the aspect of ultra-thinness in the traditional technology is effectively solved, the number of bonding pads is reduced to five by adopting the design that RGBW four-in-one chips share the anode / cathode, the anodes of the RGBW chips are connected in parallel, and the thickness of the packaging structure is greatly reduced. Only one common bonding pad and four independent bonding pads are needed, and the problem that bonding pad wiring is complex in the prior art is solved.

This invention relates to a stacked optocoupler chip and its fabrication method. By providing an in-situ grown silicon dioxide insulating layer on the upper surface of the photosensitive receiving chip, the thickness of the silicon dioxide insulating layer is reduced, and only one application of adhesive is required, namely, applying insulating die bond adhesive in the die bond tank. This avoids the thickness increase caused by at least two applications of adhesive in traditional stacked solutions, namely applying insulating die bond adhesive to the bottom surface of the photoelectric emitting chip and to the bottom surface of the insulating sheet. Therefore, the overall package thickness is significantly reduced, which helps to realize smaller-sized stacked optocoupler products.

The invention provides a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure comprises the components of a substrate which is provided with a first surface and a second surface which are oppositely arranged along the thickness direction of the substrate, the first surface is provided with a groove, the substrate is also internally provided with a first via hole, and the first via hole penetrates through the first surface and the second surface and is located at the side of the groove; the first shielding layer covers the bottom wall and the side wall of the groove; the chip is arranged in the groove, the chip is provided with a pin, and the pin is electrically connected with the first via hole; and the second shielding layer covers at least part of the surface, deviating from the bottom wall of the groove, of the chip. The semiconductor packaging structure is used for achieving the effect of improving magnetic shielding comprehensiveness and storage density.

The utility model discloses a kind of packaging structures, applied to semiconductor technical field, comprising: photoelectric sensing chip and glass substrate;The upper surface of photoelectric sensing chip is provided with photosensitive area, and at least two first pads around photosensitive area;First pad surface is provided with conductive bump;Glass substrate is set on the upper surface of photoelectric sensing chip;Glass substrate lower surface is provided with rewiring layer;Rewiring layer includes at least two second pads around photosensitive area;And glass substrate is also provided with solder ball electric contact with second pad;Photoelectric sensing chip is electrically connected by conductive bump, second pad and solder ball.The utility model packaging thickness is small, heat dissipation performance is good, reliability is high, and cost is low.

The invention provides a three-dimensional packaging structure which is characterized in that the packaging structure comprises a plurality of single-layer chips which are vertically stacked and interconnected with one another; the plastic packaging material is used for carrying out coating and plastic packaging on the plurality of single-layer chips; the underfill material is filled in a connection gap between the adjacent chip layers; the single-layer chip comprises a plurality of TSV interconnection structures which comprise TSV silicon through holes and copper columns; the main chip comprises an I / O surface and a back surface opposite to the I / O surface; and a plastic packaging layer, wherein the main chip and the TSV interconnection structure are coated with the plastic packaging layer. The invention further provides a three-dimensional structure packaging method, compared with a traditional WB packaging mode, a substrate is omitted, and the packaging thickness is reduced; through the TSV silicon bridge, vertical stacking between the chips is realized. Through the RDL, I / O re-surface distribution is realized, the interconnection density is greatly improved, the interconnection distance is shortened, and the performance is better.

The invention relates to a chip pre-packaging steel sheet frame packaging structure and a manufacturing method thereof, and belongs to the technical field of semiconductor chip packaging, the chip pre-packaging steel sheet frame packaging structure comprises a stainless steel sheet carrier, a peelable material pattern layer is fixedly installed on the upper surface of the stainless steel sheet carrier, a resin pattern layer is fixedly installed on the upper surface of the peelable material pattern layer, and a metal layer is fixedly installed on the upper surface of the resin pattern layer. A chip and a pre-encapsulated resin layer are fixedly mounted on the upper surface of the resin pattern layer, and chip bumps are fixedly mounted on the upper surface of the chip. According to the chip pre-packaging steel sheet frame packaging structure and the manufacturing method thereof, the corresponding I / O number of the chip pre-packaging steel sheet frame packaging structure can be randomly arranged and designed, so that the flexibility of chip packaging I / O random wiring is improved, the chip packaging thickness is reduced by 30%, and the chip packaging efficiency is improved. Furthermore, multi-chip integrated packaging can be realized by adopting a reverse-order process manufacturing method of semiconductor chip packaging; the manufacturing of a wire bonding pad of the lead frame and the wire bonding process in semiconductor chip packaging are further cancelled, and the material cost is reduced.