3results about How to "Reduce package thickness" patented technology

The utility model relates to the technical field of LED packaging, in particular to a side-emitting multi-color integrated LED packaging structure, which comprises a ceramic substrate provided with a common-anode RGBW chip group. The RGBW chip set is directly welded on the ceramic substrate by adopting a flip chip design, the overall thickness of the packaging structure is less than or equal to 1.2 mm, the RGBW chip set is matched with preset solder paste below the RGBW chip set to be mounted on a bonding pad, the RGBW chip set is directly welded on the ceramic substrate by adopting the flip chip design, technologies such as gold wire bonding and matching with a film pasting technology are abandoned, and the packaging structure is simple in structure, convenient to manufacture and high in packaging efficiency. The overall thickness of the packaging structure is smaller than or equal to 1.2 mm, the packaging thickness is greatly reduced, the packaging structure can perfectly adapt to ultrathin application scenes such as side-entry backlight, the problem in the aspect of ultra-thinness in the traditional technology is effectively solved, the number of bonding pads is reduced to five by adopting the design that RGBW four-in-one chips share the anode / cathode, the anodes of the RGBW chips are connected in parallel, and the thickness of the packaging structure is greatly reduced. Only one common bonding pad and four independent bonding pads are needed, and the problem that bonding pad wiring is complex in the prior art is solved.

The invention provides a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure comprises the components of a substrate which is provided with a first surface and a second surface which are oppositely arranged along the thickness direction of the substrate, the first surface is provided with a groove, the substrate is also internally provided with a first via hole, and the first via hole penetrates through the first surface and the second surface and is located at the side of the groove; the first shielding layer covers the bottom wall and the side wall of the groove; the chip is arranged in the groove, the chip is provided with a pin, and the pin is electrically connected with the first via hole; and the second shielding layer covers at least part of the surface, deviating from the bottom wall of the groove, of the chip. The semiconductor packaging structure is used for achieving the effect of improving magnetic shielding comprehensiveness and storage density.

The utility model discloses a kind of packaging structures, applied to semiconductor technical field, comprising: photoelectric sensing chip and glass substrate;The upper surface of photoelectric sensing chip is provided with photosensitive area, and at least two first pads around photosensitive area;First pad surface is provided with conductive bump;Glass substrate is set on the upper surface of photoelectric sensing chip;Glass substrate lower surface is provided with rewiring layer;Rewiring layer includes at least two second pads around photosensitive area;And glass substrate is also provided with solder ball electric contact with second pad;Photoelectric sensing chip is electrically connected by conductive bump, second pad and solder ball.The utility model packaging thickness is small, heat dissipation performance is good, reliability is high, and cost is low.