Multi-chips package with reduced structure and method for forming the same

Abstract

The present invention provides a structure of multi-chips package and method of the same comprising a substrate with a pre-formed die receiving cavity formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and an elastic dielectric layer filled into a gap between the die and the substrate to absorb thermal mechanical stress; therefore the thickness of the package is reduced and the CTE mismatch of the structure is reduced. The present invention also provides a structure for SIP with higher reliability and lower manufacturing cost. the process is simpler and it is easy to form the multi-chips package than the traditional one. Therefore, the present invention discloses a fan-out WLP with reduced thickness and good CTE matching performance.

Description

technical field [0001] The present invention relates to system-in-package (SIP), more specifically to board-level package (PSP) of system-in-package, and in particular to a multi-die package structure with reduced structure and its forming method. Background technique [0002] In the field of semiconductor devices, the device size is reduced but the device density is increased. Traditional packaging technologies, such as lead frame packaging, flexible packaging, and rigid packaging technology cannot meet the needs of manufacturing small-sized dies with high cell density; therefore, there is a demand for new packaging and in-line technologies suitable for high-density cells. [0003] For the above reasons, packaging technology is developing towards ball grid array packaging (BGA), flip chip (FC-BGA), grain level packaging (CSP), and wafer level packaging (WLP); among them, wafer level packaging is an advanced packaging technology , The packaging and testing of the die is per...

AI Technical Summary

Problems solved by technology

[0004] Although the use of wafer-level packaging can reduce the thermal expansion coefficient mismatch between the die and the interconnect substrate (such as the thermal expansion coefficient mismatch between the build-up layer and the redistribution layer), the silicon die (2.3) and the core paste (core paste) ( 20-180) The difference in thermal expansion coefficient is still large enough to cause the resulting mechanical stress to cause reliability problems during temperature cycle tests

In addition, the different composition and material of the cutting line, such as sand core sticky, glass and epoxy resin, will also make the cutting process more complicated

[0005] Another traditional WLP manufacturing process problem is that the stacked redistribution layers formed on the build-up layer on the die must be optimized (refined); therefore, the package thickness must be reduced to meet the shrinking package structure requirements

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