85 results about "System in package" patented technology

The invention discloses an IC (integrated circuit) chip packaging detection method for realizing system-in-package and 3D (three-dimensional) packaging, which relates to the technical field of chip packaging detection, and comprises the following steps: vertically stacking a plurality of DRAM (dynamic random access memory) core particles on a basic logic core particle with a micro-bump array on the surface through silicon through holes, and activating a self-detection circuit to obtain a suspicious area coordinate list; dividing regional risk levels through a targeted scanning scheduling algorithm, and generating a differentiated scanning parameter set; for each suspicious area, controlling an external X-ray source to collect multispectral projection data according to the differential scanning parameter set; performing three-dimensional reconstruction on the multiple groups of multispectral projection data by using an enhanced reconstruction model embedded with physical priori knowledge to obtain enhanced three-dimensional body data; and performing automatic defect identification on the enhanced three-dimensional body data, and outputting the identified defect as a detection result. The invention aims to solve the problems of difficulty in perspective imaging and insufficient resolution of internal defects of the high-density 3D stacked chip.

The invention relates to a structured light imaging system suitable for semiconductor SIP system-in-package, which comprises a central camera, and a plurality of groups of DLP projections and side cameras are symmetrically arranged on two sides of an optical axis of the central camera; the DLP projector emits parallel light beams to irradiate the surfaces of the crystal grains, and the side cameras receive reflected light rays in parallel; the device further comprises a control unit, and the control unit sequentially controls the DLP projectors and the side cameras which are symmetrically arranged in pairs to synchronously work and processes image data so as to reconstruct the three-dimensional morphology of the surface of the crystal grain. When incident light emitted by the DLP projector irradiates the surface of the crystal grain at a specific angle, specular reflection light of the incident light propagates in the symmetrical direction according to the reflection law. The side camera and the DLP projector are symmetrically arranged, so that the optical axis of the side camera is consistent with a reflection light path, and a highlight area image generated by mirror reflection is accurately captured. The layout breaks through the limitation of the traditional diffuse reflection hypothesis, so that the morphology information of the high-reflection surface can be completely acquired, and the accuracy and reliability of crystal grain three-dimensional reconstruction in SIP packaging are remarkably improved.

A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

System-in-package (SiP) devices, and associated systems and methods are disclosed herein. In some embodiments, a SiP device can include a base substrate, as well as a host device and an improved-thermal high-bandwidth memory (HBM) device each integrated with the base substrate. The improved-thermal HBM device can include an interface die and a stack of one or more memory dies carried by the interface die. The interface die includes an input / output (IO) circuit, which is communicably coupled via one or more IO circuit interfaces to the host device through communication channels of the base substrate. The IO circuit interfaces of the improved-thermal HBM device distributes physical interconnect bumps for transmit data and receive data in a dispersed manner along an edge of the interface die in a manner to reduce the occurrence of thermal hotspots.

The application relates to the technical field of system-in-package, and discloses a functional chip SIP (System in Package) system-in-package method and system. The method constructs a reduced-order discrete thermal state predictor through multi-order exponential attenuation fitting, generates a DVFS gear-noise hazard degree spectrum mapping table based on a synchronous switching noise spectrum and an ADC noise sensitivity curve, generates a multi-DVFS working condition robust grounding network topology by optimizing a narrow bridge connection structure parameter by using a sequential quadratic programming, quantizes equivalent noise interference amounts of each DVFS gear on an ADC chip, and jointly optimizes DVFS gear selection and power consumption upper limit distribution under a rolling time domain mixed integer quadratic programming framework, simultaneously performs online model correction through exponential weighted moving average and Kalman filtering, and realizes cooperative satisfaction of thermal constraints and noise constraints.

A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

The invention discloses head-mounted display equipment, and relates to the technical field of intelligent display equipment, and the head-mounted display equipment comprises a system-in-package main board, an auxiliary circuit board, a conductive part which is electrically connected with the system-in-package main board and the auxiliary circuit board, and a mirror frame. The system-in-package main board and the auxiliary circuit board are arranged on the two sides of the mirror frame respectively. According to the technical scheme provided by the invention, the system-in-package mainboard with a higher integration level is adopted, and the system-in-package mainboard is arranged in the mirror frame and is electrically connected with the auxiliary circuit board through the conductive piece; compared with the prior art, the overall size of the head-mounted display device can be optimized, and the internal space of the device is saved.

A wafer scale system-in-package structure and a method for forming the same, the package structure includes: a redistribution layer comprising an upper surface and a lower surface opposite to the upper surface; a plurality of chip modules mounted on the upper surface of the redistribution layer and electrically connected to the redistribution layer; a back surface bridge chip mounted on the lower surface of the redistribution layer and electrically connected to the redistribution layer, where the back surface bridge chip is configured to interconnect adjacent chip modules; and a first molding layer located on the upper surface of the redistribution layer, covering the chip modules, where the first molding layer exposes the upper surface of the chip modules.

A memory device includes a physical layer (PHY) interface, and a memory cell array. The PHY interface includes a phase adjusting circuit configured to generate a plurality of phase-shifted clock signals and a phase-shifted training clock signal based on a clock signal and configured to delay the clock signal based on a plurality of comparison signals output from a comparator, the comparator configured to compare training data with each of a first reference voltage and a second reference voltage based on the plurality of phase-shifted clock signals and the phase-shifted training clock signal to output the plurality of comparison signals, the plurality of comparison signals including first comparison signals based on the plurality of phase-shifted clock signals, and second comparison signals based on the plurality of phase-shifted clock signals and the phase-shifted training clock signal, and a decoder configured to perform a duo-binary decoding on the first comparison signals.

This application discloses an inductor structure and its fabrication method, equipment, and dielectric. The inductor structure includes an inductor winding, a magnet, and a metal frame. The magnet encloses the inductor winding to form a cuboid inductor body. The metal frame covers the top and / or bottom of the cuboid inductor body and connects to the inductor winding terminals that are extended and bent to the top and / or bottom of the cuboid inductor body. By adding a metal frame to the inductor surface, an inductor structure with electrical interconnect design is achieved, which is compatible with mature molding inductor manufacturing methods and semiconductor processes. Advanced system-in-package (SIIP) requires higher dimensional accuracy than general inductor manufacturing capabilities, limiting the flexibility of package design. The electrode reconfiguration method provided by this invention can solve this accuracy mismatch and improve design flexibility.

The embodiment of the invention provides a reflection phase regulation and control device based on system-in-package, and relates to the field of electronic device integration, and the reflection phase regulation and control device comprises a first-layer multi-layer wiring ceramic cavity, a second-layer ceramic wall body and a third-layer multi-layer wiring ceramic cavity. A radiation patch is arranged on the inner surface of the first-layer multi-layer wiring ceramic cavity to form a reflection unit; the top end of the second-layer ceramic wall body is connected with the first-layer multi-layer wiring ceramic cavity, and the bottom end of the second-layer ceramic wall body is connected with the third-layer multi-layer wiring ceramic cavity to form a resonant cavity; and a driving chip and a terminal computing chip are arranged at the bottom of the inner surface of the third-layer multi-layer wiring ceramic cavity. According to the reconfigurable reflective array system, a top-layer computing architecture in a traditional reconfigurable reflective array system is changed into a terminal computing architecture, and the stability and manufacturability of products are improved by improving the integration level of the terminal, reducing the complexity of the system and greatly simplifying the physical structure of the system.

A reconfigurable inference platform implemented in a system-in-package configuration is provided. The system in the reconfigurable inference platform includes a processor chip, a first memory chip storing a set of executable models for inference engines, and a second memory chip storing weights for a selected executable model. The processor chip has a running processor core, an accelerator core, and a processor-memory interface exposed on a chip-to-chip bonding surface. The first memory chip is, for example, a three-dimensional NAND flash memory. The second memory chip can include a non-volatile random access memory, such as a phase change memory. A direct vertical connection structure, such as a via-to-via connection structure, is provided between the processor chip and the second memory chip.

The invention discloses a splicable low-light-storage integrated power supply module, and belongs to the technical field of new energy and microelectronics. The module adopts a three-dimensional heterogeneous integrated stacking framework, and an optical window layer, a photoelectric conversion layer, a signal processing and power management layer and an energy storage layer are vertically integrated in a single packaging body. High-density vertical interconnection among the functional layers is realized through a system-level packaging technology, and a standardized interface is arranged on the side wall of the module, so that mechanical splicing and electrical interconnection among a plurality of modules are supported. Extreme miniaturization, high reliability and intelligent expandability of the optical storage power supply system are achieved, the problems that an existing discrete power supply scheme is low in space utilization rate, damaged in system efficiency, poor in reliability and the like are solved, and the optical storage power supply system is particularly suitable for application scenes such as Internet of Things equipment, portable electronic equipment and distributed sensing networks.

A Secure Enclave SiP (SE-SiP) is disclosed, which is an improvement to Trusted Platform Module (TPM) concepts, and in certain aspects, is a general-purpose next-generation security building block that provides all the security benefits of a system designed using a TPM, replaces the need to trust a general-purpose CPU chip vendor with the need to trust a much simpler more trustworthy configurable device, and replaces the need to trust the entire system motherboard manufacturer with the much more limited need to trust the SE-SiP manufacturer. It can provide privacy for the software and data sent to the system, resident on it, or retrieved from it, with respect to all parties—including the person / party in physical possession of the device.

A semiconductor device has a substrate. An electrical component is disposed over a first surface of the substrate. A solder paste is disposed over the first surface of the substrate. A conductive pillar is disposed on the solder paste. An encapsulant is deposited over the first surface of the substrate, the electrical component, and the conductive pillar. A solder bump is formed over the conductive pillar.

The application discloses a wafer-level system test structure, which controls TAPs of dies in a wafer through a TAP controller to form a two-dimensional test network, wherein each die comprises a first, a second and a third test access port (TAP). The first TAP is communicatively connected with the third TAP in the upper-level die in the Y direction to form a Y-direction test chain, the second TAP is communicatively connected with the third TAP in the lower-level die in the X direction to form an X-direction test chain, and the third TAP can be configured to be communicatively connected with the first TAP in the Y direction or the second TAP in the X direction according to requirements, thereby forming a complete test chain. The two-dimensional grid deployment enables effective functional test of the dies themselves when production defects occur in the test structure itself, thereby improving yield. In addition, the Y-direction or X-direction test chain can be flexibly selected according to test targets, thereby improving test efficiency and reducing test cost.

Enhancing spurious rejection in an acoustic filter circuit is provided. Specifically, the filter circuit includes an acoustic bandpass filter circuit and an acoustic bandstop filter circuit. In embodiments disclosed herein, the acoustic bandpass filter circuit and the acoustic bandstop filter circuit can be integrated into either a single semiconductor die or a single system-in-package (SiP). By integrating the acoustic bandstop filter circuit with the acoustic bandpass filter circuit, it is possible to enhance spurious rejection with minimum impact on insertion loss and passband performance to thereby improve overall performance of the acoustic filter circuit. Moreover, it is possible to reduce fabrication variation and cost of the acoustic filter circuit as well.

The invention discloses a green ceramic chip, a ceramic substrate and a preparation method, and relates to the technical field of electronic ceramics. According to the invention, the raw ceramic chip with a specific ratio is designed, the ceramic substrate containing multiple layers of raw ceramic chips is designed on the basis of the raw ceramic chip, and the ratio of the raw ceramic chip of each layer is controlled to enable the thermal expansion coefficient of each layer to meet gradient change, so that the problem that CTE of heterogeneous materials in system-level packaging is not matched is effectively solved; in addition, the sintering temperature of the green ceramic chip is higher, the mechanical strength is higher, and the ceramic substrate has higher impact resistance.

The application discloses a kind of system-in-package substrate and its processing method, comprising: the intermediate plate formed with ultra-thick copper micro pitch circuit pattern is prepared, the relative length difference between multiple SET plate board edge area B of the intermediate plate and the reentrant lead connected with circuit pattern is not more than 15% respectively made out;Thermally reformed characteristic photosensitive insulating resin film and first ink dry film are stacked on the intermediate plate to fill the micro gap between circuit pattern;Part of the composite insulating film is removed to expose circuit pattern and reentrant lead;Make out solder mask layer and electroplated gold layer, control height difference between electroplated gold layer and solder mask layer ≤5 μm.The processing method is simple, easy to implement, and the system-in-package substrate obtained meets the technical requirements of high-density integrated packaging, ultra-high heat dissipation, resin-filled circuit pattern, ink thickness on copper surface ultra-thin, height difference between soldering surface and solder mask layer ≤5 μm, etc.;Promote the development of system-in-package technology.

The invention discloses an airborne intelligent control module packaging method based on an SIP (Session Initiation Protocol) technology, belongs to the technical field of airborne electronic equipment packaging, and aims to solve the problems of overlarge size and weight, poor signal integrity and insufficient reliability. The method comprises the following steps: cleaning and passivating the surfaces of chips, removing an oxide layer and pollutants, stacking and integrating multiple chips, stacking a core processing chip, a storage chip, an interface chip and a passive device in a preset area of a ceramic substrate according to a functional level by adopting a flip-chip bonding and bonding combined mode, forming a chip stacking unit, and performing high-density interconnection construction; according to the invention, through multi-chip stacking integration and system-level packaging, the size of the module is reduced compared with that of traditional PCB packaging, the weight is reduced, and the module can adapt to a compact installation space of airborne equipment; by adopting the TSV vertical interconnection and short-distance wiring design, the parasitic inductance and capacitance are reduced, and the requirement of high-speed data processing is met.

The invention discloses a green ceramic chip, a ceramic substrate and a preparation method, and relates to the technical field of electronic ceramics. According to the invention, the raw ceramic chip with a specific ratio is designed, the ceramic substrate containing multiple layers of raw ceramic chips is designed on the basis of the raw ceramic chip, and the ratio of the raw ceramic chip of each layer is controlled to enable the thermal expansion coefficient of each layer to meet gradient change, so that the problem that CTE of heterogeneous materials in system-level packaging is not matched is effectively solved; in addition, the green ceramic chip is higher in mechanical strength and heat conductivity coefficient, and the prepared ceramic substrate has higher impact resistance and can adapt to more application scenes.

This invention proposes a battery internal multi-parameter monitoring microsystem module and packaging method based on system-level packaging, belonging to the field of microelectronic packaging and battery management technology. The module includes: a packaging substrate; a pressure sensing chip, a temperature sensing chip, a gas sensing chip, and a signal processing chip, respectively mounted on different positions on the same plane of the packaging substrate; the signal processing chip is electrically connected to the pressure sensing chip, the temperature sensing chip, and the gas sensing chip; an integrated molding compound encapsulates the packaging substrate, the pressure sensing chip, the temperature sensing chip, the gas sensing chip, and the signal processing chip; wherein, at least two open cavities are formed on the integrated molding compound, and the at least two open cavities expose the pressure-sensing diaphragm of the pressure sensing chip and the sensitive area of ​​the gas sensing chip, respectively.

Systems, apparatus, articles of manufacture, and methods are disclosed for memory access for multi-chiplet system-in-package. Example instructions cause at least one circuit in a system-in-package (SiP) to: reserve a region in memory associated with the SiP for exclusive use by a first die of the SiP and exclude for use by a second die of the SiP. For example, the memory is for use by a plurality of respective dies of the SiP.

This invention discloses a silicon photonic integrated package and method with a room-temperature quantum coherent control structure, comprising: a photoelectric composite interposer layer having vertical photonic vias and electrical vias; four heterogeneous waveguide structures within the photonic vias for vertical optical signal transmission; copper pillars within the electrical vias for electrical interconnection; a first microchannel on the back of the interposer layer; a quantum material heterogeneous integration module bonded to a set of copper pillars, integrating a diamond thin film containing NV color centers, and containing an optical microcavity, photonic crystal waveguide, and microlens; a room-temperature quantum control circuit bonded and interconnected to another set of copper pillars; an optical engine module, located above the control circuit and aligned and coupled to the waveguide interposer layer; and each functional layer integrated and packaged from bottom to top on a carrier board, forming a system-level package with three-dimensional electrical, optical, and thermal interconnection and room-temperature coherent quantum state manipulation capabilities. This invention solves technical challenges such as heterogeneous bonding of silicon photonics and quantum materials, thermal stress mismatch, and photoelectric crosstalk.

The embodiment of the invention provides a fan-out type system-in-package method and a fan-out type system-in-package structure. The fan-out type system-in-package method comprises the following steps: forming at least one rewiring layer on a temporary carrier; forming a plurality of conductive columns on the first surface of the rewiring layer; mounting a plurality of first chips on the first surface of the rewiring layer; forming a first plastic package layer wrapping the conductive columns and the first chip; cutting the first plastic package layer, and then removing the temporary carrier to form a plurality of independent intermediate package bodies; mounting a plurality of second chips on the second surface of the rewiring layer; forming a second plastic package layer wrapping the second chip; and thinning the first plastic packaging layer to expose the first chip and the conductive columns. According to the method, the rewiring layer is used for replacing a packaging substrate, so that the material cost is reduced, and the interconnection density is greatly improved; the signal transmission path is shortened, the signal loss is reduced, the packaging structure is more suitable for high-frequency application, and meanwhile, the packaging thickness is reduced after a packaging substrate is cancelled; the re-wiring layer is firstly formed and then the chip is mounted, so that the chip is not wasted and the cost is saved.

Voltage regulator devices on active silicon interposers and associated systems and methods are disclosed. Local High-Bandwidth Memory (HBM) device voltage regulation is provided via the active silicon interposer configured with one or more voltage regulators corresponding to one or more HBM devices of a system-in-package (SiP). Each of the voltage regulators are configured to receive a first voltage signal from an external power supply and to generate one or more voltage signals based on the first voltage signal. The one or more generated voltage signals are supplied to a given HBM device by a locally positioned voltage regulator. In some embodiments, the one or more generated voltage signals are further based on the voltage signal of a sense line coupling a given HBM device to a corresponding voltage regulator.

The application provides a communication chip and an electronic device, and relates to the technical field of wireless technology.The communication chip comprises a user identification module located in a system in package (SIP) structure and a communication module located in the SIP structure and connected with the user identification module; the user identification module comprises at least one first pin, the communication module comprises at least one second pin, and the at least one first pin and the at least one second pin are connected correspondingly; a first circuit is arranged between a first target pin and a second target pin connected with the first target pin correspondingly, the first target pin and the second target pin are both non-power supply ends, and the first target pin and the second target pin are both non-ground ends.The technical scheme of the application integrates the user identification module and the communication module, and the first circuit is arranged, so that the number of pins required during packaging can be greatly reduced, and the safety is improved.

A system-in-package structure (10) and a preparation method therefor. The system-in-package structure (10) comprises: a re-distribution layer (100), TSV bridging substrates (200), first-type chips (300), second-type chips (400), a first plastic packaging material layer (500), PCBs (600), third-type chips (700), and a second plastic packaging material layer (800). The TSV bridging substrates (200) and the first-type chips (300) are bonded to the upper surface of the re-distribution layer (100); the second-type chips (400) are bonded to the upper surfaces of the TSV bridging substrates (200); the PCBs (600) are bonded to the lower surface of the re-distribution layer (100); and the third-type chips (700) are bonded to the lower surfaces of the PCBs (600). The system-in-package structure (10) and the preparation method therefor can solve the problems that the packaging structure used in the existing packaging technology has high cost and a low manufacturing process yield, and needs to undergo multiple stages of different manufacturing factories during preparation, and is thus not conducive to rapid product development.

This invention discloses a low-dielectric glass material, glass-ceramic, and a method for preparing TGV through-holes for integrated circuit packaging. The glass material is composed of SiO2, B2O3, Al2O3, RO, R2O, and rare earth oxides Gd2O3 / La2O3, satisfying a SiO2 / B2O3 molar ratio of 2.0~3.5 and an Al2O3 / (Gd2O3+La2O3) molar ratio of 1:1~4:1. Through the "mixed base-like effect" and lattice distortion effect generated by the Gd2O3 / La2O3 dual doping, a dielectric constant ≤4.6, dielectric loss ≤0.001, and CTE 32~50 × 10⁻⁶ are achieved. ‑7 / °C. Further heat treatment yields a glass-ceramic containing single-crystal β-CaSiO3 phase, with a flexural strength ≥250 MPa. Based on this, laser-induced modification combined with wet etching is used to form TGV vias with an aspect ratio ≥50:1, followed by pulsed copper plating for filling, and low-temperature sealing with Kovar alloy at 975°C. Slow cooling and compressive stress design suppress bubbles and cracks. This invention solves the problems of signal loss, thermal stress failure, and insufficient mechanical strength in high-frequency packaging, and is suitable for RF connectors, MEMS, and 3D system-level packaging.