163 results about "System in package" patented technology

A chiplet hub for interconnecting a series of connected chiplets and internal resources. An HBM is mounted on top of the chiplet hub to provide multiple party access to the HBM and to save System in Package (SIP) area. The chiplet hub can form system instances to combine connected chiplets and internal resources, with the system instances being isolated. One type of system instance is a private memory system instance with private memory gathered from multiple different memory devices. The chiplet hubs can be interconnected to form a clustered chiplet hub to provide for a larger number of chiplet connections and more complex system. A DMA controller can receive DMA service requests from devices other than a system hosted, including in cases where the chiplet hub is non-hosted.

A chiplet hub for interconnecting a series of connected chiplets and internal resources. An HBM is mounted on top of the chiplet hub to provide multiple party access to the HBM and to save System in Package (SIP) area. The chiplet hub can form system instances to combine connected chiplets and internal resources, with the system instances being isolated. One type of system instance is a private memory system instance with private memory gathered from multiple different memory devices. The chiplet hubs can be interconnected to form a clustered chiplet hub to provide for a larger number of chiplet connections and more complex system. A DMA controller can receive DMA service requests from devices other than a system hosted, including in cases where the chiplet hub is non-hosted.

A chiplet hub for interconnecting a series of connected chiplets and internal resources. An HEM is mounted on top of the chiplet hub to provide multiple party access to the HEM and to save System in Package (SIP) area. The chiplet hub can form system instances to combine connected chiplets and internal resources, with the system instances being isolated. One type of system instance is a private memory system instance with private memory gathered from multiple different memory devices. The chiplet hubs can be interconnected to form a clustered chiplet hub to provide for a larger number of chiplet connections and more complex system. A DMA controller can receive DMA service requests from devices other than a system hosted, including in cases where the chiplet hub is non-hosted.

The invention discloses an IC (integrated circuit) chip packaging detection method for realizing system-in-package and 3D (three-dimensional) packaging, which relates to the technical field of chip packaging detection, and comprises the following steps: vertically stacking a plurality of DRAM (dynamic random access memory) core particles on a basic logic core particle with a micro-bump array on the surface through silicon through holes, and activating a self-detection circuit to obtain a suspicious area coordinate list; dividing regional risk levels through a targeted scanning scheduling algorithm, and generating a differentiated scanning parameter set; for each suspicious area, controlling an external X-ray source to collect multispectral projection data according to the differential scanning parameter set; performing three-dimensional reconstruction on the multiple groups of multispectral projection data by using an enhanced reconstruction model embedded with physical priori knowledge to obtain enhanced three-dimensional body data; and performing automatic defect identification on the enhanced three-dimensional body data, and outputting the identified defect as a detection result. The invention aims to solve the problems of difficulty in perspective imaging and insufficient resolution of internal defects of the high-density 3D stacked chip.

A chiplet hub for interconnecting a series of connected chiplets and internal resources. An HBM is mounted on top of the chiplet hub to provide multiple party access to the HBM and to save System in Package (SIP) area. The chiplet hub can form system instances to combine connected chiplets and internal resources, with the system instances being isolated. One type of system instance is a private memory system instance with private memory gathered from multiple different memory devices. The chiplet hubs can be interconnected to form a clustered chiplet hub to provide for a larger number of chiplet connections and more complex system. A DMA controller can receive DMA service requests from devices other than a system hosted, including in cases where the chiplet hub is non-hosted.

A chiplet hub for interconnecting a series of connected chiplets and internal resources. An HBM is mounted on top of the chiplet hub to provide multiple party access to the HBM and to save System in Package (SIP) area. The chiplet hub can form system instances to combine connected chiplets and internal resources, with the system instances being isolated. One type of system instance is a private memory system instance with private memory gathered from multiple different memory devices. The chiplet hubs can be interconnected to form a clustered chiplet hub to provide for a larger number of chiplet connections and more complex system. A DMA controller can receive DMA service requests from devices other than a system hosted, including in cases where the chiplet hub is non-hosted.

A chiplet hub for interconnecting a series of connected chiplets and internal resources. An HBM is mounted on top of the chiplet hub to provide multiple party access to the HBM and to save System in Package (SIP) area. The chiplet hub can form system instances to combine connected chiplets and internal resources, with the system instances being isolated. One type of system instance is a private memory system instance with private memory gathered from multiple different memory devices. The chiplet hubs can be interconnected to form a clustered chiplet hub to provide for a larger number of chiplet connections and more complex system. A DMA controller can receive DMA service requests from devices other than a system hosted, including in cases where the chiplet hub is non-hosted.

A chiplet hub for interconnecting a series of connected chiplets and internal resources. An HBM is mounted on top of the chiplet hub to provide multiple party access to the HBM and to save System in Package (SIP) area. The chiplet hub can form system instances to combine connected chiplets and internal resources, with the system instances being isolated. One type of system instance is a private memory system instance with private memory gathered from multiple different memory devices. The chiplet hubs can be interconnected to form a clustered chiplet hub to provide for a larger number of chiplet connections and more complex system. A DMA controller can receive DMA service requests from devices other than a system hosted, including in cases where the chiplet hub is non-hosted.

The invention relates to a structured light imaging system suitable for semiconductor SIP system-in-package, which comprises a central camera, and a plurality of groups of DLP projections and side cameras are symmetrically arranged on two sides of an optical axis of the central camera; the DLP projector emits parallel light beams to irradiate the surfaces of the crystal grains, and the side cameras receive reflected light rays in parallel; the device further comprises a control unit, and the control unit sequentially controls the DLP projectors and the side cameras which are symmetrically arranged in pairs to synchronously work and processes image data so as to reconstruct the three-dimensional morphology of the surface of the crystal grain. When incident light emitted by the DLP projector irradiates the surface of the crystal grain at a specific angle, specular reflection light of the incident light propagates in the symmetrical direction according to the reflection law. The side camera and the DLP projector are symmetrically arranged, so that the optical axis of the side camera is consistent with a reflection light path, and a highlight area image generated by mirror reflection is accurately captured. The layout breaks through the limitation of the traditional diffuse reflection hypothesis, so that the morphology information of the high-reflection surface can be completely acquired, and the accuracy and reliability of crystal grain three-dimensional reconstruction in SIP packaging are remarkably improved.

A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

A physical layer interconnect between chips / chiplets provides high bandwidth communication with low power requirements using an organic substrate such as a printed circuit board. An interface between first and second chiplets uses a separate chiplet, or a combination logic die and interconnect interface, interfacing with the interconnect. A connection between a computing device and a memory can be longer, allowing the computing device to be coupled to more memories, expansion slots, or external connections. The interconnect can route memory commands between computing devices and memories, allowing multiple and different computing devices to be coupled to each other or to multiple and different memories. The memories can perform in-memory computing using chiplets coupled thereto. The interconnect couples to possibly different computing devices and possibly different memories, such as in a rack configuration, including CPUs or GPUs. The specialized processing devices can include one or more TPUs or VPUs.

System-in-package (SiP) devices, and associated systems and methods are disclosed herein. In some embodiments, a SiP device can include a base substrate, as well as a host device and an improved-thermal high-bandwidth memory (HBM) device each integrated with the base substrate. The improved-thermal HBM device can include an interface die and a stack of one or more memory dies carried by the interface die. The interface die includes an input / output (IO) circuit, which is communicably coupled via one or more IO circuit interfaces to the host device through communication channels of the base substrate. The IO circuit interfaces of the improved-thermal HBM device distributes physical interconnect bumps for transmit data and receive data in a dispersed manner along an edge of the interface die in a manner to reduce the occurrence of thermal hotspots.

The application relates to the technical field of system-in-package, and discloses a functional chip SIP (System in Package) system-in-package method and system. The method constructs a reduced-order discrete thermal state predictor through multi-order exponential attenuation fitting, generates a DVFS gear-noise hazard degree spectrum mapping table based on a synchronous switching noise spectrum and an ADC noise sensitivity curve, generates a multi-DVFS working condition robust grounding network topology by optimizing a narrow bridge connection structure parameter by using a sequential quadratic programming, quantizes equivalent noise interference amounts of each DVFS gear on an ADC chip, and jointly optimizes DVFS gear selection and power consumption upper limit distribution under a rolling time domain mixed integer quadratic programming framework, simultaneously performs online model correction through exponential weighted moving average and Kalman filtering, and realizes cooperative satisfaction of thermal constraints and noise constraints.

A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

The invention discloses head-mounted display equipment, and relates to the technical field of intelligent display equipment, and the head-mounted display equipment comprises a system-in-package main board, an auxiliary circuit board, a conductive part which is electrically connected with the system-in-package main board and the auxiliary circuit board, and a mirror frame. The system-in-package main board and the auxiliary circuit board are arranged on the two sides of the mirror frame respectively. According to the technical scheme provided by the invention, the system-in-package mainboard with a higher integration level is adopted, and the system-in-package mainboard is arranged in the mirror frame and is electrically connected with the auxiliary circuit board through the conductive piece; compared with the prior art, the overall size of the head-mounted display device can be optimized, and the internal space of the device is saved.

A wafer scale system-in-package structure and a method for forming the same, the package structure includes: a redistribution layer comprising an upper surface and a lower surface opposite to the upper surface; a plurality of chip modules mounted on the upper surface of the redistribution layer and electrically connected to the redistribution layer; a back surface bridge chip mounted on the lower surface of the redistribution layer and electrically connected to the redistribution layer, where the back surface bridge chip is configured to interconnect adjacent chip modules; and a first molding layer located on the upper surface of the redistribution layer, covering the chip modules, where the first molding layer exposes the upper surface of the chip modules.

A memory device includes a physical layer (PHY) interface, and a memory cell array. The PHY interface includes a phase adjusting circuit configured to generate a plurality of phase-shifted clock signals and a phase-shifted training clock signal based on a clock signal and configured to delay the clock signal based on a plurality of comparison signals output from a comparator, the comparator configured to compare training data with each of a first reference voltage and a second reference voltage based on the plurality of phase-shifted clock signals and the phase-shifted training clock signal to output the plurality of comparison signals, the plurality of comparison signals including first comparison signals based on the plurality of phase-shifted clock signals, and second comparison signals based on the plurality of phase-shifted clock signals and the phase-shifted training clock signal, and a decoder configured to perform a duo-binary decoding on the first comparison signals.

The application provides a ka-band ultra-wideband miniaturized frequency converter, which comprises a tube shell, two multilayer printed boards, radio frequency BGA balls, ground BGA balls and a ka-band wideband down-conversion circuit, the tube shell encapsulates the two multilayer printed boards, the radio frequency BGA balls and the ground BGA balls in a system level of the ka-band wideband down-conversion circuit, the multilayer printed boards are vertically interconnected through radio frequency transmission lines, have through holes at the same positions in the vertical direction, the radio frequency BGA balls are arranged below the through holes, the ground BGA balls are arranged around the radio frequency BGA balls at equal intervals, the radio frequency signals between the two multilayer printed boards in the vertical direction are transmitted through the radio frequency BGA balls and the ground BGA balls, the ka-band wideband down-conversion circuit is arranged on the surface of the two multilayer printed boards, and the ka-band wideband down-conversion circuit is used for down-converting the input ka-band ultra-wideband radio frequency signals to L-band intermediate frequency signals. The application solves the technical problem of miniaturizing the ka-band ultra-wideband frequency converter through the vertical interconnection of the multilayer printed boards through the radio frequency transmission lines, the radio frequency BGA transmission, the multilayer stacking process of the radio frequency printed boards and the ka-band wideband down-conversion circuit.

A system-in-package (SIP) is described. The SIP includes a general-purpose memory die. The SIP also includes a near-memory compute die. The SIP further includes an inter-space filler in between the general-purpose memory die and the near-memory compute die.

This application discloses an inductor structure and its fabrication method, equipment, and dielectric. The inductor structure includes an inductor winding, a magnet, and a metal frame. The magnet encloses the inductor winding to form a cuboid inductor body. The metal frame covers the top and / or bottom of the cuboid inductor body and connects to the inductor winding terminals that are extended and bent to the top and / or bottom of the cuboid inductor body. By adding a metal frame to the inductor surface, an inductor structure with electrical interconnect design is achieved, which is compatible with mature molding inductor manufacturing methods and semiconductor processes. Advanced system-in-package (SIIP) requires higher dimensional accuracy than general inductor manufacturing capabilities, limiting the flexibility of package design. The electrode reconfiguration method provided by this invention can solve this accuracy mismatch and improve design flexibility.

The invention discloses a multi-head synchronous bonding system and method, and relates to the field of wafer-level system-level packaging. The system comprises a plurality of adjustable bonding heads arranged on the same X-Y axis motion platform; the Z-axis sharing module is internally provided with a high-precision linear motor and is used for synchronously driving a plurality of bonding heads to lift and realizing Z-axis position real-time feedback through a grating ruler; the bonding head adopts a modularized quick-release structure, and is mounted through a dovetail groove track, so that the stepless adjustment of the number and the spacing is realized; a laser distance measuring sensor, a voice coil motor-grating ruler closed-loop control mechanism, a force / temperature sensor and an AI algorithm module are further arranged and used for detecting and dynamically compensating the height, pressure and temperature of the bonding head in real time, and self-adaptive control and abnormal self-learning are achieved. The system supports expansion of multiple Z-axis-shared modules, achieves regional parallel operation through AI path planning, and is suitable for high-efficiency and high-precision bonding of large-size products. The invention further provides a corresponding bonding method, and the welding consistency and the production efficiency are further improved.

An interconnect structure and a system-in-package fabrication method for the interconnect structure are disclosed, the interconnect structure configured for electrically communicating / coupling one or more integrated circuit packages / semiconductor dies to a circuit board, the method includes forming one or more electrically conductive lines, filling one or more gaps between the one or more electrically conductive lines with an electrically insulating material, removing excess electrically insulating material, thereby obtaining a first layer of the interconnect structure, and repeating the above steps to produce additional one or more layers of the interconnect structure, wherein additional one or more layers are stacked over the first layer, thereby enabling immediate formation of vertical electrical connections between the conductive lines / patterns.

A three-channel power supply module based on SIP (Session Initiation Protocol) technology relates to the technical field of integrated circuits and comprises a three-channel power supply circuit, an active chip bare core and a passive device of the three-channel power supply circuit are packaged in an integrated ceramic tube shell, and the top of the integrated ceramic tube shell is connected with a metal cover plate by adopting a parallel seam welding process; the bare core is connected with the ceramic substrate through a conductive adhesive, the bare core pad is connected with the ceramic substrate through 25 [mu] m gold wire ultrasonic pressure welding, and the passive device is connected with the ceramic substrate through a tin soldering process. According to the invention, the SIP system-level packaging technology is adopted, the wide voltage input and three-path power supply output functions are realized, power can be supplied to a digital circuit and an analog circuit at the same time, a certain power supply universality requirement is met, various power utilization scenes of avionic products can be met, high power density and high integration level can be realized, the space is greatly saved, and the cost is reduced. The device has obvious advantages in the aspects of miniaturization, modularization, light weight and the like of products.

The application discloses a miniaturized multilayer electromagnetic bandgap structure. A dielectric substrate is arranged on a common ground plate, and three layers of metal structures, namely a first layer of spiral structure metal patch, a second layer of Z-shaped structure metal patch and a third layer of inverted Z-shaped structure metal patch, are sequentially embedded in the dielectric substrate from top to bottom. The first layer of spiral structure metal patch and the second layer of Z-shaped structure metal patch, the second layer of Z-shaped structure metal patch and the third layer of inverted Z-shaped structure metal patch, and the third layer of inverted Z-shaped structure metal patch and the common ground plate are electrically connected through metal through holes. The electromagnetic bandgap structure works at a lower frequency, can reduce electromagnetic radiation leakage between sputtering film and a PCB ground plane, and improves electromagnetic shielding effectiveness of a system-in-package.

The embodiment of the invention provides a reflection phase regulation and control device based on system-in-package, and relates to the field of electronic device integration, and the reflection phase regulation and control device comprises a first-layer multi-layer wiring ceramic cavity, a second-layer ceramic wall body and a third-layer multi-layer wiring ceramic cavity. A radiation patch is arranged on the inner surface of the first-layer multi-layer wiring ceramic cavity to form a reflection unit; the top end of the second-layer ceramic wall body is connected with the first-layer multi-layer wiring ceramic cavity, and the bottom end of the second-layer ceramic wall body is connected with the third-layer multi-layer wiring ceramic cavity to form a resonant cavity; and a driving chip and a terminal computing chip are arranged at the bottom of the inner surface of the third-layer multi-layer wiring ceramic cavity. According to the reconfigurable reflective array system, a top-layer computing architecture in a traditional reconfigurable reflective array system is changed into a terminal computing architecture, and the stability and manufacturability of products are improved by improving the integration level of the terminal, reducing the complexity of the system and greatly simplifying the physical structure of the system.

This invention relates to the field of integrated circuit packaging technology, and in particular to a system-in-package (SIP) method and packaging device. The SIP method involves first preparing a substrate carrier plate that includes both a base carrier plate and a temporary bonding material layer; then, batch exposure, development, and etching of copper plates, filling circuit gaps with passivation dry film to form a motherboard, and cutting independent thick copper interconnect units adapted to the first type of chip to be packaged; subsequently, the chip and the unit are mounted on the carrier plate, and a second type of chip is soldered using metal bumps, making the unit a customized thick copper redistribution layer; finally, through molding, disassembling the carrier plate, creating passivation layer openings and metal circuit terminals, the SIP is completed. By reconfiguring the process route to achieve pre-integration of thick copper units, the thick copper electroplating process on the front side of the chip is avoided, eliminating wafer warpage problems from the source, significantly simplifying the packaging process, and completely eliminating interface risks caused by adhesive-mediated connections, thus combining high reliability with design flexibility.

The present invention relates to an optical system-in-package and an optical module using same, wherein a laser diode can be packaged together with a silicon photonics chip and an electronic IC in the O-SiP, thereby implementing a short signal line and implementing a structure with integrated optical / electronic elements at a semiconductor package level. The optical system-in-package of the present invention comprises: a mold body having a first surface and a second surface; a laser diode arranged in or outside the mold body; a photonic IC which is molded inside the mold body, receives an optical signal, input from the laser diode through an input waveguide connected to an input side, and has multiple output waveguides connected to an output side; an electronic IC molded in the mold body; a fiber array unit molded in the mold body; and a redistribution layer which is formed on the first surface of the mold body and on which multiple external connection terminals are disposed.

A reconfigurable inference platform implemented in a system-in-package configuration is provided. The system in the reconfigurable inference platform includes a processor chip, a first memory chip storing a set of executable models for inference engines, and a second memory chip storing weights for a selected executable model. The processor chip has a running processor core, an accelerator core, and a processor-memory interface exposed on a chip-to-chip bonding surface. The first memory chip is, for example, a three-dimensional NAND flash memory. The second memory chip can include a non-volatile random access memory, such as a phase change memory. A direct vertical connection structure, such as a via-to-via connection structure, is provided between the processor chip and the second memory chip.

The invention discloses a splicable low-light-storage integrated power supply module, and belongs to the technical field of new energy and microelectronics. The module adopts a three-dimensional heterogeneous integrated stacking framework, and an optical window layer, a photoelectric conversion layer, a signal processing and power management layer and an energy storage layer are vertically integrated in a single packaging body. High-density vertical interconnection among the functional layers is realized through a system-level packaging technology, and a standardized interface is arranged on the side wall of the module, so that mechanical splicing and electrical interconnection among a plurality of modules are supported. Extreme miniaturization, high reliability and intelligent expandability of the optical storage power supply system are achieved, the problems that an existing discrete power supply scheme is low in space utilization rate, damaged in system efficiency, poor in reliability and the like are solved, and the optical storage power supply system is particularly suitable for application scenes such as Internet of Things equipment, portable electronic equipment and distributed sensing networks.

A Secure Enclave SiP (SE-SiP) is disclosed, which is an improvement to Trusted Platform Module (TPM) concepts, and in certain aspects, is a general-purpose next-generation security building block that provides all the security benefits of a system designed using a TPM, replaces the need to trust a general-purpose CPU chip vendor with the need to trust a much simpler more trustworthy configurable device, and replaces the need to trust the entire system motherboard manufacturer with the much more limited need to trust the SE-SiP manufacturer. It can provide privacy for the software and data sent to the system, resident on it, or retrieved from it, with respect to all parties—including the person / party in physical possession of the device.