Microwave multi-chip packaging structure using silicon through hole and manufacture method thereof

A microwave multi-chip and through-silicon via technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problems of low integration density, complex process, and low yield, and achieve high packaging and integration Density, simple process, and improved yield

Active Publication Date: 2012-10-10
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a microwave multi-chip packaging structure using through-silicon vias and its manufacturing method, which is used to solve the problem of complex process, low yield, and signal crosstalk in the prior art. , high loss, and low integration density

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  • Microwave multi-chip packaging structure using silicon through hole and manufacture method thereof
  • Microwave multi-chip packaging structure using silicon through hole and manufacture method thereof
  • Microwave multi-chip packaging structure using silicon through hole and manufacture method thereof

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Embodiment Construction

[0089] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0090] see Figure 1a to Figure 1m ,as well as figure 2 . It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of ​​the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each com...

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Abstract

The invention provides a microwave multi-chip packaging structure using a silicon through hole and a manufacture method thereof. The method uses a temperature safety valve (TSV) to achieve two-sided integrated system-stage packaging structure, when a monolithic microwave integrated circuit (MMIC) chip needs integrating, a user does not need embed a substrate before wiring, and performance, reliability and rate of finished products of the packaging structure are improved. Simultaneously, processes such as injection, corrosion, release and high temperature annealing in a manufacture process can be used before integration of the MMIC, and components needing special processes can be assembled and integrated in advance on the other side of the substrate. Therefore, the substrate comprising active and passive devices, micro-electromechanical systems (MEMS), photoelectric devices and the like can be conveniently manufactured in a large scale before integration of the MMIC, and the manufacture method is simple in process, reduces cost, and is advanced and reliable at present.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a microwave multi-chip packaging structure utilizing through-silicon holes and a manufacturing method thereof. Background technique [0002] In order to meet the needs of the development of very large scale integration (VLSI), a novel 3D stacked packaging technology emerged as the times require. It integrates chips of different performance and multiple technologies into a single package with the smallest size and lightest weight. It is a kind of vertical electrical conduction between chips and wafers. , the latest package interconnection technology to realize the interconnection between chips, different from the previous IC package bonding and overlay technology using bumps, the package interconnection technology uses TSV (Through Silicon Via) instead of 2D -Cu interconnection, which can maximize the density of chips stacked in the three-dimensional direction, minimize the ext...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L25/00H01L23/48
CPCH01L2224/16225H01L2924/1461
Inventor 陈骁罗乐汤佳杰徐高卫
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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