Microwave multi-chip packaging structure using silicon through hole and manufacture method thereof

A microwave multi-chip and through-silicon via technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problems of low integration density, complex process, and low yield, and achieve high packaging and integration Density, simple process, and improved yield
CN102723306AActive Publication Date: 2012-10-10SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
Publication Date
2012-10-10

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Abstract

The invention provides a microwave multi-chip packaging structure using a silicon through hole and a manufacture method thereof. The method uses a temperature safety valve (TSV) to achieve two-sided integrated system-stage packaging structure, when a monolithic microwave integrated circuit (MMIC) chip needs integrating, a user does not need embed a substrate before wiring, and performance, reliability and rate of finished products of the packaging structure are improved. Simultaneously, processes such as injection, corrosion, release and high temperature annealing in a manufacture process can be used before integration of the MMIC, and components needing special processes can be assembled and integrated in advance on the other side of the substrate. Therefore, the substrate comprising active and passive devices, micro-electromechanical systems (MEMS), photoelectric devices and the like can be conveniently manufactured in a large scale before integration of the MMIC, and the manufacture method is simple in process, reduces cost, and is advanced and reliable at present.
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Description

technical field

[0001] The invention relates to the field of integrated circuits, in particular to a microwave multi-chip packaging structure utilizing through-silicon holes and a manufacturing method thereof. Background technique

[0002] In order to meet the needs of the development of very large scale integration (VLSI), a novel 3D stacked packaging technology emerged as the times require. It integrates chips of different performance and multiple technologies into a single package with the smallest size and lightest weight. It is a kind of vertical electrical conduction between chips and wafers. , the latest package interconnection technology to realize the interconnection between chips, different from the previous IC package bonding and overlay technology using bumps, the package interconnection technology uses TSV (Through Silicon Via) instead of 2D -Cu interconnection, which can maximize the density of chips stacked in the three-dimensional direction, minimize the ext...

Claims

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