25 results about "Integrated circuit layout" patented technology

This invention provides a method, apparatus, medium, and terminal for transferring integrated circuit layout process information. The method includes: acquiring first-level information of each layer in a first layout and second-level information of each layer in a second layout; acquiring meaning information of the first-level information and the second-level information; matching the first-level information and the second-level information based on the meaning information to obtain multiple layer information pairs; exporting the first-level information as language text format information; matching the second-level information corresponding to the language text format information in the layer information pairs; replacing the language text format information according to the matched second-level information to obtain target text information; and generating a target process layout based on the target text information. This invention can quickly realize the process transfer of two integrated circuit layouts, improve layout transfer efficiency, and reduce costs.

According to the invention, an integrated circuit arrangement is formed by reducing the injection of charge carriers into a semiconductor substrate. The circuit arrangement comprises a first and second half-bridge connected as a full bridge, wherein the drain terminals of the first transistors and the source terminals of the second transistors are electrically connected. The two parallel-connected source terminals of the second transistors are connected to the first terminal of a two-terminal resistor, while the second terminal of the resistor provides a connection for a negative supply voltage or ground potential. A Zener diode is connected between the source terminal (supply voltage) and the gate terminal of at least one of the first MOS transistors. The transistors are surrounded by at least one guard ring.The guard ring is implemented as a contacted N or P well on the P or N substrate. Around the guard ring, further P or N wells, insulated by means of deep trench structures, are arranged.

This invention discloses an automatic routing optimization method and apparatus for chips, relating to the field of integrated circuit layout design technology. In this method, the chip is divided into multiple differential grids; the connectivity of the edges and / or diagonals of each differential grid is determined to generate connectivity relationships; candidate paths from the routing start point to the routing end point are determined based on the connectable edges and / or diagonals; differential grids associated with the candidate paths are retained while unrelated differential grids are deleted; the grid size is reduced within the retained area and the filtering is repeated until a preset threshold is met, at which point a pathfinding algorithm is executed to obtain the routing path. This method can reduce the automatic routing search area and improve the routing efficiency of large-scale complex chips.

This invention discloses a rapid assessment method for soft error rate caused by single-event effects based on an analytical function library. It addresses the problems of low efficiency and difficulty in supporting large-scale circuit evaluation in traditional TCAD simulation. The method constructs and calibrates device models based on process design kits to obtain accurate electrical characteristics of the calibration device model. Based on multidimensional key irradiation variables, dense TCAD sampling and parametric fitting are performed on the calibration device to construct a response function library. Based on the actual integrated circuit layout, particle transport simulation under radiation conditions is performed in Geant4 to extract the secondary particle set. The corresponding transient current is rapidly synthesized by querying the response function library and interpolating. The current is injected into the SPICE circuit netlist for simulation to determine whether single-event upset has occurred and to calculate the soft error rate. This method achieves an order-of-magnitude improvement in simulation efficiency while maintaining accuracy, making it suitable for rapid radiation resistance assessment and design hardening of complex integrated circuits.

The application discloses a high-density integrated circuit layout and wiring method, which realizes high-density layout of the integrated circuit by global and local layout control in the layout and wiring stage. An embodiment of the application discloses local layout control in the ECO stage of static timing analysis to complete convergence of all timing violations. In addition, another embodiment discloses a system for high-density integrated circuit layout and wiring, which adopts a global layout control unit and a local layout control unit in the layout stage to realize high-density layout under the premise of timing convergence, and adopts a local layout control unit and a local wiring control unit in the wiring stage to realize layout optimization.

Systems, devices, and methods for optimization of conducting interconnects are described. A method includes receiving an integrated circuit layout including a plurality of terminals and an interconnect, wherein the interconnect represents a conductive coupling between the plurality of terminals. The method includes receiving terminal information describing operating parameters of the plurality of terminals. The method includes receiving layer information describing material composition and material property information for the plurality of terminals and the interconnect. The method includes generating a three-dimensional representation of an integrated circuit using the integrated circuit layout and the layer information. The method includes determining an individual contribution of a cell included in the three-dimensional representation to a resistance-capacitance (RC) value of the interconnect using the three-dimensional representation and the terminal information. The method also includes generating an updated integrated circuit layout based at least in part on the individual contribution.

This invention belongs to the field of integrated circuit layout and design technology, specifically relating to a multi-level interconnect planning method for signal-power-thermal integrity in 2.5D-3D integrated chips. It aims to solve the problems of low planning efficiency and design convergence difficulties caused by differences in design rules between silicon interposers and packaging substrates. This invention takes chip placement, chip pin layout, and available wiring resources as inputs. Based on a hierarchical variable scheduling strategy, it divides interconnect design variables into three subsets: interposer design variables, substrate design variables, and bridging variables. A three-stage Bayesian optimization algorithm is used to optimize sequentially: Stage 1 optimizes interposer and bridging variables, generates candidate designs and interconnect layouts, and updates the surrogate model until convergence; Stage 2 optimizes bridging and substrate variables, initializes with the optimal solution from Stage 1, and executes the same process; Stage 3 jointly optimizes all variables, executes the evaluation and update process until convergence; the algorithm finally outputs the optimal set of interconnect design variables.

An electronic memory device includes a non-memory cell region and a memory cell region including circuitry formed in a substrate. The memory cell region includes first, second, and third sections. In a top view, the first section is closest to the non-memory cell region. The second and third sections are both farther from the non-memory cell region than the first section. In a cross-sectional side view, a first interconnect structure is disposed over a first side of the substrate. The first interconnect structure includes a first interconnect layer and a second interconnect layer. The first and second interconnect layers are configured to route memory signals to the first and second sections, respectively. A second interconnect structure is disposed on a second side of the substrate. The second interconnect structure includes a third interconnect layer configured to route memory signals to the third section. The present disclosure also relates to methods of fabricating an electronic memory device and methods of modifying an integrated circuit layout design.

An optimization method and apparatus for integrated circuit layout in the post-wire-wound stage are provided. The method includes: identifying power rails and corresponding power domains in an integrated circuit design file; performing design specification verification on circuit cells in the integrated circuit design file to calculate multiple usable areas; determining multiple electromigration violations corresponding to the power rails and related current information; defining a path to be corrected on the power rail corresponding to the electromigration violation based on the electromigration violation and the current information; replacing the types of multiple vias on the power rails that do not overlap with the path to be corrected; and correcting the number of vias on the power rails that overlap with the path to be corrected to reduce the number of electromigration violations.

This invention discloses a method for accelerating the development of PDK parameterized units for large-scale language models, relating to the field of integrated circuit layout design automation. It solves the technical problems of low development efficiency, unstable quality, and difficulty in knowledge transfer associated with traditional PDK parameterized unit development. The method includes: S11: collecting data resources and preprocessing them to obtain the training dataset and auxiliary database required for the model; S12: selecting a model and training and optimizing it; S13: merging and lightweighting the weights of the trained and optimized model; S14: locally deploying and applying the merged and lightweighted model; S15: validating and optimizing the locally deployed and applied model to obtain feedback data, and inputting the feedback data back into S11 for re-collection. This invention can effectively shorten the code generation time of PDK parameterized units and significantly improve code development efficiency for PDK parameterized units with complex structures.

The application discloses a kind of RC parasitic parameter extraction method and system based on Transformer, the method includes: obtaining integrated circuit layout file and process file, and constructs local interconnection sample;Wherein, the layout file is parsed, and geometric information is obtained;The process file is parsed, and material information and environmental information are obtained;Geometric information, material information and environmental information are serialized into structured Token sequence, semantic embedding, numerical embedding, position embedding and paragraph embedding are carried out, and form Transformer input vector;Self-supervised pre-training is carried out to structured Token sequence, masked Token modeling mode is used to reconstruct the structure Token and numerical Token that are shielded, and pre-training Transformer encoder is obtained;Capacitance label and resistance label generated by high-precision solver or RC extractor are used to fine-tune training of pre-training Transformer encoder with physical constraints, and RC prediction model is obtained;The layout file to be measured and process file are input into RC prediction model, and corresponding parasitic capacitance and / or parasitic resistance are output.

In an example there is provided a first integrated circuit. The first integrated circuit is configured to receive an audio signal and configured to drive an audio transducer based on the received audio signal. The first integrated circuit is configured to transmit a portion of the audio signal to a second integrated circuit.

This invention discloses a hotspot detection method for integrated circuit layouts based on R-tree graph construction. First, each independent and continuous polygon in the integrated circuit layout file is created as a node in the graph structure. An R-tree is used to establish spatial adjacency relationships, and polygon contour expansion technology is employed to determine node connectivity. When the expanded polygons have overlapping areas, connecting edges are established, thus constructing the graph structure. This graph structure is then input into a graph neural network model to obtain the hotspot prediction results for each node. This invention achieves an innovative solution that accurately preserves the geometric features of the layout while efficiently constructing the graph structure, completely avoiding rectangular segmentation. This effectively improves the model's representation ability and detection efficiency for complex real-world layouts.

A method of generating an IC layout diagram includes generating a plurality of logic patterns, wherein each logic pattern corresponds to a number of bits N greater than two, arranging a column of NOR-type read-only memory (ROM) bit cells as a plurality of N-bit groups separated from each other by isolation features, assigning a pattern of the plurality of logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the plurality of logic patterns in a storage device.

The application discloses an integrated circuit layout verification method and device, and belongs to the technical field of integrated circuit design. The method comprises the following steps: obtaining arrangement information of selected target units from an integrated circuit layout; performing out-expanding processing on to-be-detected metal lines of the target units according to design rule spacing requirements, and generating an auxiliary layer pattern; performing copy processing on the auxiliary layer pattern according to the arrangement information, and forming an auxiliary layer pattern set covering all target unit regions; performing Boolean operation on the auxiliary layer pattern set and global metal lines on the same layer, and generating an identification layer; when the identification layer is empty, it is determined that the to-be-detected metal lines meet the design rule spacing requirements; and when the identification layer is not empty, a spacing violation region indicated by the identification layer is output. The application realizes efficient and accurate spacing violation detection, and improves the automation degree and reliability of design rule checking.

The application provides a probability-driven-based layout optimization method, device, equipment and medium, and relates to the technical field of integrated circuit design. The method comprises the following steps: determining a target polygon to be optimized and a plurality of adjacent polygons thereof from an integrated circuit layout file; calculating the vertex interior angle of the target polygon, identifying convex points and convex degrees; performing a setback operation on each target convex point according to a set number of setback points and a setback step length; searching for a shortest distance critical interval of the target polygon and its adjacent polygons under the condition of meeting the process minimum distance, and calculating the confidence probability; iteratively calculating the confidence probability and the area ratio of the target polygon until the target confidence probability or the minimum area ratio is met, and stopping the iteration; and outputting the optimized layout data and generating an iteration log. The application makes the optimized layout meet the manufacturing tolerance requirements of advanced processes in a statistical sense, significantly reduces the risk of short circuit or performance deviation caused by random process fluctuations, and improves the manufacturing yield.

The application discloses a multi-expert module cooperative intelligent agent system for automatic generation of a Pcell layout, relates to design verification or optimization of an integrated circuit layout, and comprises three expert modules, a decision module, and the like, wherein the three expert modules are trained based on a constructed sequential decision problem to obtain an expert calling sequence; the decision module is used for problem decomposition on an input problem to obtain problem analysis; a target calling sequence matched with the problem analysis is searched as a target calling sequence, and then the problem analysis is input into an expert module at a first sequence position in the target calling sequence to obtain an output result of the expert module at the first sequence position; the problem analysis and the output result of the expert module at a previous sequence position in the calling sequence are taken as inputs of an expert module at a next sequence position, and finally process information corresponding to the input problem is obtained. The application improves the development efficiency of the Pcell layout, realizes fast migration of an existing process layout to a new process, and significantly shortens the research and development cycle.

This invention provides a digital integrated circuit layout method, apparatus, device, medium, and digital integrated circuit. The method includes: obtaining multiple netlists based on the netlist information and policy network model of each circuit module to be laid out. i The first layout diagram corresponding to the next iteration; based on the first... i The optimal first layout graph and greedy algorithm corresponding to the next iteration generate the... i The second layout diagram corresponding to the next iteration; in determining i If the first preset value is reached, the first i The second layout diagram corresponding to the next iteration is determined as the target layout diagram for each circuit module. i If the first preset value is not reached, based on the first i The next iteration corresponds to the layout graph sequence and the second layout graph, which updates the model parameters of the policy network model, and then... i Increase by 1, return to the execution step. i The next level of iteration. This invention can significantly improve the rationality and efficiency of digital integrated circuit layout.

According to the invention, an integrated circuit arrangement is formed by reducing the injection of charge carriers into a semiconductor substrate. The circuit arrangement comprises a first and second half-bridge connected as a full bridge, wherein the drain terminals of the first transistors and the source terminals of the second transistors are electrically connected. The two parallel-connected source terminals of the second transistors are connected to the first terminal of a two-terminal resistor, while the second terminal of the resistor provides a connection for a negative supply voltage or ground potential. A Zener diode is connected between the source terminal (supply voltage) and the gate terminal of at least one of the first MOS transistors. The transistors are surrounded by at least one guard ring.The guard ring is implemented as a contacted N or P well on the P or N substrate. Around the guard ring, further P or N wells, insulated by means of deep trench structures, are arranged.

The present disclosure relates to electrostatic discharge protection circuit, driving circuit, and pre-driver circuit and integrated circuit layout thereof. An integrated circuit layout of a pre-driver circuit includes a plurality of class one transistor regions having a density less than a predetermined level, and a class two base region surrounding the class one transistor regions in a complete ring. The present disclosure also provides an ESD circuit with better voltage resistance, and an output stage circuit with better stability.

This application discloses a design method and layout structure for three-dimensional integrated circuits, applicable to the field of integrated circuit design. The method first determines the first process technology used in the first device layer and the second process technology used in the second device layer. Then, based on the process design kit corresponding to the first process technology and the general simulation program model of the integrated circuit corresponding to the second process technology, circuit simulation is performed to determine the dimensions of the second type of device using the second process technology. Finally, based on the process design kit corresponding to the first process technology, the dimensions of the second type of device, and the vertical interconnect channels used to realize the electrical connection between the first type of device using the first process technology and the second type of device, a three-dimensional integrated circuit layout is designed. Thus, by vertically stacking, the projected area of ​​the logic cells approaches the area of ​​a single transistor, significantly reducing the integrated circuit layout area.

This invention relates to the field of semiconductor integrated circuit technology, and discloses a three-dimensional integrated circuit layout optimization method, system, and electronic device. The method first allocates module layers based on the number of through-silicon vias (TSVs) as the optimization target, decoupling and generating interconnection information for each layer. Then, it optimizes the two-dimensional layout of functional modules, inserting TSVs in the blank areas between modules to obtain initial position information. Finally, it optimizes the inter-layer joint temperature by iteratively exchanging the positions of functional modules, using the three-dimensional thermal aggregation index as the optimization target. This invention achieves coordinated optimization of TSV positions and functional module layout while ensuring computational efficiency, and effectively controls the thermal aggregation effect of the 3D-IC system.

A method is provided, including following operations: obtaining information on gate pitch and a ratio between the gate pitch and a first metal line pitch; comparing a preset metal line end spacing with a second metal line pitch, of multiple metal traces, and a spacing between a metal line layer and a power rail layer; in response to the comparison, defining multiple first metal line patterns overlapping multiple first gate patterns and defining multiple second metal line patterns disposed between two adjacent gate patterns in multiple second gate patterns; placing the first metal line patterns in a first row in a floorplan of an integrated circuit layout design and the second metal line patterns in a second row, adjacent the first row; and manufacturing at least one element in an integrated circuit based on the integrated circuit layout design.