152 results about "Integrated circuit layout" patented technology

The invention belongs to the related technical field of integrated circuit design, and discloses an integrated circuit design process collaborative optimization method and system, and the optimization method comprises the steps: S1, randomly generating a plurality of groups of process parameters; s2, TCAD simulation is carried out, and an electrical characteristic curve of the device is obtained; s3, extracting electrical characteristics and inputting the electrical characteristics into the intelligent parameter extraction model to obtain compact model parameters; s4, inputting the compact model parameters into the SPICE model, and generating an integrated circuit layout by using an automatic layout generation system; s5, taking the optimized circuit performance index as an optimization target, and adopting a Bayesian optimization method to generate an optimal process parameter of a next iteration round; and S6, judging whether an iteration termination condition is met or not, if not, skipping to S2, and if yes, outputting the current process parameters. According to the method, the process / design barrier can be broken, it is ensured that the process development and the circuit design process can be collaboratively carried out, the whole optimization process is completely automatic, and the high-precision and high-efficiency collaborative optimization process is achieved.

Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Methods for automated routing in an an integrated circuit layout design (322) using artificial intelligence (AI) and corresponding systems and computer-readable mediums. A method includes receiving (402) routing requirements (324), receiving (404) an unrouted layout design (322), and receiving (406) an AI model (306). The method includes creating (408) a routing strategy for the unrouted layout design (322) using the AI model (306) and the routing requirements (324). The method includes creating (410) a physical routing plan based on the routing strategy to produce a routed layout design (312). The method includes storing (412) the routed layout design, wherein a physical part can thereafter be manufactured (414) according to the routed layout design.

The invention relates to the technical field of integrated circuit reliability analogue simulation, in particular to an analogue simulation system and method applied to an integrated circuit. The method comprises the following steps: acquiring an integrated circuit layout and carrying out circuit topological structure datamation on the integrated circuit layout to obtain an oxide layer area grid chart; performing stress distribution mapping generation on the integrated circuit according to the oxide layer region grid chart to obtain a region stress state matrix; performing electric field-temperature collaborative analysis according to the regional stress state matrix to obtain a random fluctuation factor matrix; performing time sequence damage accumulation calculation according to the random fluctuation factor matrix to obtain a time sequence damage state set; and performing damage state feedback adjustment on the time sequence damage state set to obtain a time-varying damage evolution graph. According to the method, the fragile performance indexes and areas of the integrated circuit are identified, and the comprehensive circuit performance degradation characteristic spectrum is generated, so that a scientific basis is provided for reliability design and performance optimization of the integrated circuit.

The invention provides an integrated circuit layout classification method and system, a medium, a program and an electronic terminal, key coordinate points are obtained by identifying graphic units in a to-be-classified layout and extracting contour features, great dimension reduction of data is realized while key geometric features are reserved, the calculation complexity is remarkably reduced, and the processing efficiency is improved. Furthermore, the key coordinate points are mapped and aligned to the grid points according to a preset grid step length, a physical tolerance mechanism is constructed, and coordinate jitter introduced by precision limitation or process errors is effectively eliminated. According to the method, the graphs with the same topology but fine difference in coordinates can be accurately classified, the robustness of the algorithm to process deviation is remarkably improved, fragmentation of the classification result is avoided, and the classification effect is good.

The invention discloses an integrated circuit layout verification method and device, and belongs to the technical field of integrated circuit design, and the method comprises the steps: obtaining the arrangement information of a selected target unit from an integrated circuit layout; performing external expansion processing on the to-be-detected metal wire of the target unit according to a design rule spacing requirement to generate an auxiliary layer pattern; copying the auxiliary layer graph according to the arrangement information to form an auxiliary layer graph set covering all target unit areas; performing Boolean operation on the auxiliary layer graph set and the global metal wire on the same layer to generate an identification layer; when the identification layer is empty, determining that the to-be-detected metal wire meets the design rule spacing requirement; and when the identification layer is not empty, outputting the interval violation area indicated by the identification layer. According to the method and the device, efficient and accurate interval violation detection is realized, and the automation degree and the reliability of design rule inspection are improved.

The invention relates to the technical field of integrated circuits, in particular to an integrated circuit layout modular layout method and system based on AI matching. The method selects a target module; the target module is converted to an IC layout area, an initial circuit layout is generated, and an external rectangle and module internal pins are extracted; determining an initial coordinate of an interface point according to a shortest physical path from an internal pin of each module to an external rectangle to which the module belongs; determining a theoretical shortest path according to the respective displaceable range in the interface point combination; determining a path adaptation degree according to the actual connection path and the theoretical shortest path; the overall layout fitness is determined by combining the distribution dense characteristics of the actual connection paths; taking the overall layout fitness as an optimization target, performing iterative optimization through a genetic algorithm until the overall layout fitness converges, and outputting an optimized circuit layout; and inputting the optimized circuit layout into a pre-training AI engine, and outputting a final circuit layout, so that the expandability of layout design is improved.

Aspects of the disclosure are directed to automatically determining floor planning in chips, which factors in memory macro alignment. A deep reinforcement learning (RL) agent can be trained to determine optimal placements for the memory macros, where memory macro alignment can be included as a regularization cost to be added to the placement objective as a RL reward. Tradeoffs between the placement objective and alignment of macros can be controlled by a tunable alignment parameter.

The application provides a via hole design method of an integrated circuit layout, comprising the following steps: searching for a source end and a drain end of a via hole in the layout; judging whether the via hole can be used as a to-be-expanded via hole region; if yes, moving the via hole in four directions by a certain distance; if the moved via hole is located in an active region and the top of the moved via hole has a metal layer, and the metal layer on the top of the moved via hole is the same layer as the metal layer on the top of the original via hole, then expanding the via hole in the to-be-expanded via hole region; if the moved via hole is located in the active region and the top of the moved via hole does not have a metal layer, then extending the metal layer on the top of the original via hole to the place of the moved via hole, if the extended metal layer is the same layer as the metal layer near the moved via hole or if the extended metal layer is not the same layer as the metal layer near the moved via hole but meets a certain spacing, then expanding the via hole in the to-be-expanded via hole region.

The application provides a processing method of integrated circuit layout data in GDSII format and a computer storage medium, and the processing method comprises the following steps: establishing a rectangular coordinate system, and placing a rectangular layout with a multiple-point collinear condition in the rectangular coordinate system; taking an arbitrary point on the rectangular layout as an initial point to start traversal, and acquiring the coordinates of the traversed points; recording the vertex coordinates of the rectangular layout, and deleting the redundant point coordinates located on the edges of the rectangular layout; stopping the traversal and outputting the recorded vertex coordinates when the traversal is restarted from the initial point or the vertex recorded in the first traversal. Compared with the prior art, the application provides a processing method of integrated circuit layout data in GDSII format, which can compress the layout data with a multiple-point collinear condition, thereby reducing the size of the layout data and saving the storage space.

The application discloses a method and device for feature extraction of integrated circuit layouts and a non-transitory computer readable storage medium thereof. A circuit pattern layout file to be implemented on a semiconductor wafer is obtained from a memory. Data preparation and preprocessing is performed on the circuit pattern layout file. A deep learning model is established and trained. Transfer learning and model fusion are performed on the deep learning model. The deep learning model is used to perform image segmentation and feature extraction on the circuit pattern layout file to extract a plurality of features. Density parameters and total perimeter parameters of the plurality of features are calculated.

This invention provides a method, apparatus, medium, and terminal for transferring integrated circuit layout process information. The method includes: acquiring first-level information of each layer in a first layout and second-level information of each layer in a second layout; acquiring meaning information of the first-level information and the second-level information; matching the first-level information and the second-level information based on the meaning information to obtain multiple layer information pairs; exporting the first-level information as language text format information; matching the second-level information corresponding to the language text format information in the layer information pairs; replacing the language text format information according to the matched second-level information to obtain target text information; and generating a target process layout based on the target text information. This invention can quickly realize the process transfer of two integrated circuit layouts, improve layout transfer efficiency, and reduce costs.

The invention provides an integrated circuit layout splitting method and a related product. The splitting method comprises the following steps: constructing a conflict graph of the layout according to a preset spacing rule; performing structure search in the conflict graph to obtain a plurality of equivalent identification structures, and determining a plurality of groups of equivalent nodes in the nodes of the plurality of equivalent identification structures; under the condition that a conflict edge is connected between two equivalent nodes in any group of equivalent nodes, determining that the conflict graph is unsolvable; performing conflict solution on the conflict graph; and splitting the conflict graph into a plurality of split layouts of preset split layers. According to the method, whether the conflict graph contains the complex and unsolvable conflict relation or not can be quickly and effectively judged, the conflict relation is effectively optimized, and then normal dyeing and splitting of the layout are achieved.

The invention provides an OPC processing method of an integrated circuit layout and computer equipment. The OPC processing method for the integrated circuit layout comprises the following steps: carrying out partitioning analysis on a target integrated circuit layout to obtain a plurality of local areas; constructing features for each local area; reasoning and judging all the local areas by using a pre-trained learning model, wherein the learning model establishes a mapping relationship between features and classification results; and removing the local areas which do not need to be subjected to OPC processing, screening out the local areas which need to be subjected to OPC processing, and outputting a result. According to the scheme, the limitation of a traditional layout screening mode based on rules can be broken through, and precise screening of empty local areas and efficient elimination of invalid calculation are achieved; the adaptability of a learning model to a complex layout scene is improved, and core support is provided for efficiency optimization and precision guarantee of an OPC process.

The application discloses a kind of integrated circuit clock tree optimization method and system based on graph neural network and reinforcement learning, comprising the following steps: step S1: construct graph structure generation module, according to integrated circuit layout to construct the graph structure with register as node, with timing path as edge;Step S2: construct GNN feature extraction module, for the high-dimensional graph embedding representation of the feature vector of register node according to the graph structure constructed;Step S3: construct reinforcement learning network decision module, for receiving current node embedding representation vector and generating specific action after data processing;Step S4: construct timing verification and reward calculation module, for evaluating the updated circuit state, and obtaining reward signal to be used for the training of reinforcement learning network decision module;Step S5: constantly train reinforcement learning network decision module, until training is completed, finally obtain optimized register node feature vector, that is, optimized clock tree.

The application discloses a polygon decomposition method, an electronic device and a computer readable storage medium. The polygon decomposition method comprises the following steps: obtaining a to-be-decomposed polygon of an integrated circuit layout; obtaining a plurality of candidate polygon templates from a template library; performing shape matching processing and polygon update iteration processing on the to-be-decomposed polygon and the candidate polygon templates to obtain a shape matching result; and performing polygon decomposition processing on the to-be-decomposed polygon according to the shape matching result to obtain a trapezoidal set for manufacturing a mask after decomposition. According to the scheme of the embodiment of the application, the polygon in the integrated circuit layout can be efficiently decomposed, thereby reducing the decomposition time consumption and improving the universal applicability.

An integrated circuit (IC) device includes an isolation structure extending between two locations in a first direction on a front side of a semiconductor substrate; a transistor including a gate and an MD segment extending between two locations, and the gate and the MD segment being all of the gate and the MD segment located between the two locations and between the isolation structures in the second direction; a front-side gate via electrically connected to all of the front-side gate vias of the gate; and a front side source / drain via electrically connected to all of the front side source / drain vias of the MD segment. All the front gate vias are located at the positions of first and / or second tracks in the first to third layers of tracks extending in the second direction, and the first to third layers of tracks are all the lowermost front metal layer tracks located between the two positions; all front source / drain vias are located at the location of the second and / or third tracks. The embodiment of the invention also provides a manufacturing method of an integrated circuit (IC) device and a generating method of an integrated circuit layout map.

The application discloses a detection area forming method, a crystal grain surface detection method and a crystal grain surface hotspot judgment method. The detection area forming method is to select a characteristic area on an integrated circuit layout and form a detection area from each characteristic area; wherein the characteristic area is used to represent a local area with similar structure, and the size of the local area is in the range of 0.5 microns to 50 microns. The crystal grain surface detection method uses the detection area formed by the detection area forming method to perform shape detection on the crystal grain surface. The crystal grain surface hotspot judgment method judges whether there is a hotspot according to the result of the shape detection. By using the above method, compared with the prior art, the detection compression ratio is higher, and the detection means with high resolution is more conducive to popularization and application on the production line.

The invention relates to the field of integrated circuit layout design, provides a circuit device model parameter extraction and optimization method based on artificial intelligence, and aims at solving the technical problems that a traditional EDA tool is high in artificial dependence, low in optimization efficiency, poor in algorithm adaptability and split in tool. Automatic data interaction among the modules is realized through a standardized API; preprocessing and intention recognition are carried out on the multi-modal input, and user requirements are converted into formatted data; searching similar circuit historical parameters based on the knowledge base and generating a recommendation list; extracting a target curve through an image recognition model and carrying out standardization processing; dynamically matching an optimization algorithm according to circuit characteristics and adjusting hyper-parameters in real time; multi-tool collaborative optimization control is realized, and the parameter search progress is dynamically updated; and outputting the optimal parameter combination and carrying out verification iteration. The method is used for high-precision automatic optimization and full-process closed-loop verification of circuit parameters.

The present application relates to the technical field of integrated circuit layout detection, and particularly relates to a curve layout test pattern generation method and system based on machine learning, comprising: obtaining historical curve layout data and preprocessing to obtain an effective data set; extracting geometric and defect correlation features, and obtaining a feature matrix through correlation analysis and dimension reduction; generating a defect mode label by K-means clustering combined with contour coefficient correction clustering number; inputting the feature matrix and the label into a classification model to output parameters to generate an initial test pattern, and obtaining an optimized test pattern through redundancy and coverage optimization; importing a test system for verification, and if the verification does not meet the standard, the model is retrained, and if the verification meets the standard, the final pattern is output. The present application realizes accurate identification of defect modes with the aid of machine learning, balances detection accuracy and efficiency, improves the applicability of test patterns, and is suitable for integrated circuit curve layout detection.

According to the invention, an integrated circuit arrangement is formed by reducing the injection of charge carriers into a semiconductor substrate. The circuit arrangement comprises a first and second half-bridge connected as a full bridge, wherein the drain terminals of the first transistors and the source terminals of the second transistors are electrically connected. The two parallel-connected source terminals of the second transistors are connected to the first terminal of a two-terminal resistor, while the second terminal of the resistor provides a connection for a negative supply voltage or ground potential. A Zener diode is connected between the source terminal (supply voltage) and the gate terminal of at least one of the first MOS transistors. The transistors are surrounded by at least one guard ring.The guard ring is implemented as a contacted N or P well on the P or N substrate. Around the guard ring, further P or N wells, insulated by means of deep trench structures, are arranged.

An electronic design automation (EDA) tool and system for physical verification of workflow for semiconductor circuit designs, and methods of using the same is described. Generally, the method includes (i) automatic splitting an integrated circuit (IC) layout into a number of windows for parallel processing using a plurality of central processing cores; (ii) extracting parasitic capacitance structures from the IC layout; (iii) generating fill elements for masks to fabricate an IC having the IC layout using a metadata matrix to minimize volume of information and resources needed; and (iv) extraction of parasitic resistance structures from IC layout. In some embodiments, the IC layout is additionally or alternatively split into groups of rules for processing. Other embodiments are also described.

The invention relates to a layout optimization method of an integrated circuit, computer equipment, a storage medium and a product. The layout optimization method is applied to a global layout stage of integrated circuit design, and comprises the following steps: providing an integrated circuit layout which is provided with a plurality of metal layers arranged in a stacked manner, and the metal layers are provided with track consumption objects and area occupation objects; obtaining a track consumption object in the integrated circuit layout, and calculating the actual total consumption of the track consumption object in the wiring track; acquiring a metal layer and an area occupation object in the integrated circuit layout, and calculating the total amount of available resources of a wiring track; and counting the resource distribution of the wiring track based on the total amount of available resources and the actual consumption total amount, calculating the resource exceeding total amount of the wiring track, calculating the diffusive force of the resource distribution on the track consumption object in combination with the resource distribution so as to push the track consumption object to be far away from the congestion area in the integrated circuit layout, and optimizing the integrated circuit layout.

This invention discloses an automatic routing optimization method and apparatus for chips, relating to the field of integrated circuit layout design technology. In this method, the chip is divided into multiple differential grids; the connectivity of the edges and / or diagonals of each differential grid is determined to generate connectivity relationships; candidate paths from the routing start point to the routing end point are determined based on the connectable edges and / or diagonals; differential grids associated with the candidate paths are retained while unrelated differential grids are deleted; the grid size is reduced within the retained area and the filtering is repeated until a preset threshold is met, at which point a pathfinding algorithm is executed to obtain the routing path. This method can reduce the automatic routing search area and improve the routing efficiency of large-scale complex chips.

Methods and systems for determining information for an area having unknown patterns and unknown pattern repeatability are provided. One or more computer systems of the system are configured for detecting first and second polygons in first and second rows, respectively, in a design for a specimen. The first and second rows have first dimensions perpendicular to an edge of a known area in the design from inner boundaries of the rows to outer boundaries of the rows. The computer system(s) are also configured for determining first and second repeating pitches of the first and second polygons, respectively. When the first and second repeating pitches are different from each other, the computer system(s) are configured for determining an outer boundary of the area having the unknown patterns and the unknown pattern repeatability as the outer boundary of the first row.

A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are shifted to align and connect to the power rail and the ground rail of the other one of the standard cells.

The application provides a kind of integrated circuit layout detection method, device and storage medium;Method includes: in layout, determine multi-finger structure, wherein multi-finger structure includes: at least one upper continuous source-drain and at least one upper continuous via, upper continuous source-drain is electrically connected with upper layer metal line by upper continuous via;The number of upper continuous source-drain and the number of upper continuous via are calculated;For multi-finger structure, if the number of its upper continuous source-drain is greater than the number of its upper continuous via, then determine that the multi-finger structure is unqualified multi-finger structure.The application can find design defects in time, thereby improving the yield of chip.

An integrated circuit layout includes a space that is arranged for the integrated circuit layout and includes a plurality of rows extending along a first direction, each of the plurality of rows having a uniform row height along a second direction perpendicular to the first direction. The integrated circuit layout also includes one or more first cell areas arranged in the space, one of the first cell areas being placed within one corresponding row of the plurality of rows; one or more second cell areas arranged in the space, one of the second cell areas being placed within two corresponding adjacent rows of the plurality of rows; and one or more third cell areas arranged in the space, one of the third cell areas being placed partially across three corresponding adjacent rows of the plurality of rows.

The application discloses a kind of digital integrated circuit layout post wire length and line delay collaborative prediction method, comprising: constructing preliminary version heterogeneous graph based on the connection information of circuit netlist;From netlist file and process file, the features used for prediction are extracted;The features extracted are added to the corresponding node and edge of preliminary version heterogeneous graph, to obtain final version heterogeneous graph;Construct prediction model;The constructed prediction model is trained;Final version heterogeneous graph is input into the prediction model that training is completed, and finally the prediction result of wire length and the prediction result of line delay are obtained.The model used in the application introduces multi-task learning framework, considers the collaborative relationship of wire length and line delay, in this case, by the model, wire length and line delay are predicted, not only can reduce the time cost of training and reasoning, improve the prediction efficiency, but also can ensure the deep integration and full use of wire length and line delay related information, overcome the problem that the two indicators are relatively independent in the prior art.

The application discloses a FPGA integrated circuit layout optimization method, device and equipment and a storage medium. The method comprises the following steps: performing a short logic connection line selection operation: selecting a short logic connection line with the lowest Slack value from a short logic connection line set as a selected short logic connection line; wherein the short logic connection line is a logic connection line with a length less than a preset value; the short logic connection line set is: at the beginning, a set of short logic connection lines in the FPGA integrated circuit; performing a first moving operation, and after the first moving operation is performed, removing the current selected short logic connection line from the short logic connection line set, and re-performing the short logic connection line selection operation; through the embodiment of the application, the direct connection optimization of the short logic connection line can be realized in the layout stage.