289 results about "Integrated circuit layout" patented technology

The invention relates to a method for checking spacing in a large-scale integrated circuit layout, which belongs to the technical field of integrated circuit computer aided design, and comprises the following steps: S1, dividing an integrated circuit layout to be processed into a plurality of local layouts according to a preset division rule, including an original local layout and an interference local layout; outwards expanding the edges, determined by a preset division rule, of the interference local layouts to obtain expanded local layouts; s2, checking whether the edges of all the functional parts in all the local layouts meet the constraint condition upper limit corresponding to the selected preset checking rule one by one according to the currently selected preset checking rule so as to screen out the edges meeting the potential conditions; s3, forming associated edge pairs, and screening the associated edge pairs through a filter to obtain associated edge pairs meeting filtering conditions; and S4, carrying out secondary cutting on the associated edge pairs according to the cutting ranges of the associated edge pairs meeting the filtering conditions.

Disclosed in the present application are an integrated circuit routing method and system, and a device and a medium. The method comprises: acquiring an integrated circuit layout model; performing routing area generation processing on the integrated circuit layout model on the basis of a particle swarm optimization algorithm, so as to obtain a routing area; performing routing processing on the routing area on the basis of an improved A* search algorithm, so as to obtain a routing path; on the basis of the routing path, removing a redundant segment, so as to obtain a post-processed path; and performing dictionary conversion processing on the post-processed path, so as to obtain a routing layout. In the embodiments of the present application, a discrete particle swarm optimization algorithm can be used to reduce a routing search space, and a detailed routing area is determined by means of an improved A* search algorithm, thereby further enhancing routing speed, and improving the routing efficiency of an integrated circuit. The embodiments of the present application can be widely applied to the field of integrated circuits.

The invention provides an analog integrated circuit layout method, device and equipment, a medium and an integrated circuit, and the method comprises the steps: obtaining an original layout diagram corresponding to the ith iteration based on the netlist information and a strategy network model of each electronic element needing to be arranged; when it is determined that i does not reach the first preset value, obtaining a value parameter of the original layout diagram corresponding to the ith iteration, updating a model parameter of the strategy network model based on the value parameter of the original layout diagram corresponding to the ith iteration, increasing i by 1, returning to execute the ith iteration calculation, and when it is determined that i reaches the first preset value, updating the model parameter of the strategy network model based on the value parameter of the original layout diagram corresponding to the ith iteration. Determining the original layout diagram corresponding to the ith iteration as a first intermediate layout diagram of each electronic component; and based on the netlist information of each electronic component, correcting the first intermediate layout diagram to obtain a target layout diagram of each electronic component. According to the invention, the reasonability and efficiency of the analog integrated circuit layout are effectively improved, and an automatic solution is provided for the analog integrated circuit layout.

The invention discloses an integrated circuit layout design teaching assistance method, and relates to the field of integrated circuits, and the method comprises the steps: receiving a circuit diagram creation instruction, and generating a circuit diagram drawing interface according to the circuit diagram creation instruction; identifying types and connection relations of circuit devices in the circuit diagram drawing interface; according to the identified circuit device type and the connection relation, generating a corresponding circuit schematic diagram data structure by adopting a graph neural network GNN algorithm based on message passing; converting the schematic circuit diagram data structure into a layout data structure; the layout data structure comprises geometric parameters and layout position data of layout elements; and according to the layout data structure, generating a circuit layout by using a reinforcement learning algorithm based on a graph neural network. In view of low integrated circuit layout design efficiency in the prior art, the design efficiency is improved by constructing a multi-objective optimized Markov decision process, utilizing deep learning and reinforcement learning algorithms and the like.

The invention belongs to the related technical field of integrated circuit design, and discloses an integrated circuit design process collaborative optimization method and system, and the optimization method comprises the steps: S1, randomly generating a plurality of groups of process parameters; s2, TCAD simulation is carried out, and an electrical characteristic curve of the device is obtained; s3, extracting electrical characteristics and inputting the electrical characteristics into the intelligent parameter extraction model to obtain compact model parameters; s4, inputting the compact model parameters into the SPICE model, and generating an integrated circuit layout by using an automatic layout generation system; s5, taking the optimized circuit performance index as an optimization target, and adopting a Bayesian optimization method to generate an optimal process parameter of a next iteration round; and S6, judging whether an iteration termination condition is met or not, if not, skipping to S2, and if yes, outputting the current process parameters. According to the method, the process / design barrier can be broken, it is ensured that the process development and the circuit design process can be collaboratively carried out, the whole optimization process is completely automatic, and the high-precision and high-efficiency collaborative optimization process is achieved.

The invention relates to the technical field of circuit wiring, in particular to an AI-based circuit wiring system, method, medium and equipment, and the system comprises an input module, a preprocessing module, a deep learning module, a topology loss calculation module, a candidate layout generation module, a graphical user interface module, a man-machine interaction module and an output module. The input module is used for receiving each device of an analog circuit and physical size information thereof, and describing a description file of a topology constraint relationship between device pairs; the preprocessing module performs normalization processing on the size information of the device; the deep learning module is a graph structure neural network, and an output layer of the graph structure neural network outputs two-dimensional plane position coordinates corresponding to the devices; the topology loss calculation module defines a topology loss function and calculates an error value in a graph structure neural network training process, and the candidate layout generation module automatically generates a plurality of device candidate layout schemes meeting the topology loss function based on the trained graph structure neural network; the graphical user interface module is used for displaying candidate layout schemes and the error component value of each scheme; the man-machine interaction module provides a layout fine tuning function through a graphical user interface; the output module is used for outputting a final device layout scheme after manual fine tuning or automatic generation; according to the invention, the design efficiency and quality of the layout of the analog integrated circuit are improved, and the requirements of modern integrated circuit design for rapid iteration and efficient layout are met.

The invention discloses a line length and line time delay collaborative prediction method after digital integrated circuit layout. The method comprises the following steps: constructing a primary version heterogeneous graph based on connection information of a circuit netlist; extracting features for prediction from the netlist file and the process file; adding the extracted features to corresponding nodes and edges of the initial-edition heterogeneous graph to obtain a final-edition heterogeneous graph; constructing a prediction model; the constructed prediction model is trained; and inputting the final-edition heterogeneous graph into the trained prediction model, and finally obtaining a prediction result of the line length and a prediction result of the line time delay. The model adopted by the invention introduces a multi-task learning framework, considers the collaborative relationship between the line length and the line time delay, and predicts the line length and the line time delay through the model under the condition, so that the time cost of training and reasoning can be reduced, the prediction efficiency can be improved, deep fusion and full utilization of related information of the line length and the line time delay can be ensured, and the method has a good application prospect. The problem that the two indexes are relatively independently processed in the prior art is solved.

Embodiments of the present disclosure provide methods, systems, and computer program products for implementing intelligent timing aware metal fill optimization for an IC layout. The disclosed methods enable fill tooling to identify the existing metal tile density and provide timing-aware metal fill insertion to specifically target density requirements and enable effective timing characteristics of signal path nets.

Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Methods for automated routing in an an integrated circuit layout design (322) using artificial intelligence (AI) and corresponding systems and computer-readable mediums. A method includes receiving (402) routing requirements (324), receiving (404) an unrouted layout design (322), and receiving (406) an AI model (306). The method includes creating (408) a routing strategy for the unrouted layout design (322) using the AI model (306) and the routing requirements (324). The method includes creating (410) a physical routing plan based on the routing strategy to produce a routed layout design (312). The method includes storing (412) the routed layout design, wherein a physical part can thereafter be manufactured (414) according to the routed layout design.

The invention discloses an SRAF placement effect evaluation method and device, equipment and a medium, and relates to the technical field of layout correction, and the method comprises the steps: obtaining an SRAF placement rule file written by a user, and carrying out the analysis of the SRAF placement rule file, so as to recognize the position information, type information, quantity information and priority information of an SRAF graph in an integrated circuit layout, so as to obtain SRAF feature information; performing effect evaluation on the SRAF feature information by using a preset evaluation rule to obtain an effect evaluation result of each piece of information; and according to an effect evaluation result, outputting a defect problem currently existing in the SRAF placement rule file, and prompting a user to carry out design adjustment on an SRAF graph. The whole evaluation period is shortened, a basis can be provided for subsequent SRAF graphic design adjustment more quickly, and the speed of integrated circuit process development verification is effectively increased.

The invention relates to the technical field of integrated circuit reliability analogue simulation, in particular to an analogue simulation system and method applied to an integrated circuit. The method comprises the following steps: acquiring an integrated circuit layout and carrying out circuit topological structure datamation on the integrated circuit layout to obtain an oxide layer area grid chart; performing stress distribution mapping generation on the integrated circuit according to the oxide layer region grid chart to obtain a region stress state matrix; performing electric field-temperature collaborative analysis according to the regional stress state matrix to obtain a random fluctuation factor matrix; performing time sequence damage accumulation calculation according to the random fluctuation factor matrix to obtain a time sequence damage state set; and performing damage state feedback adjustment on the time sequence damage state set to obtain a time-varying damage evolution graph. According to the method, the fragile performance indexes and areas of the integrated circuit are identified, and the comprehensive circuit performance degradation characteristic spectrum is generated, so that a scientific basis is provided for reliability design and performance optimization of the integrated circuit.

The invention provides an integrated circuit layout classification method and system, a medium, a program and an electronic terminal, key coordinate points are obtained by identifying graphic units in a to-be-classified layout and extracting contour features, great dimension reduction of data is realized while key geometric features are reserved, the calculation complexity is remarkably reduced, and the processing efficiency is improved. Furthermore, the key coordinate points are mapped and aligned to the grid points according to a preset grid step length, a physical tolerance mechanism is constructed, and coordinate jitter introduced by precision limitation or process errors is effectively eliminated. According to the method, the graphs with the same topology but fine difference in coordinates can be accurately classified, the robustness of the algorithm to process deviation is remarkably improved, fragmentation of the classification result is avoided, and the classification effect is good.

Predicting local layout effects using a variational autoencoder with integrated regression and classification network including identifying a vector of features and a vector of output metrics from a dataset; performing basic training of a neural network machine learning variational autoencoder (VAE) combined with a regression network using the vector of features and the vector of output targets constrained to a latent space of the VAE; performing interpolation training of the VAE and combined regression network; determining a set of influential features of an integrated circuit layout based on an input gradient using an output of the VAE and combined regression network with interpolation training; using the set of influential features as input into a parallel neural network to generate a function for each influential feature; and creating a compact model to calculate local layout effects based on the functions for each influential feature.

The invention discloses an integrated circuit layout verification method and device, and belongs to the technical field of integrated circuit design, and the method comprises the steps: obtaining the arrangement information of a selected target unit from an integrated circuit layout; performing external expansion processing on the to-be-detected metal wire of the target unit according to a design rule spacing requirement to generate an auxiliary layer pattern; copying the auxiliary layer graph according to the arrangement information to form an auxiliary layer graph set covering all target unit areas; performing Boolean operation on the auxiliary layer graph set and the global metal wire on the same layer to generate an identification layer; when the identification layer is empty, determining that the to-be-detected metal wire meets the design rule spacing requirement; and when the identification layer is not empty, outputting the interval violation area indicated by the identification layer. According to the method and the device, efficient and accurate interval violation detection is realized, and the automation degree and the reliability of design rule inspection are improved.

The invention relates to the technical field of integrated circuits, in particular to an integrated circuit layout modular layout method and system based on AI matching. The method selects a target module; the target module is converted to an IC layout area, an initial circuit layout is generated, and an external rectangle and module internal pins are extracted; determining an initial coordinate of an interface point according to a shortest physical path from an internal pin of each module to an external rectangle to which the module belongs; determining a theoretical shortest path according to the respective displaceable range in the interface point combination; determining a path adaptation degree according to the actual connection path and the theoretical shortest path; the overall layout fitness is determined by combining the distribution dense characteristics of the actual connection paths; taking the overall layout fitness as an optimization target, performing iterative optimization through a genetic algorithm until the overall layout fitness converges, and outputting an optimized circuit layout; and inputting the optimized circuit layout into a pre-training AI engine, and outputting a final circuit layout, so that the expandability of layout design is improved.

The invention relates to the technical field of module splicing layout, and provides an automatic integrated circuit layout area optimization method which comprises the following steps: S1, determining at least two preset modules, and defining a plurality of different parameter combinations including quantity, width and height for all the preset modules; s2, selecting any one of limits including a width limit or a height limit when the circuit layout is spliced, and matching and combining different parameter combinations of the preset modules for splicing; s3, according to the selected limiting mode, the row number and the column number of each prediction module are calculated based on the matching combination of each preset module; and S4, calculating and scoring each matching combination according to a preset rule, and taking the matching combination with the highest score as a final circuit layout splicing scheme. According to the technical scheme, based on a height or width matching algorithm between different modules in the integrated circuit layout, the matching problem during multi-module splicing layout in the layout is solved, and the overall layout area is optimized.

The invention relates to an MDAC circuit of a pipelined analog-to-digital converter. The technical problems that in the prior art, an assembly line ADC is large in stage number and large in delay are solved, and jitter signal injection is facilitated. According to the technical scheme, the circuit comprises a first sampling capacitor array, a second sampling capacitor array, a first feedback capacitor array, a second feedback capacitor array and an operational amplifier. According to the further technical scheme, the circuit further comprises a first bridge capacitor, a first correction capacitor array, a second bridge capacitor and a second correction capacitor array. According to the technical scheme, the operational amplifiers of the adjacent sub-conversion stages are shared, so that one operational amplifier is saved, and the overall power consumption of the ADC is effectively reduced. The single conversion stage can adopt high-resolution conversion processing, the serial stage number of the whole assembly line analog-to-digital converter is reduced, and the assembly line delay is reduced. The capacitors of two adjacent sub-conversion stages are shared, so that the number of the capacitors is reduced, and the layout area of an integrated circuit is reduced.

Aspects of the disclosure are directed to automatically determining floor planning in chips, which factors in memory macro alignment. A deep reinforcement learning (RL) agent can be trained to determine optimal placements for the memory macros, where memory macro alignment can be included as a regularization cost to be added to the placement objective as a RL reward. Tradeoffs between the placement objective and alignment of macros can be controlled by a tunable alignment parameter.

The application provides a via hole design method of an integrated circuit layout, comprising the following steps: searching for a source end and a drain end of a via hole in the layout; judging whether the via hole can be used as a to-be-expanded via hole region; if yes, moving the via hole in four directions by a certain distance; if the moved via hole is located in an active region and the top of the moved via hole has a metal layer, and the metal layer on the top of the moved via hole is the same layer as the metal layer on the top of the original via hole, then expanding the via hole in the to-be-expanded via hole region; if the moved via hole is located in the active region and the top of the moved via hole does not have a metal layer, then extending the metal layer on the top of the original via hole to the place of the moved via hole, if the extended metal layer is the same layer as the metal layer near the moved via hole or if the extended metal layer is not the same layer as the metal layer near the moved via hole but meets a certain spacing, then expanding the via hole in the to-be-expanded via hole region.

The present invention relates to an integrated circuit layout generation method and system, wherein the method includes receiving a layout diagram of the IC device, wherein the IC layout diagram includes: a gate region having a width on an active area; and a gate through hole located at a position along the width. The width is divided into a plurality of width segments using the position, an effective resistance of the gate region is calculated based on the plurality of width segments, and the effective resistance is used to determine whether the IC layout diagram complies with design specifications.

The application provides a processing method of integrated circuit layout data in GDSII format and a computer storage medium, and the processing method comprises the following steps: establishing a rectangular coordinate system, and placing a rectangular layout with a multiple-point collinear condition in the rectangular coordinate system; taking an arbitrary point on the rectangular layout as an initial point to start traversal, and acquiring the coordinates of the traversed points; recording the vertex coordinates of the rectangular layout, and deleting the redundant point coordinates located on the edges of the rectangular layout; stopping the traversal and outputting the recorded vertex coordinates when the traversal is restarted from the initial point or the vertex recorded in the first traversal. Compared with the prior art, the application provides a processing method of integrated circuit layout data in GDSII format, which can compress the layout data with a multiple-point collinear condition, thereby reducing the size of the layout data and saving the storage space.

The application discloses a method and device for feature extraction of integrated circuit layouts and a non-transitory computer readable storage medium thereof. A circuit pattern layout file to be implemented on a semiconductor wafer is obtained from a memory. Data preparation and preprocessing is performed on the circuit pattern layout file. A deep learning model is established and trained. Transfer learning and model fusion are performed on the deep learning model. The deep learning model is used to perform image segmentation and feature extraction on the circuit pattern layout file to extract a plurality of features. Density parameters and total perimeter parameters of the plurality of features are calculated.

This invention provides a method, apparatus, medium, and terminal for transferring integrated circuit layout process information. The method includes: acquiring first-level information of each layer in a first layout and second-level information of each layer in a second layout; acquiring meaning information of the first-level information and the second-level information; matching the first-level information and the second-level information based on the meaning information to obtain multiple layer information pairs; exporting the first-level information as language text format information; matching the second-level information corresponding to the language text format information in the layer information pairs; replacing the language text format information according to the matched second-level information to obtain target text information; and generating a target process layout based on the target text information. This invention can quickly realize the process transfer of two integrated circuit layouts, improve layout transfer efficiency, and reduce costs.

The invention provides a face-to-face bonding heterogeneous integrated circuit layout method, a face-to-face bonding heterogeneous integrated circuit layout system, face-to-face bonding heterogeneous integrated circuit layout equipment and a medium, which are applied to the technical field of integrated circuit design automation (EDA). The method comprises the following steps: firstly, based on a connection netlist of multiple layers of bare chips, a bare chip layout rule and a unit bonding process library, carrying out layout position iteration on standard units in each layer of bare chips by utilizing a vectorized analysis layout device, and distributing initial solutions between positions of the units on the bare chips to which the units belong and face-to-face bonding positions required by a cross-bare chip wire net; and legalizing each layer of bare chip unit to obtain an optimal region of the bonding position, and traversing all units and the bonding position to obtain a final allocation result.

The invention provides an integrated circuit layout splitting method and a related product. The splitting method comprises the following steps: constructing a conflict graph of the layout according to a preset spacing rule; performing structure search in the conflict graph to obtain a plurality of equivalent identification structures, and determining a plurality of groups of equivalent nodes in the nodes of the plurality of equivalent identification structures; under the condition that a conflict edge is connected between two equivalent nodes in any group of equivalent nodes, determining that the conflict graph is unsolvable; performing conflict solution on the conflict graph; and splitting the conflict graph into a plurality of split layouts of preset split layers. According to the method, whether the conflict graph contains the complex and unsolvable conflict relation or not can be quickly and effectively judged, the conflict relation is effectively optimized, and then normal dyeing and splitting of the layout are achieved.

The invention provides an OPC processing method of an integrated circuit layout and computer equipment. The OPC processing method for the integrated circuit layout comprises the following steps: carrying out partitioning analysis on a target integrated circuit layout to obtain a plurality of local areas; constructing features for each local area; reasoning and judging all the local areas by using a pre-trained learning model, wherein the learning model establishes a mapping relationship between features and classification results; and removing the local areas which do not need to be subjected to OPC processing, screening out the local areas which need to be subjected to OPC processing, and outputting a result. According to the scheme, the limitation of a traditional layout screening mode based on rules can be broken through, and precise screening of empty local areas and efficient elimination of invalid calculation are achieved; the adaptability of a learning model to a complex layout scene is improved, and core support is provided for efficiency optimization and precision guarantee of an OPC process.

The application discloses a kind of integrated circuit clock tree optimization method and system based on graph neural network and reinforcement learning, comprising the following steps: step S1: construct graph structure generation module, according to integrated circuit layout to construct the graph structure with register as node, with timing path as edge;Step S2: construct GNN feature extraction module, for the high-dimensional graph embedding representation of the feature vector of register node according to the graph structure constructed;Step S3: construct reinforcement learning network decision module, for receiving current node embedding representation vector and generating specific action after data processing;Step S4: construct timing verification and reward calculation module, for evaluating the updated circuit state, and obtaining reward signal to be used for the training of reinforcement learning network decision module;Step S5: constantly train reinforcement learning network decision module, until training is completed, finally obtain optimized register node feature vector, that is, optimized clock tree.

An integrated circuit layout includes a first and a second standard cells abutting along a boundary line. The boundary line and a first active region of the first standard cell include a distance D1. A first gate line on the first active region protrudes from the first active region by a length L1. The boundary line and a second active region of the second standard cell include a distance D2. A second gate line on the second active region protrudes from the second active region by a length L2. Two first dummy gate lines and two second dummy gate lines are disposed at two sides of the first active region and the second active region and are away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1≤D1−S, L2≤D2−S, and D1≠D2.