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A thin film transistor includes a substrate, and a pair of source/drain electrodes (i.e., a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films are provided such that each coats at least a part of one of the source/drain electrodes. The low resistance conductive thin films define a gap therebetween. An oxide semiconductor thin film layer is continuously formed on upper surfaces of the pair of low resistance conductive thin films and extends along the gap defined between the low resistance conductive thin films so as to function as a channel. Side surfaces of the oxide semiconductor thin film layer and corresponding side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel.

MEMS packaging schemes having a system-on-package (SOP) configuration and a system-on-board (SOB) configuration are provided. The MEMS package comprises one or more MEMS dies, a cap section having one or more integrated circuit (IC) dies, and a packaging substrate or a printed circuit board (PCB) arranged in a stacking manner. Vertical connectors, such as through-silicon-vias (TSVs), are formed to provide short electrical connections between the various components. The MEMS packaging schemes enable higher integration density, reduced MEMS package footprints, reduced RC delays and power consumption.

A nonvolatile memory transistor having a poly-silicon fin, a stacked nonvolatile memory device having the transistor, a method of fabricating the transistor, and a method of fabricating the device are provided. The device may include an active fin protruding upward from a semiconductor substrate. At least one first charge storing pattern on a top surface and sidewalls of the active fin may be formed. At least one first control gate line on a top surface of the at least one first charge storing pattern may be formed. The at least one first control gate line may intersect over the active fin. An interlayer dielectric layer may be formed on the at least one first control gate line. A poly-silicon fin may be formed on the interlayer dielectric layer. At least one second charge storing pattern on a top surface and sidewalls of the poly-silicon fin may be formed. At least one second control gate line on a top surface of the at least one second charge storing pattern may be formed, and the at least one second control gate line may intersect over the poly-silicon fin.

A micro air vehicle (MAV) comprises features that emulate insect-like topology and flight, including a dangling three part body (100a, 100b, 100c), wing-like dual side rotors (107, 107a) positioned to either side on rotor arms (103) providing tilt and teeter motions to vector thrust and allow crawling along improved surfaces, and elevators (101) that approximate the center of gravity and center of pressure control employed by insects via the inertial reaction and aerodynamic influence of a repositionable abdomen. Control, sensing, surveillance, and payload elements (114), (401), (402), (403), (404), (405), and (407) enable transmission of surveillance and engagement of an emerging target. Left and right perch hangers and grapples (112, 112a) allow perching on various structures, and energy storage (504) and (505) combined with power line (500) and solar (502) energy scavenging circuitry allow extended loiter and mission duration by replenishing onboard energy supplies.

The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention adjusts a threshold voltage with a common contact, which has a portion outside the source or drain region extending to the back-gate region and provides an electrical contact of the source or drain region and the back-gate region, which leads to a simple manufacturing process, an increased integration level and a lowered manufacture cost. Moreover, the asymmetric design of the back-gate structure further increases the threshold voltage and improves the performance of the device.

A system for providing a wide range of telecommunications initiated data fulfillment services in which a multi-function code, such as “*#” (star, pound), input into an originating telecommunications device, such as a conventional land-line or wireless telephone, triggers the treatment of the input sequence as a multi-function code service request rather than a dialed directory number. The multi-function code is followed by an input data string to complete the multi-function code service request, which the user typically enters into the telecommunications device just like a conventional telephone call, except that the input string begins with the multi-function code. The telecommunications system recognizes the multi-function code as a trigger, and in response takes one or more actions, such as automatically terminating the call to an announcement and routing a data message to a data fulfillment center, which responds to the message by implementing a response action indicated by the multi-function code service request. For example, the data fulfillment center may respond by transmitting a message over a wireless data network or the Internet to implement a service, such as activation of a vending machine, remote control of device, delivery of a message over the Internet or wireless data network, initiation of an interactive Internet session with the originating device, or a wide range of other services. In addition, a charge for this service may be automatically charged to an account associated with the originating telecommunications device, which may be billed separately or incorporated on the user's conventional monthly telecommunications invoice.

In an active matrix semiconductor display device in which pixel TFTs and driver circuit TFT are formed on the same substrate in an integral manner, the cell gap is controlled by gap retaining members that are disposed between a pixel area and driver circuit areas. This makes it possible to provide a uniform cell thickness profile over the entire semiconductor display device. Further, since conventional grainy spacers are not used, stress is not imposed on the driver circuit TFTs when a TFT substrate and an opposed substrate are bonded together. This prevents the driver circuit TFTs from being damaged.

A package array and its package unit of flip chip LED are proposed, wherein an LED chip is mounted on a ceramic material capable of enduing the eutectic temperature of the fabrication process for packaging. Next, metal wires are directly distributed on the ceramic material to finish an LED package unit, or a plurality of LEDs are serial/parallel connected with metal wires on the ceramic material to finish a high density package array. Because the ceramic material has a good thermal expansion match and a good thermal conductivity and the LED chip itself has a high reflective index match, the light emission characteristic and heat-radiating effect of the packaged LED can be effectively improved.

Within one pixel element 200, two display circuits corresponding to the analog display mode and the digital display mode are disposed such that they are adjacent to each other. One of these two display circuits can be selected through the circuit selection circuits 40 or 43. Since the high voltage power line 150 of the retaining circuit 110, which is used under the digital display mode, also performs as the signal selection line 88, it is possible to have the high density integration of the pixel element 200. Also, the bias voltage Vsc supplied through the selection storage capacitor line 81 is same as the signal A. Therefore, the storage capacitor line 81 is connected to the drain of the TFT 122 of the signal selection circuit 120 so that the signal line 82 for supplying the signal A can be omitted. Thus, the high-density integration of the pixel element 200 can be achieved.

The present invention can promote the large capacity, high performance and high reliability of a semiconductor memory device by realizing high-performance of both the semiconductor device and a memory device when the semiconductor memory device is manufactured by stacking a memory device such as ReRAM or the phase change memory and the semiconductor device. After a polysilicon forming a selection device is deposited in an amorphous state at a low temperature, the crystallization of the polysilicon and the activation of impurities are briefly performed with heat treatment by laser annealing. When laser annealing is performed, the recording material located below the silicon subjected to the crystallization is completely covered with a metal film or with the metal film and an insulating film, thereby making it possible to suppress a temperature increase at the time of performing the annealing and to reduce the thermal load of the recording material.

A method of generating a signal comprising providing a capacitive touch sensor pad including a matrix of X and Y conductors, developing capacitance profiles in one of an X direction and a Y direction from the matrix of X and Y conductors, determining an occurrence of a single gesture through an examination of the capacitance profiles, the single gesture including an application of at least two objects on the capacitive touch sensor pad, and generating a signal indicating the occurrence of the single gesture.

Provided are phase change random access memory (PRAM) devices and methods of operating the same. The PRAM device may include a switching device, a lower electrode, a lower electrode contact layer, a phase change layer and/or an upper electrode. The lower electrode may be connected to a switching device. The lower electrode contact layer may be formed on the lower electrode. The phase change layer, which may include a bottom surface that contacts an upper surface of the lower electrode contact layer, may be formed on the lower electrode contact layer. The upper electrode may be formed on the phase change layer. The lower electrode contact layer may be formed of a material layer having an absolute value of a Seebeck coefficient higher than TiAlN. The Seebeck coefficient of the lower electrode contact layer may be negative. The material layer may have lower heat conductivity and/or approximately equivalent electrical resistance as TiAlN.

According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.

Biosensor circuit arrangement including a substrate, a sensor element formed in or on a surface region of the substrate with a physical parameter, which is coupled to a substance to be examined, the type of coupling having a resistive component, the sensor element having an electrically conductive sensor electrode that is coupled to the substance to be examined, the sensor element having a measuring transistor the gate terminal of which is coupled to the electrically conductive sensor electrode, and the physical parameter being the threshold voltage of the measuring transistor, and a calibration device formed in or on the substrate, the calibration device being set up such that it is used to at least partly compensate for an alteration of the value of the physical parameter of the sensor element.

A matrix-addressed system includes a system substrate and an array of pixels arranged in rows and columns disposed on the system substrate. A column-control circuit provides information to or receives information from the pixels. The column-control circuit includes a separate column-driver circuit connected to each column of pixels that provides information in common to all of the pixels in the column or receives information in common from all of the pixels in the column. A row-select circuit likewise disposed on the system substrate includes a serial shift register having a number of row storage elements equal to or larger than the number of rows in the array of pixels. Each row storage element in the shift register has a row-select line connected to all of the pixels in a row.

An autonomous driver assistance system is integrated with a vehicular control system to constantly detect ambient road environment of the vehicle, identify a vehicle ahead with same driving route to a destination, and follow the vehicle ahead by autonomous driving to the destination. Signals of direction indicators of the vehicle ahead can be recognized to determine a driving direction and driving state of the vehicle ahead beforehand, thereby reducing the chances of emergency brake and collision and increasing driving efficiency. Without expensive radar detection equipment, the present invention can be easily integrated with a vehicular control system to tackle the high installation cost and integration difficulty of conventional autonomous driver assistance apparatuses.

The invention relates to an integrated optical sensor package. The integrated optical sensor package comprises a package substrate, an ambient light sensor, a proximity optical sensor, an image sensor and a package cover, wherein the package substrate is positioned at the bottom; the ambient light sensor, the proximity optical sensor and the image sensor are arranged on the package substrate; and the package cover is mutually sealed with the package substrate so that a package housing is formed. The integrated optical sensor package provided by the invention can reduce the package volume and reduce the manufacturing cost.