4643 results about "Driver circuit" patented technology

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A voltage mode driver circuit has a first driver slice has a pullup structure that includes a first transistor and a second transistor and a pulldown structure that includes a third transistor and a fourth transistor. The first transistor has a gate that receives a first version of a first data signal. The second transistor has a gate that receives a first version of a second data signal. The third transistor has a gate that receives a second, complementary version of the first data signal. The fourth transistor has a gate that receives a second, complementary version of the second data signal. The first data signal encodes data in a first mode and enables the pullup and pulldown structures in a second mode of operation. The second data signal encodes data in the second mode of operation and enables the pullup and pulldown structures in the first mode of operation.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

The invention belongs to the technical field of display driving, and particularly relates to a noise reduction circuit and a gate driving circuit, and the noise reduction circuit comprises a first noise reduction module which is used for carrying out the noise reduction processing of the voltage of a driving control node, a driving output end and a stage transmission output end; the first noise reduction module is also used for enabling a noise reduction transistor in the first noise reduction module to be in a reverse bias state under the action of a second noise reduction control signal; the second noise reduction module is used for carrying out noise reduction processing on voltage on the driving control node, the driving output end and the stage transmission output end; the second noise reduction module is also used for enabling a noise reduction transistor in the second noise reduction module to be in a reverse bias state under the action of the first noise reduction control signal; according to the noise reduction circuit, the noise reduction transistors in the two groups of noise reduction modules are in the reverse bias state when not working, so that the forward bias state of the noise reduction transistors in alternate working is counteracted, the problem that the threshold voltage of the noise reduction transistors drifts is solved, and the noise reduction stability of the noise reduction circuit is improved.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

Power switch device includes a wide-bandgap semiconductor switch, and a gate driver. The gate driver includes a driver circuit and a diagnostic circuit. The driver circuit is configured to provide a driver signal to control the wide-bandgap semiconductor switch. The diagnostic circuit is configured to sense an electrical characteristic of the wide-bandgap semiconductor switch, and perform a diagnostic test for the wide-bandgap semiconductor switch in response to the electrical characteristic of the wide-bandgap semiconductor switch.

A power switching device is disclosed. The power switching device includes a cascode switching circuit comprising a normally-on transistor and a normally-off transistor provided in a cascode topology. The power switching device also includes a gate driver circuit configured to apply a positive bias voltage at a respective gate terminal of the normally-on transistor under a normal operating condition, and to apply a negative bias voltage at the respective gate terminal of the normally-on transistor under a short circuit condition.

The invention belongs to the technical field of display driving, and particularly relates to a noise reduction circuit, a gate driving circuit and a display panel, and the noise reduction circuit comprises a noise reduction control unit, a threshold compensation unit and a noise reduction execution unit. The noise reduction control unit is used for outputting a noise reduction signal at the non-scanning time of the scanning stage of the current-stage gate driving module under the action of the noise reduction control signal output by the noise reduction control end and the voltage on the driving control node; the threshold compensation unit is used for compensating the noise reduction signal according to the threshold voltage of a transistor in the noise reduction execution unit to obtain a noise reduction compensation signal; the noise reduction control signal is compensated through the threshold compensation unit according to the threshold voltage of the transistor in the noise reduction execution unit, the problem of unstable noise reduction caused by threshold voltage drift of the noise reduction transistor is solved, and the noise reduction stability of the noise reduction circuit is improved.

The invention belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel, the gate driving circuit comprises N cascaded GOA circuit units, the nth GOA circuit unit comprises a first pull-down control module, the control end of the first pull-down control module is connected with a first pull-down signal end, and the control end of the first pull-down control module is connected with a second pull-down signal end; the output end of the first pull-down control module is respectively connected with the control voltage end, the stage transmission output end and the driving output end of the nth stage GOA circuit unit, and the first pull-down control module is used for discharging the voltage on the control voltage end, the stage transmission output end and the driving output end and maintaining the voltage to a second target voltage; according to the display panel, the problem of unstable Q point potential caused by leakage current is solved, the GOA charging effect is effectively improved, the design of a narrow-frame product is facilitated, and the product competitiveness of the display panel is improved.

A half-bridge driver circuit periodically repeats switching cycles by closing a first FET via a first drive signal, detecting an instant when a current flowing through the first FET reaches a threshold and then opening the first FET and closing a second FET via a second drive signal. An error amplifier generates a control voltage by comparing a feedback signal with a reference signal, and a variable current generator generates a first current as a function of the control voltage. The error amplifier includes a proportional-integral controller, and a slope compensation circuit that generates a second current as a ramp signal. The threshold is generated by subtracting the second current from the first current. In response to detecting the instant, the second current is sampled and a signal indicative of the threshold is generated by subtracting the sampled second current from the first current.

The invention belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel, the gate driving circuit comprises N cascaded GOA circuit units, and the nth GOA circuit unit comprises a control voltage maintaining module used for maintaining the control voltage of the n + 1th GOA circuit unit under the action of the pre-charging voltage on the control voltage end of the (n + 1) th GOA circuit unit, maintaining the control voltage end of the nth GOA circuit unit at a first target voltage; the output module is used for outputting a gate driving signal under the action of a first target voltage on a control voltage end and a clock signal output by a clock signal end; the stage transmission module is used for outputting a stage transmission signal for pre-charging the control voltage end of the (n + i) th stage GOA circuit unit under the action of a target voltage on the control voltage end and a clock signal output by the clock signal end; the problem that the potential of the Q point is unstable due to leakage current is solved, the falling edge time of the gate driving signal can be greatly shortened, and the display effect of a picture is improved.

The invention belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel, the gate driving circuit comprises a plurality of clock signal lines and cascaded N driving units, and the nth-level driving unit further comprises a pre-charging module used for pre-charging the nth-level driving unit under the action of a level transmission signal of the (n-i) th-level driving unit, the driving control node is charged through a first driving signal of the (n-i) th-stage driving unit; the output module is used for outputting a first driving signal through the first driving output end and outputting a second driving signal through the second driving output end under the action of the control voltage on the driving control node; according to the gate driving circuit, the number of the driving units can be reduced by half on the premise that the number of the output signals is the same through the mode that the first-stage driving unit outputs the two driving signals, so that the number of transistors in the gate driving circuit is greatly reduced, a narrow-frame product can be achieved, meanwhile, the cost of a panel is reduced, and the stability of the panel is improved.

The present disclosure provides a pixel driving circuit and a display panel, including a driving transistor connected in series with a light emitting element between a first power supply line and a second power supply line; a data transistor electrically connected to a gate of the driving transistor; a boost module configured to be loaded with a boost input signal, where an output terminal of the boost module is electrically connected to the gate of the driving transistor to enable the voltage of the gate of the driving transistor to boost from the first voltage to the second voltage, and the first capacitor and the second capacitor are connected in series between the first wiring and the gate of the driving transistor.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

An integrated structure for an optoelectronic device and a method of fabricating an integrated structure for an optoelectronic device. The method comprises the steps of providing a complementary metal-oxide-semiconductor, CMOS, backplane comprising a driver circuit for the optoelectronic device; and providing a plurality of optical elements on the CMOS backplane, wherein the plurality of optical elements are based on a material system different from CMOS and are disposed in different device layers; wherein a first bonding dielectric is provided between the CMOS backplane and a first one of the different device layers for monolithic integration; and wherein a second bonding dielectric is provided between respective ones of the different device layers for monolithic integration, the second bonding dielectric being transparent.

The invention discloses a gate driving circuit and a display panel, and the gate driving circuit comprises a plurality of cascaded gate driving units, and each gate driving unit at least comprises a first cascade unit which is connected with the gate driving unit of the previous stage; the first output unit is connected with the first cascade unit and is used for controlling and outputting a scanning signal according to a cascade signal of the first cascade unit; the scanning signal comprises a turn-on voltage and a turn-off voltage; the overvoltage output unit is connected with the first cascade unit and is used for outputting an overvoltage scanning signal according to a cascade signal of the first cascade unit after the first output unit outputs the starting voltage; wherein the overvoltage scanning signal is greater than the cut-off voltage of the scanning signal. Through the circuit, the blank time is shortened, and the circuit is suitable for a high-refresh panel.

The present disclosure provides a gate driving circuit and a display panel. by the control of one of the fourth node, the output end of the second output module, and the first node of the shift register of the next stage, the voltage regulating module may utilize a low voltage signal to stabilize or reduce the gate voltage of the second transistor, so that the second transistor is stable or preferably in the cut-off state to reduce the leakage current. In this way, voltage level of the second gate driving signal can be maintained at a high voltage level or a pulse amplitude.

The invention discloses an integration and optimization method of a multilayer circuit board in a photovoltaic inverter, and the method comprises at least seven layers of functional stacked structures which are an electromagnetic shielding layer, a power device layer, a first insulating dielectric layer, a control circuit layer, a second insulating dielectric layer, a heat dissipation substrate layer and a mechanical strengthening layer from top to bottom in sequence. Wherein the power device layer adopts a three-dimensional embedded packaging technology to integrate an IGBT module and a SiC MOSFET module, and a gate drive circuit of the power device layer is embedded into a first insulating dielectric layer in a coplanar waveguide structure; the heat dissipation substrate layer is provided with a micro-channel array with gradient apertures, and the inner wall of each micro-channel is subjected to anodic oxidation treatment to form an Al2O3 ceramic layer with the thickness of 20-50 microns.

An electronic component. The electronic component includes a base; a first semiconductor device attached to the base and having: a first Gallium nitride (GaN)-based switch having a first gate, a first source and a first drain, the first gate arranged to control a current flow between the first source and the first drain; a second GaN-based switch having a second source, a second gate and a second drain, the second gate coupled to the first gate, and the second drain coupled to the first drain. In one aspect, the electronic component also includes a second semiconductor device attached to the base and having: a logic circuit coupled to the second source and arranged to detect a magnitude of the current flow; and a driver circuit coupled to the first and second gates, the driver circuit arranged to control on and off states of the first and second GaN-based switches.

A driver circuit for controlling a high-power switch. The driver circuit comprises a flyback converter having a positive output rail and a negative output. The driver circuit also comprises: a driving stage that is connected between the positive output rail and the negative output rail; a shunt regulator configured to regulate the negative output voltage on the negative output rail based on a difference between the negative output voltage and a target negative voltage value, wherein the shunt regulator is powered by the positive output voltage on the positive output rail; a short-circuit transistor having a conduction channel that is connected between the negative output rail and a ground terminal; and a regulation control circuit configured to: provide a short-circuit control signal to a control terminal of the short-circuit transistor in order to short the negative output rail to the ground terminal until the positive output voltage reaches a positive threshold.

A gate driving circuit includes gate driving units. Each of the gate driving units includes a node voltage control module and a pull-down module. The node voltage control module includes a first module and a storage module. The first module outputs a first voltage signal at a first node in response to a pull-down control signal at a first control port. The storage module includes a first port receiving the first voltage signal, and a second terminal electrically connected to the first node. The pull-down module outputs a first working signal for controlling a plurality of sub-pixels to turn off at an output port of the gate driving unit in response to the first voltage signal. The storage module maintains the first voltage signal applied on the first node to maintain the first working signal at the output port of the gate driving unit controlled by the pull-down module.

The invention provides a display device which is characterized in that two cascaded gate drive circuits are spaced by X gate drive circuits, and the phase difference of first clock signals corresponding to the two cascaded gate drive circuits is (X + 1) H, the effective level of a first gate control signal corresponding to the compensation transistor and the effective level of a second gate control signal corresponding to the data transistor are at least partially overlapped; the effective level of a second gate control signal corresponding to the data transistor is located between two first effective levels of a first clock signal applied by a gate drive circuit corresponding to the compensation transistor, and the phase difference between the effective level of the second gate control signal corresponding to the data transistor and one of the two first effective levels is larger than 0 and smaller than (X + 1) H, therefore, in the same sub-pixel, the effective level of the second gate control signal corresponding to the data transistor does not coincide with the moment when the voltage drop of the first gate control signal corresponding to the compensation transistor occurs, and the problem of uneven display is solved.

The invention provides a light-emitting unit driving circuit, a pixel circuit and a display device.The light-emitting unit driving circuit comprises a light-emitting driving unit, a switching circuit, a data switch and an overturning circuit, the light-emitting driving unit comprises a driving tube and a light emitting switch which are connected in series, and the switching circuit comprises a first switch, a second switch, a third switch, a fourth switch and a fourth switch; the first switch, the light-emitting driving unit and the fourth switch form a first output circuit, the second switch, the light-emitting driving unit and the third switch form a second output circuit, and the flip circuit switches the output level polarity after receiving a second scanning signal and a third scanning signal once in each frame. The first output circuit and the second output circuit are controlled to be switched on alternately, so that the voltage direction and the current direction of the driving tube are switched, abnormal accumulation of carriers caused by polarization of the driving tube is avoided, the working performance of the driving tube is improved, and the display effect of the pixel unit and the display device is guaranteed.

Methods, devices, and systems for managing layouts of semiconductor structures in memory devices are provided. In one aspect, a memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first memory block, and the second semiconductor structure includes a driver circuit. The first semiconductor structure and the second semiconductor structure are stacked along a first direction. The driver circuit at least partially overlaps with the first memory block in a plan view perpendicular to the first direction.

A gate driving circuit includes a plurality of stages, wherein each of the plurality of stages includes transistors that control the voltages of control nodes by a carry signal output from a previous stage and a carry signal output from a next stage, and a transistor that reduces leakage current of a first control node.

A power integrated circuit comprising: a heterojunction structure Gallium Nitride, GaN, chip comprising at least one GaN layer and at least one Aluminium Gallium Nitride, AlGaN, layer wherein the GaN chip comprises at least one main power device comprising a source terminal, a drain terminal, a gate terminal and a two-dimensional electron gas, 2DEG, formed at an interface between the AlGaN and GaN layers and between the source and drain terminals, wherein the gate terminal is configured to modulate at least a portion of the 2DEG when a charge is applied to the gate terminal, a driver comprising at least one low-side component and at least one high-side component, wherein the low-side component comprises a terminal connected to a low DC voltage rail and at least one other terminal connected to the gate terminal of the main power device; wherein the high-side component comprises at least one terminal connected to a high DC voltage rail and at least one other terminal connected to the gate of the main power device; wherein the at least one low-side component of the driver is configured to discharge an input capacitance of the main power device during a turn-off of the main power device and is monolithically integrated within the GaN chip; and wherein the at least one high-side component of the driver is configured to charge up the input capacitance of the main power device and is formed in a semiconductor region comprising a material other than GaN.

The present disclosure provides a multi-stage charge pump, a current limiting circuit, a driver circuit, a charge pump, a chip, and an electronic device. A control circuit controls a first charge pump circuit to boost an input voltage of a multi-stage charge pump, and controls, based on a second-phase clock signal, a second charge pump circuit to be charged using an output voltage of the first charge pump circuit, such that the second charge pump circuit boosts an output voltage of the first charge pump circuit, and hence a high-side switch driver circuit satisfies a drive requirement of a high-side switch. This ensures normal operation of the charge pump is ensured while reducing the cost and circuit area. In this way, the reliability and safety of the charge pump are improved.

This disclosure is directed to circuits and techniques for configuring a driver circuit for a power switch when entering a fail-safe state. The driver circuit includes a volatile memory connected to a plurality of independent power supplies, the volatile memory configured to store a fail-safe configuration for the driver circuit. The driver circuit includes driver logic connected to the volatile memory that is configured to determine to enter a fail-safe state and, in response to determining to enter the fail-safe state, configure the driver circuit or a power switch according to the fail-safe configuration stored in the volatile memory.