3287 results about "Driver circuit" patented technology

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A power switching device is disclosed. The power switching device includes a cascode switching circuit comprising a normally-on transistor and a normally-off transistor provided in a cascode topology. The power switching device also includes a gate driver circuit configured to apply a positive bias voltage at a respective gate terminal of the normally-on transistor under a normal operating condition, and to apply a negative bias voltage at the respective gate terminal of the normally-on transistor under a short circuit condition.

The invention belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel, the gate driving circuit comprises N cascaded GOA circuit units, and the nth GOA circuit unit comprises a control voltage maintaining module used for maintaining the control voltage of the n + 1th GOA circuit unit under the action of the pre-charging voltage on the control voltage end of the (n + 1) th GOA circuit unit, maintaining the control voltage end of the nth GOA circuit unit at a first target voltage; the output module is used for outputting a gate driving signal under the action of a first target voltage on a control voltage end and a clock signal output by a clock signal end; the stage transmission module is used for outputting a stage transmission signal for pre-charging the control voltage end of the (n + i) th stage GOA circuit unit under the action of a target voltage on the control voltage end and a clock signal output by the clock signal end; the problem that the potential of the Q point is unstable due to leakage current is solved, the falling edge time of the gate driving signal can be greatly shortened, and the display effect of a picture is improved.

The invention belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel, the gate driving circuit comprises a plurality of clock signal lines and cascaded N driving units, and the nth-level driving unit further comprises a pre-charging module used for pre-charging the nth-level driving unit under the action of a level transmission signal of the (n-i) th-level driving unit, the driving control node is charged through a first driving signal of the (n-i) th-stage driving unit; the output module is used for outputting a first driving signal through the first driving output end and outputting a second driving signal through the second driving output end under the action of the control voltage on the driving control node; according to the gate driving circuit, the number of the driving units can be reduced by half on the premise that the number of the output signals is the same through the mode that the first-stage driving unit outputs the two driving signals, so that the number of transistors in the gate driving circuit is greatly reduced, a narrow-frame product can be achieved, meanwhile, the cost of a panel is reduced, and the stability of the panel is improved.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

The present disclosure provides a gate driving circuit and a display panel. by the control of one of the fourth node, the output end of the second output module, and the first node of the shift register of the next stage, the voltage regulating module may utilize a low voltage signal to stabilize or reduce the gate voltage of the second transistor, so that the second transistor is stable or preferably in the cut-off state to reduce the leakage current. In this way, voltage level of the second gate driving signal can be maintained at a high voltage level or a pulse amplitude.

A driver circuit for controlling a high-power switch. The driver circuit comprises a flyback converter having a positive output rail and a negative output. The driver circuit also comprises: a driving stage that is connected between the positive output rail and the negative output rail; a shunt regulator configured to regulate the negative output voltage on the negative output rail based on a difference between the negative output voltage and a target negative voltage value, wherein the shunt regulator is powered by the positive output voltage on the positive output rail; a short-circuit transistor having a conduction channel that is connected between the negative output rail and a ground terminal; and a regulation control circuit configured to: provide a short-circuit control signal to a control terminal of the short-circuit transistor in order to short the negative output rail to the ground terminal until the positive output voltage reaches a positive threshold.

The invention provides a display device which is characterized in that two cascaded gate drive circuits are spaced by X gate drive circuits, and the phase difference of first clock signals corresponding to the two cascaded gate drive circuits is (X + 1) H, the effective level of a first gate control signal corresponding to the compensation transistor and the effective level of a second gate control signal corresponding to the data transistor are at least partially overlapped; the effective level of a second gate control signal corresponding to the data transistor is located between two first effective levels of a first clock signal applied by a gate drive circuit corresponding to the compensation transistor, and the phase difference between the effective level of the second gate control signal corresponding to the data transistor and one of the two first effective levels is larger than 0 and smaller than (X + 1) H, therefore, in the same sub-pixel, the effective level of the second gate control signal corresponding to the data transistor does not coincide with the moment when the voltage drop of the first gate control signal corresponding to the compensation transistor occurs, and the problem of uneven display is solved.

Methods, devices, and systems for managing layouts of semiconductor structures in memory devices are provided. In one aspect, a memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first memory block, and the second semiconductor structure includes a driver circuit. The first semiconductor structure and the second semiconductor structure are stacked along a first direction. The driver circuit at least partially overlaps with the first memory block in a plan view perpendicular to the first direction.

A gate driving circuit includes a plurality of stages, wherein each of the plurality of stages includes transistors that control the voltages of control nodes by a carry signal output from a previous stage and a carry signal output from a next stage, and a transistor that reduces leakage current of a first control node.

The present disclosure provides a multi-stage charge pump, a current limiting circuit, a driver circuit, a charge pump, a chip, and an electronic device. A control circuit controls a first charge pump circuit to boost an input voltage of a multi-stage charge pump, and controls, based on a second-phase clock signal, a second charge pump circuit to be charged using an output voltage of the first charge pump circuit, such that the second charge pump circuit boosts an output voltage of the first charge pump circuit, and hence a high-side switch driver circuit satisfies a drive requirement of a high-side switch. This ensures normal operation of the charge pump is ensured while reducing the cost and circuit area. In this way, the reliability and safety of the charge pump are improved.

This disclosure is directed to circuits and techniques for configuring a driver circuit for a power switch when entering a fail-safe state. The driver circuit includes a volatile memory connected to a plurality of independent power supplies, the volatile memory configured to store a fail-safe configuration for the driver circuit. The driver circuit includes driver logic connected to the volatile memory that is configured to determine to enter a fail-safe state and, in response to determining to enter the fail-safe state, configure the driver circuit or a power switch according to the fail-safe configuration stored in the volatile memory.

The invention relates to the technical field of power distribution equipment, and discloses a centralized station terminal which comprises a main control module, an FPGA module, a remote control bus driving circuit, a remote signaling bus driving circuit, a plurality of remote control expansion circuits, a plurality of remote signaling expansion circuits and a plurality of telemetering expansion circuits. Wherein the main control module is provided with a PCIe interface, the FPGA module is connected with the main control module through a PCIe bus, and the remote control bus driving circuit and the remote signaling bus driving circuit are both electrically connected with the FPGA module. And the plurality of remote control expansion circuits are electrically connected with the remote control bus driving circuit and are used for outputting remote control signals. And the plurality of remote signaling expansion circuits are electrically connected with the remote signaling bus driving circuit and are used for receiving the remote signaling signals. And the plurality of telemetering expansion circuits are directly and electrically connected with the FPGA module and are used for receiving telemetering signals. According to the centralized station terminal, the FPGA module can process the telemetering signals received by the multiple telemetering expansion circuits in parallel, and transmits the collected data to the main control module through the PCIe bus at a high speed, so that the equipment data collection efficiency is improved.

The embodiment of the invention provides an interlaced PFC circuit and a phase locking method of the interlaced PFC circuit, the interlaced PFC circuit comprises n PFC circuits, n driving circuits and a processor, and the n PFC circuits comprise a main phase PFC circuit and a slave phase PFC circuit. The phase locking method comprises the steps that a processor obtains a master phase driving signal input to a master phase PFC circuit and obtains a slave phase driving signal input to a slave phase PFC circuit; capturing a first rising edge of the slave phase driving signal after the first rising edge of the master phase driving signal occurs to obtain first time; capturing a second rising edge of the master phase driving signal after the first rising edge of the slave phase driving signal occurs to obtain a second time; and controlling the conduction duration of the slave phase driving signal according to the difference value between the first time and the second time. Therefore, quick closed-loop phase locking of the multi-phase interleaving parallel circuit is realized, full-range quick phase locking is realized under the conditions of non-valley bottom opening and valley bottom opening, meanwhile, the circuit design is simplified, and accurate phase locking can be realized without redundant hardware circuits.

A cascoded power switch includes a high-side (HS) switch between an output node and a first voltage supply terminal and a low-side switch. The HS switch includes a first, second, and third transistor in series between the first voltage supply terminal and the output node, and a fourth, fifth, and sixth transistor in series between the first voltage supply terminal and the output node. The first and fourth transistors are in parallel, the second and fifth transistors are in parallel, and the third and sixth transistors are in parallel. A HS driver circuit begins turning on the first transistor in response to assertion of a first control signal and delays turning on the fourth transistor until both the first and second controls signal are asserted. A voltage monitoring circuit includes logic which asserts the second control signal in response to a rise of an output voltage at the output node.

A self-calibrating driver circuit (100, 300, 400, 500, 700) for a laser diode is disclosed. The circuit comprises a configurable current source (105, 305, 405, 505), a current mirror (115, 315, 415) configured to mirror a current from the configurable current source to a first transistor (120, 320, 420, 520, 720) and to a second transistor (125, 325, 425, 725), and a control circuit (140, 340, 440). The control circuit is configured to monitor a current through the first transistor at a first time, and to configure the current source based on the current through the first transistor to provide a desired current to the second transistor for driving the laser diode at a subsequent second time. A radiation-emitting device comprising one or more of the self-calibrating driver circuits and at least one radiation-emitting element is also disclosed.

A hair straightening brush with a thin film transistor-liquid crystal display (TFT-LCD) includes a head part and a handheld part. The head part includes a first housing, metal heat-conducting teeth, and an electric heating component. The handheld part includes a second housing, and a main control unit. The electric heating component is electrically connected to the main control unit. A display module is further disposed in the second housing, is provided with a display (TFT-LCD), and is electrically connected to the display. The display module includes a driver circuit and a signal control module, and is configured to generate timing signals for controlling row and column drivers of the display. The driver circuit is configured to: receive the timing signals for controlling the row and column drivers, convert the timing signals into row and column driver analog voltages, output the analog voltages to the display, and control liquid crystal alignment of the display.

A display device includes a plurality of data lines in a display region, a plurality of display elements in the display region and connected to the plurality of data lines, and a plurality of wirings in the display region and connected to the plurality of data lines, the plurality of wirings configured to transmit data signals from a driver circuit to the plurality of data lines, the driver circuit being outside the display region in a peripheral region, each of the plurality of wirings includes a plurality of branches protruding from a corresponding one of the wirings in a direction perpendicular to an extension direction of the corresponding one of the wirings, and an end portion of each of the plurality of wirings has a tilted shape tilted from the extension direction of the wiring in a plan view.

A gate driving panel circuit and a display device are discussed. The gate driving circuit in an example includes n gate driving panel circuits configured to output two or more gate signals where, n is a natural number equal to or larger than 2, a start dummy gate driving panel circuit configured to generate a first feedback voltage and transfer a start carry signal to a first gate driving panel circuit among the plurality of gate driving panel circuits, and an end dummy gate driving panel circuit configured to generate a second feedback voltage and transferring an end carry signal to an nth gate driving panel circuit.

The invention provides a display panel and a display device, and belongs to the technical field of display driving. The display panel comprises a gate drive unit and a frequency division unit, a display area of the display panel comprises a pixel array composed of a plurality of pixel circuits arranged in an array mode, the gate drive unit comprises a plurality of cascaded gate drive circuits, and each gate drive circuit is connected with one row of pixel circuits. The frequency division unit comprises a plurality of frequency division circuits, and the pixel circuit is used for refreshing and displaying according to a driving signal output by the gate driving circuit. And at least one frequency dividing circuit is arranged between each gate driving circuit and the pixel circuit. The frequency division unit is used for controlling the pixel circuits in partial areas of the display area to input driving signals through the frequency division circuits during the display period of one frame of image, and the pixel circuits in other areas do not input the driving signals, so that the pixel circuits in different areas in the display area carry out display at different refresh rates. Therefore, balance of the refresh rate and the power consumption of the display panel can be realized.

A gate driving circuit, and a display panel and display device including the gate driving circuit are discussed. The display device in an example includes a first switching transistor connected between an output node of a first signal transmitter from which a first gate signal is output and a first gate line, a second switching transistor connected to the output node of the first signal transmitter, a first diode connected between the second switching transistor and the first gate line, a third switching transistor connected between an output node of a second signal transmitter from which a second gate signal is output and a second gate line, a fourth switching transistor connected to the output node of the second signal transmitter, and a second diode connected between the fourth switching transistor and the second gate line.

The invention provides a display device, a gate drive circuit of the display device comprises N levels of cascaded gate drive units, the ith level of gate drive unit comprises a first transistor, a first frequency division signal line, a second frequency division signal line and a frequency division control module, a gate of the first transistor is electrically connected to a second node, and a gate of the second transistor is electrically connected to a third node. The source electrode and the drain electrode are electrically connected to the first clock signal line and the gate driving signal output end respectively, and the frequency division control module is electrically connected with the first node, the second node, the first frequency division signal line and the second frequency division signal line. The first frequency division signal line and the second frequency division signal line are located between the first transistor and the frequency division control module. Through the layout mode, the metal overline distance is reduced, the layout space of the gate driving unit is saved, meanwhile, different areas of the display panel are refreshed by adopting different refresh frequencies, and the power consumption of the display device is reduced.

An object is to provide a technique that eliminates the need for an external circuit for enhancing the breakdown voltage. A switching element drive circuit includes a primary circuit and a secondary circuit, and an insulating element isolating the primary circuit and the secondary circuit from each other in terms of a direct current. The secondary circuit includes a semiconductor substrate, a detector provided on a portion of the semiconductor substrate, including a pn junction isolation portion, and configured to detect a voltage of a high voltage terminal, and a controller provided on a remaining portion of the semiconductor substrate and configured to control a control voltage of a semiconductor switching element based on a second signal and a detection result of the detector.

A semiconductor device is provided. The semiconductor device includes: an equalizer circuit configured to output a first control signal corresponding to a first bit of original two-bit data and a second control signal corresponding to a second bit of the original two-bit data; and a driver circuit including a plurality of pull-up transistors connected between an output node and a first power node configured to provide a first power supply voltage, and a plurality of pull-down transistors connected between the output node and a second power node configured to provide a second power supply voltage, wherein the second power supply voltage is lower than the first power supply voltage, and the driver circuit is connected to the equalizer circuit in series. The plurality of pull-up transistors includes a first pull-up transistor and a second pull-up transistor connected to each other in parallel, between the first power node and the output node, and a third pull-up transistor and a fourth pull-up transistor connected to each other in series, between the first power node and the output node.

The invention belongs to the technical field of pulse power, and relates to a solid-state repetition-frequency pulse generator driven by multiple paths of synchronous optical fibers and a control method, the solid-state repetition-frequency pulse generator comprises a drive control circuit, the drive control circuit is connected with a Marx generator, and an AC-DC converter and a plurality of groups of IGBT switching circuits connected in series are arranged in the Marx generator; and the AC-DC converter is electrically connected with the group of IGBT switching circuits. In the topological structure, a plurality of IGBTs connected in series only need a gate driving voltage signal to drive the lowermost IGBT switching circuit, and other IGBT switching circuits are connected in series with one another, so that the IGBT switching circuits are sequentially conducted in an extremely short time, and synchronous driving is realized. Based on the circuit structure, a plurality of IGBT devices are modularly designed, and each module only needs one driving signal, so that the number of driving circuits is reduced, and the circuit structure is more compact.

Circuits for reflection cancellation in single-ended signaling are disclosed. A transmission circuit includes a control circuit configured to receive a plurality of input signals that include a plurality of symbols having at least one bit and a data driver circuit configured to generate a particular signal on a transmission medium using a particular symbol of the plurality of symbols. The transmission circuit further includes a reflection cancellation circuit configured to, after a generation of the particular signal, generate a reflection cancellation signal on the transmission medium using an inverted value of a different symbol of the plurality of symbols received prior to the particular symbol. A first composite of the particular signal and the cancellation signal is readable at a load as a value of the particular symbol, wherein the load is configured to receive a transmitted signal via the transmission medium.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.