432 results about "Driver circuit" patented technology

A display panel includes pixels and a driver circuit. The driver circuit includes shift register units and switch modules. Each switch module includes N switch units turned on in a time-sharing manner. A signal input terminal of an M-th-stage shift register unit is electrically connected to a start control signal terminal through any one of an M-th switch unit to an N-th switch unit; and the signal input terminal of the M-th-stage shift register unit is electrically connected to a signal output terminal of at least one of a first-stage to an (M−1)-th-stage shift register unit through a first to an (M−1)-th switch unit. A signal input terminal of an (I+N)-th-stage shift register unit is electrically connected to a signal output terminal of at least one of an I-th-stage to an (I+N−1)-th-stage shift register unit through the N switch units.

Embodiments of the present application provide a display panel and a display device. The display panel comprises a gate drive circuit. A pull-down capacitor is arranged in the gate drive circuit. At least one of a first node and a second node is electrically connected to a first plate of the pull-down capacitor. A second plate of the pull-down capacitor is electrically connected to a low potential power supply end. The pull-down capacitor is arranged between the at least one of the first node and the second node and the low potential power supply end. The pull-down capacitor can improve the ability to maintain the first node and / or the second node at a low potential. The ability to maintain other nodes and a signal output end at a low potential is improved. The pull-down speed is improved. The ability to maintain a low potential is improved. The channel width of a transistor in a pull-down maintenance module and an inverting module can be appropriately reduced due to the increased pull-down maintenance ability of the pull-down capacitor. As a result, the leakage current is reduced. The low leakage and the low potential maintenance ability of the gate drive circuit are balanced.

This disclosure provides a DC-DC converter and chip, wherein the DC-DC converter includes a bootstrap boost circuit, a charge pump boost circuit, a high-side drive circuit, a low-side drive circuit, a high-side power transistor, and a low-side power transistor. The bootstrap boost circuit provides a first boost voltage to the high-side drive circuit. The high-side drive circuit outputs a first high-side drive voltage to the control electrode of the high-side power transistor based on the first boost voltage. The charge pump boost circuit generates a second boost voltage through a charge pump and outputs a second high-side drive voltage to the control electrode of the high-side power transistor based on the second boost voltage. The second boost voltage is greater than the first boost voltage. The first electrode of the high-side power transistor is coupled to the input voltage terminal, and the second electrode is coupled to the first electrode of the low-side power transistor via a switching node. The high-side power transistor is turned on or off according to the first and second high-side drive voltages. One end of the bootstrap boost circuit and one end of the charge pump boost circuit are respectively coupled to the switching node.

The invention relates to an electronics unit (10) for controlling a load current (I) of an electric load (12), in particular of an electric motor (14), of an electric device by means of at least one power transistor (18) which has at least one control electrode (34) and two power electrodes (36, 38), wherein a control circuit (48) of the power transistor (18) comprises a driver circuit (26) controlling the control electrode (34) and a power circuit (52) of the power transistor (18) comprises the two power electrodes (36, 38) and the electric load (12), and wherein a parasitic inductance of the control circuit (48) and at least one parasitic inductance of the power circuit (52) form a common source inductance (LCSH, LCSH1, LCSH2). According to the invention, the switching behaviour of the at least one power transistor (18) can be influenced during a switching phase (T2, T7), in particular a switch-off phase T7), in which the load current (I) changes over time, by means of at least one controlled current source (54) which is connected to one of the power electrodes (38), in such a way that a negative voltage feedback to the control electrode (34) takes place as a result of the change over time of the load current (dI / dt) via the common source inductance (LCSH, LCSH1, LCSH2). In addition, the invention relates to an electric device, in particular a motor-operated electric device, comprising an electronics unit (10) according to the invention for controlling an electric load (12), in particular a one-phase or multiphase electric motor (14).

Provided are an array substrate, a display panel, and a display device. The array substrate includes a substrate, multiple pixel driving circuits, and multiple signal lines; a pixel driving circuit of the multiple pixel driving circuits includes a drive transistor and a regulating transistor, the multiple signal lines include a scan signal line, a regulating signal line, and a power signal line, and the scan signal line includes a regulating control signal line; a first electrode of the drive transistor is electrically connected to a power signal line; a first electrode of the regulating transistor is electrically connected to the regulating signal line, a second electrode of the regulating transistor is electrically connected to the first electrode of the drive transistor or a second electrode of the drive transistor, and the gate of the regulating transistor is electrically connected to the regulating control signal line.

A light-emitting control circuit includes a first detection control unit electrically connected to a detection control terminal, a first clock signal terminal, a first voltage signal terminal, and a first node, configured to transmit a first voltage signal to the first node under the control of a detection control signal and a first clock signal. A first light-emitting output unit electrically connected to the first node, the first voltage signal terminal, and a first output signal terminal, configured to transmit the first voltage signal to the first output signal terminal under the control of the voltage at the first node. A second detection control unit electrically connected to a detection control terminal, a second clock signal terminal, the first voltage signal terminal, and a second node, configured to transmit the first voltage signal to the second node under the control of a detection control signal and a second clock signal. A second light-emitting output unit electrically connected to the second node, the first voltage signal terminal, and a second output signal terminal, configured to transmit the first voltage signal to the second output signal terminal under the control of the voltage at the second node.

An electronic device may include display and touch sensor circuitry. The display circuitry may include gate driver circuitry that provides anode reset control signals to display pixels. If desired, the gate driver circuitry may include per-row gate drivers and per-row pull-down circuits in an interlaced configuration on opposing sides of the display pixel array. If desired, the gate driver circuitry may include gate drivers configured with dynamic knee voltage control on their driver outputs.

This application discloses a differential transmitter circuit, chip, and electronic device. The differential transmitter circuit includes: a single-slip differential drive enhancement circuit, including a single-ended digital input terminal (IN) and a first differential output terminal (IN_P, IN_N), used to convert the input single-ended digital signal into a pair of differential signals; a differential drive circuit, connected to the first differential output terminal (IN_P, IN_N), including a second differential output terminal (OUT_P, OUT_N), used to convert the differential signals into differential output voltages; wherein, the single-slip differential drive enhancement circuit includes a transmission gate (Tran) and an inverter, used to generate the differential signals with a phase difference of 180° and timing matching. The embodiments of this application aim to solve the technical problems of slow response speed, poor common-mode stability, high power consumption, and insufficient noise suppression capability in the prior art when transmitter circuits are used in LVDS interface applications.

The application discloses a crosstalk suppression module and a control method thereof, a display panel and a display device, and relates to the technical field of display. The crosstalk suppression module is provided with a gate drive circuit integrating gate scanning units at all levels, and a replacement circuit connected between a direct-current high-voltage signal line and a first passage end of a pre-charging transistor in the gate scanning unit. When the direct-current high-voltage signal line is normal, the pre-charging transistor is enabled to be connected to a pre-charging voltage provided by the direct-current high-voltage signal line under the drive of a front-stage scanning signal to pre-charge the first node, so that an output transistor is turned on and a current-stage scanning signal is output. When the direct-current high-voltage signal line is invalid, the pre-charging transistor is enabled to provide a pre-charging replacement voltage of the replacement circuit to the first node under the drive of the front-stage scanning signal, so that the output transistor is normally turned on. The application aims to improve the fault tolerance of the gate drive circuit to the invalid direct-current high-voltage signal line to improve the uniformity of picture display.

The present disclosure provides an array substrate and a display device. The array substrate includes a substrate layer and a gate drive circuit disposed at a peripheral region of the substrate layer. The gate drive circuit includes a plurality of cascaded shift registers. The shift register includes an input circuit, an output circuit, a pull-down node control circuit, and a noise reduction circuit. At least one transistor included in the input circuit, the output circuit, and the noise reduction circuit is a first type of transistor. The pull-down node control circuit includes a plurality of transistors connected between a first voltage terminal and a first reset voltage terminal, and at least one transistor of the plurality of transistors is a second type of transistor. The first type of transistor includes a first active layer, and the second type of transistor includes a second active layer. An electron mobility of the second active layer is less than an electron mobility of the first active layer.

The utility model discloses a kind of synchronous rectification circuit and switching power supply, synchronous rectification circuit includes the isolation transmission circuit, inverting driver circuit and freewheeling tube driving circuit connected in turn;The isolation transmission circuit is for processing and transmission with driving signal;The inverting driver circuit is for the driving signal to be inverted, and control the freewheeling tube driving circuit;The freewheeling tube driving circuit is for according to the stress signal of freewheeling tube, output is used for controlling the freewheeling tube driving signal that freewheeling tube opens or shuts off.The utility model transmits primary side timing to the control freewheeling tube driving logic of secondary side, realize that negative pressure detection chip can use in depth CCM mode, greatly widen the application of negative pressure detection chip in high-power product.

The application discloses a shift register unit, a driving method thereof, a display driving circuit and a display device, and belongs to the technical field of display. In the shift register unit, an input circuit (01) can transmit power signals with different potentials to a control node (PD) in different time periods in response to an input signal (In / ESTV) and a clock signal (CKN, CK), and two output circuits (02, 03) can transmit power signals with different potentials to connected output ends (Nout, Next) in different time periods in response to the potential of the control node (PD). Therefore, it can be determined that the shift register unit comprises P-type transistors and N-type transistors. Furthermore, the two output circuits (02, 03) can independently output signals to the connected output end (Nout). On this basis, the potential of the power signal can be flexibly adjusted, so that the driving output end (Nout, Next) of the connected pixel can reliably transmit the required driving signal with the potential to the pixel in different refresh frequency regions, to support the local refresh function. The shift register unit has simple structure and rich functions.

A gate drive circuit and a display panel. The gate drive circuit includes one or more shift register groups. Each of the shift register groups includes N shift adjacent registers that output in sequence, with N being an integer greater than or equal to 3. Each of the shift registers includes a first output stage and a frequency division control module. The first output stage is configured to output a gate drive signal. The frequency division control module is configured to control outputting of the gate drive signal based on a refresh frequency. A control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies.

A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.

The application provides a gate driving circuit, and belongs to the technical field of display. An alternating switching module outputs a first n-th stage switching signal according to an n-th stage reverse signal and a first local clock signal. The alternating switching module outputs a second n-th stage switching signal according to the n-th stage reverse signal and a second local clock signal. The first local clock signal is opposite to the second local clock signal. A pull-down maintaining module pulls down and maintains the potential of an n-th stage control signal and the potential of an n-th stage gate driving signal to a reference low potential according to the first n-th stage switching signal or the second n-th stage switching signal. Under the control of the first n-th stage switching signal or the second n-th stage switching signal alternately output by the alternating switching module, each transistor in the pull-down maintaining module can be alternately turned on and operated, so that the problem of forward drift of threshold voltage caused by the long-time opening of the transistor in the pull-down maintaining module is solved.

Disclosed is a display substrate including: a base substrate, and a drive circuit layer disposed on the base substrate layer, which includes at least multiple circuit units, wherein at least one of the multiple circuit units includes a pixel circuit which includes at least a first capacitor a second capacitor, a data writing transistor, a drive transistor, and a first light emitting control transistor. A first end of the first capacitor is electrically connected with a gate electrode of the drive transistor, a second end of the first capacitor is electrically connected with a second end of the second capacitor, and a first end of the second capacitor is electrically connected with a first signal line. A first electrode of the first light emitting control transistor is electrically connected with a first power supply line and a second electrode is electrically connected with a first electrode of the drive transistor.

A display substrate, a control method and a manufacturing method therefor and a display device are disclosed.The display substrate comprises a plurality of circuit units, wherein the circuit units comprise at least one pixel driver circuit, the pixel driver circuit comprises at least one data write transistor (T4), and the data write transistor (T4) is connected to a data signal line (62); the plurality of circuit units comprises at least one first circuit unit (Q1) and a second circuit unit (Q2), the first circuit unit (Q1) comprises a first pixel driver circuit, the second circuit unit (Q2) comprises a second pixel driver circuit, the first pixel driver circuit and the second pixel driver circuit share the same data write transistor (T4) and are connected to the same data signal line (62), and the data signal line (62) sequentially supplies a first data signal to the first pixel driver circuit and a second data signal to the second pixel driver circuit through the data write transistor (T4).

Disclosed are a display substrate, a manufacturing method therefor, and a display apparatus. The display substrate includes a plurality of circuit units, at least one circuit unit includes a pixel drive circuit, the pixel drive circuit includes, at least, a first storage capacitor and a second storage capacitor, the first storage capacitor includes at least two first capacitor plates, orthographic projections of the two first capacitor plates on a substrate are overlapped, at least partially, with each other, the second storage capacitor includes at least two second capacitor plates, orthographic projections of the two second capacitor plates on the substrate are overlapped, at least partially, with each other.

A display driving circuit and a display driving method are provided. The display driving circuit includes a controller, a common voltage supply circuit, and a border voltage supply circuit. The controller generates a plurality of border voltage control signals and a plurality of common voltage control signals. The common voltage supply circuit outputs a common voltage to the display panel according to the plurality of common voltage control signals. The border voltage supply circuit outputs a border voltage to the display panel according to the plurality of border voltage control signals. When a voltage polarity of the common voltage is reversed, the common voltage supply circuit performs charge sharing by a common ground voltage.

The application belongs to the technical field of display, and discloses a substrate structure, a forming method, a display panel and a substrate splicing layout structure. The substrate structure comprises at least one substrate unit, the substrate unit has a first side edge and two second side edges adjacent to and opposite to the first side edge, the first side edge is used to correspond to the direction of a chip on film circuit, and the second side edge is used to correspond to the direction of a gate driver on array circuit; the at least one substrate unit comprises a first substrate unit, the first substrate unit is provided with an alignment area and a wiring area, the alignment area is used to align an inner alignment part arranged on a mask plate, the wiring area is used to supply a common electrode line, the alignment area is arranged adjacent to one of the second side edges, and the wiring path of the wiring area is arranged to avoid the alignment area. In the application, the first substrate unit can be positioned in the GDL direction when splicing, so that the splicing is not limited by the direction, the wiring area is avoided in the first substrate unit, and it is ensured that the pixels can be normally displayed.

Pixel driver circuit applied to a display field, wherein the display field comprises multiple pixel elements, and wherein the pixel driver circuit comprises the following: a driver module (11) comprising a driver transistor (Tm) whose input terminal (111) is coupled to a driver voltage terminal (VDD) and whose output terminal (112) is coupled to a subpixel element (M); a data write module (12) whose output terminal is coupled between the input terminal (111) of the driver transistor (Tm) and the driver voltage terminal (VDD) and which serves to write a data voltage to the driver transistor (Tm) during a compensation write phase; and a voltage stabilization module (13) coupled to a first control terminal (113) of the driver transistor (Tm) and serves to maintain a stable voltage of the first control terminal (113) of the driver transistor (Tm) during a reset phase; characterized in that the driver transistor (Tm) further comprises a second control terminal (114), wherein the first control terminal (113) in conjunction with an active layer of the driver transistor (Tm) forms a first parasitic capacitance (Cgd), while the second control terminal (114) is coupled to a DC signal terminal, such that the second control terminal (114) and the active layer (4) form a second parasitic capacitance (Cgd2).

A display panel and display device are disclosed. The display panel includes sub-pixel units arranged in an array along a first direction (X) and a second direction (Y), the first direction (X) and the second direction (Y) intersecting. Each sub-pixel unit includes a pixel driving circuit and a light-emitting unit (OLED). The pixel driving circuit is connected to a first electrode of the light-emitting unit (OLED). The pixel driving circuit includes a driving transistor (T3) and a capacitor (C). The first electrode of the capacitor (C) is connected to a first power line (VSS), and the second electrode of the capacitor (C) is connected to the gate of the driving transistor (T3). The display panel further includes a substrate (81), a second conductive layer, a fourth conductive layer, and a common electrode layer (6). The second conductive layer is located on one side of the substrate (81) and includes a plurality of first conductive portions (21). The first conductive part (21) and the pixel driving circuit are correspondingly disposed. The first conductive part (21) is used to form the first electrode of the capacitor (C) in the corresponding pixel driving circuit. The fourth conductive layer is located on the side of the second conductive layer away from the substrate (81). The fourth conductive layer includes multiple first power lines (VSS). The orthographic projection of the first power lines (VSS) on the substrate (81) is distributed at intervals along the first direction (X) and extends along the second direction (Y). The first conductive part (21) is connected to the first power lines (VSS) through vias. The common electrode layer (6) is located on the side of the fourth conductive layer away from the substrate (81). The common electrode layer (6) is used to form the second electrode of the light-emitting unit (OLED). The first power lines (VSS) are connected to the common electrode layer (6) through vias. This display panel can reduce the voltage drop caused by the resistance of the common electrode layer (6) itself.

The present disclosure relates to the technical field of display, and proposes a gate driving circuit, a driving method of a display panel, and a display device. The gate driving circuit comprises: a plurality of output terminals, the output terminals are arranged in correspondence with pixel driving circuit rows, and the output terminals are configured to provide a pulse width modulation signal to a control terminal of a first switch unit in a pixel driving circuit row corresponding to the output terminal; the gate driving circuit is configured to provide the pulse width modulation signal to a pixel driving circuit subgroup in a same pixel driving circuit group in a same frame, a pixel driving circuit row comprises a plurality of pixel driving circuits distributed along a first direction, and a part of the pixel driving circuit rows in the pixel driving circuit group form a pixel driving circuit subgroup; and the gate driving circuit is configured to provide the pulse width modulation signal to different pixel driving circuit subgroups in the same pixel driving circuit group in at least partially different frames. The display panel can improve the threshold shift problem of the first switch unit.

Provided are a shift register unit and a driving method therefor, a gate driving circuit, and a display apparatus, which belong to the technical field of display. In the shift register unit, a register circuit can transmit signals of different potentials to a control node in different time periods under the control of signals such as an input signal and a clock signal, such that a transmission circuit and an output circuit can both output signals of different potentials by means of a connected output end in different time periods under the control of the potential of the control node. Therefore, it can be seen that the shift register unit can be a hybrid circuit of a P-type transistor and an N-type transistor, thereby achieving the overall simple circuit structure and a relatively good output reliability.

A display substrate and a display device. The display substrate comprises a substrate, a pixel circuit layer and an anode layer; the pixel circuit layer is located on the substrate and comprises a plurality of pixel driving circuits; the anode layer is located on a side of the pixel circuit layer away from the substrate and comprises a plurality of anodes. The plurality of pixel driving circuits are arranged one-to-one corresponding to the plurality of anodes, each pixel driving circuit comprises a functional thin film transistor; the plurality of pixel driving circuits comprise first pixel driving circuits and second pixel driving circuits arranged adjacently, and the channel region of the functional thin film transistor in the first pixel driving circuit and the channel region of the functional thin film transistor in the second pixel driving circuit are both overlapped with the normal projection of the anode corresponding to the first pixel driving circuit on the substrate. Thus, the display substrate can improve the stability and the life of the functional thin film transistor, thereby improving the long-term light-emitting stability and the life of the display substrate.

An array substrate is provided. The array substrate includes K number of reset signal lines respectively configured to provide reset signals to reset transistors in K columns pixel driving circuits of the array substrate. The K number of reset signal lines includes a plurality of third reset signal lines in (2k−1)-th columns of K columns, K and k being positive integers, 1≤k≤(K / 2); and a plurality of fourth reset signal lines in (2k)-th columns of the K columns.

A display substrate includes multiple circuit units, a first power supply connection line, a second power supply connection line, a first power supply line, and a second power supply line, a circuit unit includes a pixel drive circuit, the first power supply line is connected to the pixel drive circuit, and is connected to the first power supply connection line, and the second power supply line is connected to the second power supply connection line; the pixel drive circuit includes a first shielding electrode and at least one transistor with a double-gate structure, an orthographic projection of the first shielding electrode on the base substrate is at least partially overlapped with that of a node between two gate electrodes of a transistor with the double-gate structure on the base substrate; the first shielding electrode is connected to a first power supply connection line or a second power supply connection line.

This invention discloses a BUCK circuit with precisely adjustable current and its adjustment method. The circuit includes a time loop control circuit and a BUCK constant current circuit. The input terminal of the time loop control circuit is connected to the output terminal of the BUCK constant current circuit to obtain the output current Iout of the BUCK constant current circuit. The output terminal of the time loop control circuit is connected to the input terminal of the BUCK constant current circuit to adjust the output current Iout of the BUCK constant current circuit. The time loop control circuit includes a sampling circuit I0, a comparator I1, a control calculation module I2, and an AND gate I3. The BUCK constant current circuit includes a driver circuit I4, an NMOS transistor Q0, a freewheeling diode D0, an energy storage inductor L0, a current sensing resistor R0, a filter capacitor C0, a light-emitting diode D1, and a power supply. The adjustment method includes: obtaining the sampling voltage Vsns and calculating the output current Iout; if the output current Iout is adjusted to a high current adjustment, it enters the analog adjustment mode; otherwise, it enters the mixed analog-digital adjustment mode. The output current of the BUCK circuit can be precisely adjusted.

This invention provides a control circuit and power supply method for controlling a power switching transistor in a switching power supply. The control circuit includes a logic control circuit, a high-voltage power supply circuit, and a power supply control circuit. The high-voltage power supply circuit draws power from the line voltage terminal and stores energy in an energy storage circuit under the control of the power supply control circuit. The control circuit further includes a drive circuit and a current source for powering it. The drive circuit drives the power switching transistor to switch on and off states to adjust the output signal of the switching power supply. The current source draws power from the line voltage terminal and is further coupled to the drive circuit to supply power to the control terminal of the power switching transistor. The control circuit and power supply method provided by this invention reduce fluctuations in the power supply signal of the logic control circuit, improve anti-interference capability, provide controllable turn-on speed of the power switching transistor's control terminal, suppress noise, and have a small energy storage capacity that is easy to integrate.

This invention discloses a T-type three-level hybrid rectification system and control method for charging piles. Addressing the issues of high switching losses in existing all-IGBT solutions and high costs in all-SiC solutions, this invention introduces a heterogeneous hybrid switching unit composed of parallel Si IGBTs and SiC MOSFETs in the vertical bridge arm of the T-type midpoint clamping topology. Through an RC hardware delay drive circuit, the SiC MOSFET is precisely controlled to turn on and off before switching transients, creating a zero-voltage turn-on and zero-current turn-off environment for the Si IGBT, completely eliminating the tail current loss of the IGBT. In the steady-state conduction, the Si IGBT bears the main load current. This invention has been verified by thermal loss modeling on the PLECS power electronics simulation platform, significantly reducing device costs while lowering switching losses by more than 80%, effectively improving the conversion efficiency and power density of the charging pile's rectifier stage.