82 results about "Line driver" patented technology

A memory device may be provided herein. The memory device may comprise a memory block configured to include a first select line, word lines, a second select line, a channel layer, first select transistors, second select transistors, and memory cells; a voltage generator configured to produce a turn-on voltage and a turn-off voltage applied to the first and second select lines, and to produce a programming voltage and a pass voltage applied to the word lines; a source line driver configured to produce a pre-charge voltage applied to the source line; and a side buffer group configured to apply a programming enable voltage and a programming lock voltage to bit lines.and a control circuit designed to determine a reference position and to control the voltage generator, source line driver, and side buffer group to adjust the time required to preload the channel layer.

The application discloses a flat valve repairing device, which comprises a fixing device, a valve cover disassembling device, a valve seat disassembling device, a turnover device, a valve cover fastening device, a packing sealing device and an ultrasonic cleaning device. The fixing device is used for fixing the flat valve; the valve cover disassembling device is used for disassembling the valve cover of the flat valve; the valve seat disassembling device is used for disassembling the valve seat; the turnover device is used for rotating the flat valve; the valve cover fastening device is used for clamping the valve cover; the packing sealing device is used for sealing the packing into the valve cover of the flat valve; and the ultrasonic cleaning device is used for cleaning the disassembled parts. The application further discloses an automatic control system of the flat valve repairing device, which realizes the automatic disassembling, assembling and packing sealing of the flat valve through an industrial control touch screen, a PLC controller, an A / D converter, a signal conditioner, a circuit driver and a power component driver. The application realizes the automatic operation of the disassembling and packing sealing of the flat valve, has high working efficiency and low labor intensity, and is suitable for all scenes in which the flat valve needs to be disassembled.

A tunable termination resistor circuit associated with a line driver in a line on-chip is provided. The circuit includes a first current source and a first resistor coupled to the first current source and the line. The circuit also includes a first diode comprising a first terminal and a second terminal, the first terminal being coupled to the first resistor and the second terminal being coupled to a gate of a transistor, the gate being coupled to a gate voltage. The circuit also includes a capacitor coupled to the gate and the source of the transistor. The circuit also includes a third resistor coupled in series to a fourth resistor in the line each of the third resistor and the fourth resistor comprising a resistance changed by the gate voltage. There are other embodiments as well.

A microelectronic device includes a memory array structure and a control circuitry structure overlying and bonded to the memory array structure. The memory array structure includes memory cells, digit lines, and word lines. The control circuitry structure includes a control circuitry region, digit line contact sections, and word line contact sections. The control circuitry region includes sense amplifier sections including sense amplifiers, and sub-word line driver sections including sub-word line drivers. The digit line contact sections are horizontally adjacent to the sense amplifier sections in a first direction and include contact structures coupled to the sense amplifiers and the digit lines. The word line contact sections are horizontally adjacent to the sub-word line driver sections in a second direction orthogonal to the first direction and include additional contact structures coupled to the sub-word line drivers and the word lines. Additional microelectronic devices, memory devices, and electronic systems are also described.

A memory device with high storage capacity and low power consumption is provided. The memory device includes a first layer and a second layer including the first layer. The first layer includes a circuit, and the second layer includes a first memory cell. The circuit includes a bit line driver circuit and / or a word line driver circuit which transmits(s) a signal to the first memory cell. The first memory cell includes a first transistor, a second transistor, a conductor, and an MTJ element. The MTJ element includes a free layer. The free layer is electrically connected to the conductor. The first terminal of the first transistor is electrically connected to a first terminal of the second transistor through the conductor. The free layer is positioned above the conductor. The circuit includes a transistor containing silicon in a channel formation region, and each of the first transistor and the second transistor contains a metal oxide in a channel formation region.

This invention provides an optimized system for improving the slew rate of a Line Driver, comprising a differential input module, a bias current module, an amplification module, an active load module, and a mirror load module. The differential input module receives the input signal and converts the voltage signal into a current signal. The bias current module provides a stable bias current to the circuit. The amplification module receives the current signal from the differential input module and achieves voltage gain. The amplification module is electrically connected to the active load module. The active load module can improve the amplification gain of the amplification module, replicate the current, and stabilize the output node. The mirror load module can replicate the signal amplification path of the amplification module to achieve symmetrical output, thereby improving the signal amplification effect and anti-interference reliability of the circuit and solving the problem of limited slew rate in traditional optimized systems for Line Drivers.

A semiconductor memory device is provided. The apparatus includes: a first word line in N layers, the first word line extending from a first stack region toward a first step region; a second word line in the N layers, the second word line extending from the second stack region toward the second step region; a first memory cell provided in the first stack region; a second memory cell provided in the second stack region; n first word line contacts connected to the first word line in the first step region; and N second word line contacts connected to the second word line in the second step region. A first word line in a Kth layer (K is an integer from 1 to N) among the first word lines and a second word line in an (N-K + 1) th layer among the second word lines are commonly connected to one sub-word line driver.

A microelectronic device includes a memory array structure and a control circuitry structure vertically overlying and bonded to the memory array structure. The memory array structure includes array regions respectively including memory cells, digit lines, and word lines within horizontal areas thereof. The control circuitry structure includes control circuitry regions, sense amplifier (SA) sections including SA circuitry, and sub-word line driver (SWD) sections including SWD circuitry. The control circuitry regions horizontally overlap the array regions of the memory array structure. The SA sections respectively horizontally overlap each of two of the control circuitry regions horizontally neighboring one another in a first direction. The SWD sections are respectively interposed between two other of the control circuitry regions horizontally neighboring one another in a second direction orthogonal to the first direction. Additional microelectronic devices, memory devices, and electronic systems are also described.

An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bias voltage for word line driver and a configuration of the current mirroring circuit to inhibit drop of a voltage on the bit line below a bit flip voltage during execution of the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.

This application discloses a wired transmitter with overvoltage protection, comprising a digital-to-analog converter (DAC) and a line driver. The DAC generates a plurality of first output signals based on a digital code, wherein a first circuit in the DAC operates in a first voltage domain, a second circuit in the DAC operates in a second voltage domain, and the upper limit of the first voltage domain is lower than the upper limit of the second voltage domain. The line driver operates in the second voltage domain and generates a plurality of second output signals based on the first output signals, wherein each of the DAC and the line driver is implemented via a plurality of transistors corresponding to the first voltage domain.

An example memory device includes a first wafer that includes a first sub-memory block connected to first to n-th word lines, a first bit line, a first string selection line, and a first ground selection line, and a second wafer that is stacked on the first wafer in a vertical direction and includes a second sub-memory block connected to (n+1)-th to 2n-th word lines, a second bit line, a second string selection line, and a second ground selection line. The first to n-th word lines are respectively connected to the (n+1)-th to 2n-th word lines and share first to n-th word line drivers with the (n+1)-th to 2n-th word lines. The first bit line is connected to the second bit line and shares a first page buffer with the second bit line.

A semiconductor memory device is provided. The device includes: first word lines in N layers, the first word lines extending from a first stack region toward first stair regions; second word lines in the N layers, the second word lines extending from a second stack region toward second stair regions; first memory cells provided in the first stack region; second memory cells provided in the second stack region; N first word line contacts connected to the first word lines in the first stair regions; and N second word line contacts connected to the second word lines in the second stair regions. A first word line in a Kth layer (K being an integer from 1 to N) among the first word lines and a second word line in an (N−K+1)th layer among the second word lines are commonly connected to one sub-word line driver.

Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

An oxide semiconductor 2 T0C DRAM non-volatile power-off testing circuit and verification method, relating to the technical field of information materials and devices. The testing circuit comprises an oxide semiconductor 2 T0C DRAM cell, transmission gates, an input data buffer, a current mode sense amplifier, and a bootstrap write word line driver. After a write operation of the oxide semiconductor 2 T0C DRAM cell, high-impedance nodes are introduced in the form of the transmission gates, so that the oxide semiconductor 2 T0C DRAM cell is completely powered off and isolated from an external circuit. In the present invention, non-volatility test and verification can be well performed on an oxide semiconductor 2 T0C DRAM cell, thereby broadening the application range of non-volatility of an oxide semiconductor 2 T0C DRAM, which is of great significance for the development of the oxide semiconductor 2 T0C DRAM in the post-Moore era.

Disclosed are a word line (WL) driver and a memory structure including a WL driver system with multiple WL drivers. The WL driver includes a write WL voltage (VWL) control node, a read VWL control node, and an output node. First and second transistors are connected in series between the write VWL control node and the output node. Third and fourth transistors are connected in parallel between the read VWL control node and the output node. The first, second, and third transistors are P-type field effect transistors (PFETs) and the fourth transistor is an N-type field effect transistor (NFET). Additional NFETs are connected between the output node and ground and, optionally, between the gate and source of the second transistor. All transistors are the same gate dielectric type.

The utility model relates to the technical field of drivers, and provides a long-line driver cable folding device which comprises a box body, a winding bin and a cleaning bin are arranged on the upper side and the lower side in the box body respectively, sliding grooves are formed in the two sides of the box body, sliding mechanisms are arranged in the sliding grooves and on one side of the sliding grooves, a winding roller is arranged between the sliding mechanisms on the two sides, and the winding roller is connected with the cleaning bin. First pneumatic telescopic rods are fixedly connected to the two sides of the interior of the cleaning bin correspondingly, telescopic frames are fixedly connected to the extending ends of the first pneumatic telescopic rods, telescopic supporting rods are connected to the interiors of the telescopic frames in an inserted mode, and the telescopic frames can extend through the arranged first pneumatic telescopic rods; the extension mechanism in the telescopic frame is started to drive the telescopic supporting rod to extend so as to adapt to the anti-skid extrusion blocks on the two sides to clamp the driver, the telescopic frame is pulled back after clamping, the driver can be attached to one side of the box body, and therefore the interior of the box body can be in a relatively closed state.

A touch sensor controller including a line driver and a method of calibrating a line driver for a touch panel are described. The line driver is configured to be coupled to a row or column of a touch panel, the method includes providing a line drive current and providing a sense current related to the drive current. The sense current values are digitized and an overload status determined dependent on the digitized sense current values. The line driver is controlled to increase or decrease the line drive current dependent on the overload status.

Dual-rail storage device capable of operating at a first voltage (VDDM) and a second voltage (VDD), wherein the dual-rail storage device comprises the following: a memory array (150) that operates at the first voltage (VDDM); a word line driver circuit (140) configured to drive a word line of the memory array (150) to the first voltage (VDDM); a data path (110) configured to carry an input data signal or an output data signal; and a control circuit (120) configured to generate control signals for the memory array (150), the word line driver circuit (140) and the data path (110), wherein the data path (110) and the control circuit (120) are configured to operate at both the first voltage (VDDM) and the second voltage (VDD), wherein part of the data path (110) and part of the control circuit (120) are configured to operate at the first voltage (VDDM), and the remaining part of the data path (110) and the remaining part of the control circuit (120) are configured to operate at the second voltage (VDD).

The invention relates to a soft start and overcurrent protection system and module for a magnetic drive conveying line and a control method. The system mainly comprises a soft start and overcurrent protection module, and the soft start and overcurrent protection module is connected in series between a switching power supply and a magnetic drive line driver. The soft start and overcurrent protection module comprises a main power module, a sampling and processing module, a control logic module and a state indication module, and the control logic module is respectively connected with the main power module, the sampling and processing module and the state indication module. Surge current of parallel power-on of multiple drivers is effectively suppressed, impact on a switching power supply and a capacitor is reduced, and the service life of key components of a system is prolonged.

An arrangement of a word line driver stage for a semiconductor memory device is illustrated. The present invention is characterized in that the word line driver stages are divided into a plurality of substages WD11-WD51 within an array of memory cells, a word line extending from either of the substages is uncoupled to the substage adjacent thereto, and the other word line proximate to the first word line is coupled to the other substage. Consequently, this arrangement is capable of reducing signal transmission delay and eliminating detrimental factors in current critical design standards and geometries.

A display device includes a plurality of pixels and at least one scanning-line driver circuit. The plurality of pixels each includes a light-emitting element and a pixel circuit electrically connected to the light-emitting element. The scanning-line driver circuit is electrically connected to the plurality of pixels. The pixel circuits each do not overlap the scanning-line driver circuit. A display region partly overlaps the scanning-line driver circuit. The pixel circuits are arranged in a matrix form having a plurality of rows and a plurality of columns. The pixel circuits each include a driving transistor configured to supply a current to the light-emitting element and a switching transistor configured to supply the current from the driving transistor to the light-emitting element. The switching transistor and the light-emitting element are electrically connected to each other through a relay wiring in each pixel.

A display device includes a backlight unit, a plurality of pixels, a gate-line driver circuit, a signal-line driver circuit, and a control substrate. The plurality of pixels is so that light from the light-emitting element is incident and is arranged in a matrix form with a plurality of row and a plurality of columns. The control substrate is electrically connected to the backlight unit, the gate-line driver circuit, and the signal-line driver circuit. The plurality of rows is composed of a plurality of row groups having the same number of rows and sequentially arranged in a column direction. The control substrate is configured to, in a first frame period, to supply the same potential to all of the plurality of pixels to supply the gate-line driver circuit and the signal-line driver circuit with a control signal for performing a pre-charge.

A microelectronic device comprises a first microelectronic device structure, a second microelectronic device structure vertically neighboring the first microelectronic device structure, and a third microelectronic device structure vertically neighboring the second microelectronic device structure. The first microelectronic device structure comprises a first memory array region and the third microelectronic device structure comprises a second memory array region. The second microelectronic device structure comprises a control logic region comprising a first sub word liner driver region comprising transistor structures in electrical communication with structures of the first microelectronic device structure and a second sub word line driver region comprising additional transistor structures in electrical communication with structures of the third microelectronic device structure. Related microelectronic devices, electronic systems, and methods are also described.

This application relates to word line characteristic monitors for memory devices and associated methods and systems. In one embodiment, the memory device includes a memory array including a word line (e.g., a local word line) and a word line driver coupled to the word line. When the memory device activates the word line driver, the memory device can generate a diagnostic signal in response to a word line voltage reaching a threshold value. Further, the memory device can generate a reference signal to compare the diagnostic signal to the reference signal. In some cases, if the diagnostic signal indicates a sign of degradation of a word line characteristic, the memory device can generate an alert signal based on comparing the diagnostic signal to the reference signal. The memory device can implement certain preventative and / or precautionary measures upon detecting the sign.

A variety of applications can include a memory device having memory cells that include capacitors as storage units with each capacitor having a plate coupled to a plate line. The memory device can include a plate line driver coupled to specific plate select lines of a set of multiple plate select lines. A plate line driver scheme can include transistors to provide a plate line voltage to a specific plate line and transistors to provide a system reference voltage to the specific plate line, where high state voltages and low state voltages can be applied to specific plate select lines to switch between placing the plate line voltage or the system reference voltage on the specific plate line. Plate select lines and the plate line driver scheme can be arranged to balance the number of plate select lines and device counts for the plate line drivers.

System arrangement for fault-tolerant and electromagnetically compatible control of a large number of execution units (AU), comprising: - a command unit (CU), wherein - the plurality of execution units (AE) into a plurality of serial subchains, each subchain having at least one execution unit (AE) along a first data line, segmented and each subchain having a line driver unit (LTE) upstream; and - the line driver units (LTE) are communicatively coupled to each other serially via a second data line, and the first line driver unit (LTE) connected in series is communicatively coupled to the command unit (CE) via the second data line, wherein the first data line is an electrical data line which always carries current, and the second data line is an optical data line.

A variety of applications can include an apparatus having a three-dimensional (3D) memory device with sub-access line drivers to access lines embedded in a memory array of the 3D memory device. A sub-access line driver to an access line to a tier of memory cells of the memory array can include two transistors coupled to each other and the access line. A first transistor of the two transistors can be coupled at one end of the access line and the second transistor of the two transistors can be coupled at the other end of the access.

The invention discloses a memory, an access method thereof and electronic equipment. The memory comprises a plurality of layers of memory cell arrays and a plurality of word lines which are stacked in the direction perpendicular to a substrate, word lines distributed in the same column or multiple layers of word lines distributed in the same column in the second direction are divided into K first word line groups, and the word lines of the same first word line group are connected to the same first word line driver through the corresponding gating sub-circuits; the word lines are divided into a plurality of second word line groups, each second word line group comprises K rows or K layers of word lines, and each word line in the K rows or K layers of word lines is connected to a different first word line driver; and the word lines of the same second word line group are respectively connected to the same second word line driver through the corresponding gating sub-circuits. According to the scheme provided by the embodiment, the number of word line drivers can be reduced.

A tunable termination resistor circuit associated with a line driver in a line on-chip is provided. The circuit includes a first current source and a first resistor coupled to the first current source and the line. The circuit also includes a first diode comprising a first terminal and a second terminal, the first terminal being coupled to the first resistor and the second terminal being coupled to a gate of a transistor, the gate being coupled to a gate voltage. The circuit also includes a capacitor coupled to the gate and the source of the transistor. The circuit also includes a third resistor coupled in series to a fourth resistor in the line each of the third resistor and the fourth resistor comprising a resistance changed by the gate voltage. There are other embodiments as well.

A memory and an access method therefor, and an electronic device. The memory comprises: a multi-layer memory cell array stacked in a direction perpendicular to a substrate, and a plurality of word lines (WL), wherein the word lines (WL) in the same column or at multiple layers and in the same column which are distributed in a second direction are divided into K first word line groups, and the word lines (WL) of the same first word line group are respectively connected to a same first word line driver SWD_X by means of corresponding gating sub-circuits (20); the word lines are divided into a plurality of second word line groups, each of the second word line groups comprises K rows or K layers of word lines, and each word line among the K rows or K layers of word lines is connected to a different first word line driver SWD_X; and the word lines of the same second word line group are respectively connected to a same second word line driver SWD_Y by means of corresponding gating sub-circuits.