141 results about "Line driver" patented technology

A transmitter in an interface circuit includes a first retimer circuit configured to serialize data by interleaving even bits of the data and odd bits of the data into a first bitstream, a second retimer circuit configured to serialize the data by interleaving even bits of the data and inverted versions of the odd bits of the data into a second bitstream, and line driver circuits configured to transmit the first bitstream over a communication link.

A microelectronic device includes a control circuitry structure and a memory array structure bonded to the control circuitry structure. The control circuitry structure includes a control circuitry region including two sense amplifier (SA) sub-regions including SA circuitry, and two sub-word line driver (SWD) sub-regions including SWD circuitry. The two SA sub-regions horizontally extend between opposing boundaries of the control circuitry region in a first direction. The two SWD sub-regions are interposed between the two SA sub-regions in a second direction and individually include a central region adjacent a respective one of the opposing horizontal boundaries of the control circuitry region, and two arm regions at opposing ends of the central region in the second direction and respectively horizontally protruding, in the first direction, from the central region. The memory array structure includes an array region horizontally overlapping the control circuitry region of the control circuitry structure and including memory cells.

A semiconductor device may include: a cell area in which a plurality of memory cells arranged in a first direction, a second direction and a third direction are disposed, the first direction and the second direction being parallel to an upper surface of a substrate and intersecting, and the third direction being perpendicular to the upper surface of the substrate; and a peripheral circuit area in which a word line driver connected to the plurality of memory cells through a plurality of word lines, a sense amplifier circuit connected to the plurality of memory cells through a plurality of bit lines, and a source line driver connected to the plurality of memory cells through a plurality of source lines, are disposed.

The embodiment of the invention discloses a delay adjustment circuit and a memory. The delay adjustment circuit comprises a detection circuit and a delay control circuit. And a detection circuit configured to detect an equivalent driving current of the target word line driver, and generate a selection control signal based on the equivalent driving current. The delay control circuit is coupled to the detection circuit and is configured to generate a corresponding delay signal in response to the selection control signal. Wherein the delay signal is output to the decoder and is used for applying delay to a decoding signal output to the target word line driver by the decoder.

Systems and methods for intelligent re-drivers capable of link monitoring and link training in accordance with embodiments of the invention are illustrated. A re-driver in accordance with a first embodiment includes a programmable linear equalizer capable of equalizing a transmitted analog signal to generate an equalized signal, and a variable gain amplifier capable of amplifying the equalized signal to produce an amplified signal. The re-driver further includes a line driver capable of generating an output signal based upon the amplified signal, and digital link adaptation circuitry that is capable of sampling the amplified signal to produce a sampled signal, generating programming parameters for the programmable linear equalizer based upon the sampled signal, and programming the programmable linear equalizer.

Disclosed herein is an electronic device, including a plurality of row decoders. Each row decoder includes decoder logic generating an initial word line signal and word line driver circuitry generating an inverse word line signal at an intermediate node from the initial word line signal, and generating a word line signal at a word line node from the inverse word line signal. A word line underdrive p-channel transistor has a source coupled to the intermediate node, a drain coupled to a word line underdrive sink, and a gate controlled based upon the inverse word line signal. Negative bias generation circuitry generates the negative bias voltage at a gate of the word line underdrive p-channel transistor when the initial word line signal is at a logic high, and couples the gate of the word line underdrive p-channel transistor to ground when the initial word line signal is at a logic low.

The present disclosure provides a memory circuit. The memory circuit includes: a plurality of word lines, a word line driver, and a first conductive line. The word line driver is electrically connected to the word lines. The word line driver includes: a plurality of first electronic components and a plurality of second electronic components. The plurality of first electronic components each electrically connected to the corresponding word line. The plurality of second electronic components each having a first terminal and a second terminal. The first terminal is electrically connected to the corresponding word line and the corresponding first electronic component. The first conductive line is electrically connected to the second terminal of the second electronic components. The first conductive line has a length proportional to the number of the word lines.

A semiconductor integrated circuit device capable of inputting a signal of a MEMS transducer 2 includes: a power supply circuit 11 for the MEMS transducer 2; an input amplifier 12 for inputting and amplifying a signal of the MEMS transducer 2; a line driver 13 for amplifying an output from the input amplifier 12 and allowing for driving of a load connected to an output terminal T3, the line driver 13 having an input terminal; and the output terminal T3 for outputting an output of the line driver 13, wherein the power supply circuit 11, the input amplifier 12, and the line driver 13 are integrally formed on a semiconductor substrate, and wherein a gain setting circuit 14 for determining gain of the line driver 13 and a DC potential of the output terminal T3 is connected to the input terminal of the line driver 13.

A memory device may be provided herein. The memory device may comprise a memory block configured to include a first select line, word lines, a second select line, a channel layer, first select transistors, second select transistors, and memory cells; a voltage generator configured to produce a turn-on voltage and a turn-off voltage applied to the first and second select lines, and to produce a programming voltage and a pass voltage applied to the word lines; a source line driver configured to produce a pre-charge voltage applied to the source line; and a side buffer group configured to apply a programming enable voltage and a programming lock voltage to bit lines.and a control circuit designed to determine a reference position and to control the voltage generator, source line driver, and side buffer group to adjust the time required to preload the channel layer.

The application relates to a line driver impedance calibration overvoltage protection circuit and method, which is applied to an Ethernet and comprises a first impedance calibration circuit and an overvoltage protection circuit. The first impedance calibration circuit comprises a plurality of first transmission gates, two ends of each first transmission gate are connected with a first resistor and a second resistor respectively, and the first transmission gate can be controlled to be turned on or turned off to adjust the impedance between the line driver and the first connection end to a preset value. The overvoltage protection circuit is used for detecting the amplitude of the opposite end signal received by the hybrid circuit, comparing the amplitude of the opposite end signal with a predetermined threshold value, outputting a comparison signal, and controlling the amplitude of the local end signal sent by the line driver according to the comparison signal. The application can realize impedance calibration, the transmission gate works at the intermediate voltage, the voltage interval range is smaller, the overvoltage of the transmission gate is protected, the tolerance of the reliability of the Ethernet is better, the amplitude of the local end is limited, and then the overvoltage protection of the impedance calibration is realized.

The application discloses a flat valve repairing device, which comprises a fixing device, a valve cover disassembling device, a valve seat disassembling device, a turnover device, a valve cover fastening device, a packing sealing device and an ultrasonic cleaning device. The fixing device is used for fixing the flat valve; the valve cover disassembling device is used for disassembling the valve cover of the flat valve; the valve seat disassembling device is used for disassembling the valve seat; the turnover device is used for rotating the flat valve; the valve cover fastening device is used for clamping the valve cover; the packing sealing device is used for sealing the packing into the valve cover of the flat valve; and the ultrasonic cleaning device is used for cleaning the disassembled parts. The application further discloses an automatic control system of the flat valve repairing device, which realizes the automatic disassembling, assembling and packing sealing of the flat valve through an industrial control touch screen, a PLC controller, an A / D converter, a signal conditioner, a circuit driver and a power component driver. The application realizes the automatic operation of the disassembling and packing sealing of the flat valve, has high working efficiency and low labor intensity, and is suitable for all scenes in which the flat valve needs to be disassembled.

A tunable termination resistor circuit associated with a line driver in a line on-chip is provided. The circuit includes a first current source and a first resistor coupled to the first current source and the line. The circuit also includes a first diode comprising a first terminal and a second terminal, the first terminal being coupled to the first resistor and the second terminal being coupled to a gate of a transistor, the gate being coupled to a gate voltage. The circuit also includes a capacitor coupled to the gate and the source of the transistor. The circuit also includes a third resistor coupled in series to a fourth resistor in the line each of the third resistor and the fourth resistor comprising a resistance changed by the gate voltage. There are other embodiments as well.

1. The name of the design product: cold light line driver. 2. The use of the design product: controller for controlling cold light line, cold light product, etc. 3. The design points of the design product: in shape. 4. The picture or photo that best shows the design points: perspective view 1.

A memory device with high storage capacity and low power consumption is provided. The memory device includes a first layer and a second layer including the first layer. The first layer includes a circuit, and the second layer includes a first memory cell. The circuit includes a bit line driver circuit and / or a word line driver circuit which transmits(s) a signal to the first memory cell. The first memory cell includes a first transistor, a second transistor, a conductor, and an MTJ element. The MTJ element includes a free layer. The free layer is electrically connected to the conductor. The first terminal of the first transistor is electrically connected to a first terminal of the second transistor through the conductor. The free layer is positioned above the conductor. The circuit includes a transistor containing silicon in a channel formation region, and each of the first transistor and the second transistor contains a metal oxide in a channel formation region.

A microelectronic device includes a memory array structure and a control circuitry structure overlying and bonded to the memory array structure. The memory array structure includes memory cells, digit lines, and word lines. The control circuitry structure includes a control circuitry region, digit line contact sections, and word line contact sections. The control circuitry region includes sense amplifier sections including sense amplifiers, and sub-word line driver sections including sub-word line drivers. The digit line contact sections are horizontally adjacent to the sense amplifier sections in a first direction and include contact structures coupled to the sense amplifiers and the digit lines. The word line contact sections are horizontally adjacent to the sub-word line driver sections in a second direction orthogonal to the first direction and include additional contact structures coupled to the sub-word line drivers and the word lines. Additional microelectronic devices, memory devices, and electronic systems are also described.

A memory device with high storage capacity and low power consumption is provided. The memory device includes a first layer and a second layer including the first layer. The first layer includes a circuit, and the second layer includes a first memory cell. The circuit includes a bit line driver circuit and / or a word line driver circuit which transmits(s) a signal to the first memory cell. The first memory cell includes a first transistor, a second transistor, a conductor, and an MTJ element. The MTJ element includes a free layer. The free layer is electrically connected to the conductor. The first terminal of the first transistor is electrically connected to a first terminal of the second transistor through the conductor. The free layer is positioned above the conductor. The circuit includes a transistor containing silicon in a channel formation region, and each of the first transistor and the second transistor contains a metal oxide in a channel formation region.

This invention provides an optimized system for improving the slew rate of a Line Driver, comprising a differential input module, a bias current module, an amplification module, an active load module, and a mirror load module. The differential input module receives the input signal and converts the voltage signal into a current signal. The bias current module provides a stable bias current to the circuit. The amplification module receives the current signal from the differential input module and achieves voltage gain. The amplification module is electrically connected to the active load module. The active load module can improve the amplification gain of the amplification module, replicate the current, and stabilize the output node. The mirror load module can replicate the signal amplification path of the amplification module to achieve symmetrical output, thereby improving the signal amplification effect and anti-interference reliability of the circuit and solving the problem of limited slew rate in traditional optimized systems for Line Drivers.

The utility model provides an optical fiber extender, which relates to the technical field of optical fiber extension equipment, comprises an SDI (Serial Digital Interface) line equalizer, an RECLOCK and line driver, a power supply module, an SDI video transmission channel, a single-fiber bidirectional optical module, an RS485 signal channel and a TALLY signal channel, and solves the problem that when a common cable is used for long-distance transmission of a higher-speed signal, the power supply module cannot be connected with the SDI video transmission channel. The phenomena of poor output signal quality, easy external interference and the like always occur; meanwhile, the transmission distance is short, the long-distance transmission requirement of occasions such as multimedia information issuing cannot be met, in practical application, a traditional cable is often difficult to support the integrity and stability of high-quality audio and video signals in long-distance transmission due to limitation of physical characteristics and transmission bandwidth of the traditional cable, and according to the research of Smitet al. (2020), the long-distance transmission requirement of the high-quality audio and video signals in the long-distance transmission process cannot be met, and the long-distance transmission requirement of the high-quality audio and video signals in the long-distance transmission process cannot be met. After the transmission distance of the traditional cable exceeds 100 meters, the signal attenuation can reach about 3dB, which has a significant influence on the image quality.

The invention provides a camera triggering circuit, method, device and equipment. The circuit comprises a coupling circuit, a differential driving circuit and a camera driving circuit which are connected in sequence, the coupling circuit comprises an optical coupler, the input end of the optical coupler is connected with an initial single-ended signal, and the output end of the optical coupler outputs a TTL signal; the differential driving circuit comprises a differential line driver chip, the input end of the differential line driver chip is connected with a TTL signal, and the output end of the differential line driver chip outputs a differential signal; the camera driving circuit comprises a differential line connector chip and a switch element which are connected, the input end of the differential line connector chip is connected with a differential signal, the output end of the differential line connector chip outputs a trigger level, and the switch element is connected with the trigger level and outputs a signal for triggering camera driving. Therefore, the optical coupler is utilized to realize electrical isolation and block common-mode noise, and differential signals are utilized to improve the anti-interference capability in a complex electromagnetic environment, so that the anti-interference capability of the whole circuit can be remarkably improved.

A semiconductor memory device is provided. The apparatus includes: a first word line in N layers, the first word line extending from a first stack region toward a first step region; a second word line in the N layers, the second word line extending from the second stack region toward the second step region; a first memory cell provided in the first stack region; a second memory cell provided in the second stack region; n first word line contacts connected to the first word line in the first step region; and N second word line contacts connected to the second word line in the second step region. A first word line in a Kth layer (K is an integer from 1 to N) among the first word lines and a second word line in an (N-K + 1) th layer among the second word lines are commonly connected to one sub-word line driver.

A microelectronic device includes a memory array structure and a control circuitry structure vertically overlying and bonded to the memory array structure. The memory array structure includes array regions respectively including memory cells, digit lines, and word lines within horizontal areas thereof. The control circuitry structure includes control circuitry regions, sense amplifier (SA) sections including SA circuitry, and sub-word line driver (SWD) sections including SWD circuitry. The control circuitry regions horizontally overlap the array regions of the memory array structure. The SA sections respectively horizontally overlap each of two of the control circuitry regions horizontally neighboring one another in a first direction. The SWD sections are respectively interposed between two other of the control circuitry regions horizontally neighboring one another in a second direction orthogonal to the first direction. Additional microelectronic devices, memory devices, and electronic systems are also described.

An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bias voltage for word line driver and a configuration of the current mirroring circuit to inhibit drop of a voltage on the bit line below a bit flip voltage during execution of the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.

In certain aspects, a memory device includes an array of memory cells, word lines respectively coupled to rows of the memory cells, and a peripheral circuit coupled to the array of memory cells through the word lines and configured to read a select row of the rows of the memory cells. The peripheral circuit includes a word line driver coupled to the select row through a select word line of the word lines and to an unselect row of the rows of the memory cells through an unselect word line of the word lines, and configured to apply a pass voltage to the unselect word line, and discharge the unselect word line from the pass voltage to a first recovery voltage that is greater than a supply voltage of the array of memory cells.

This application discloses a wired transmitter with overvoltage protection, comprising a digital-to-analog converter (DAC) and a line driver. The DAC generates a plurality of first output signals based on a digital code, wherein a first circuit in the DAC operates in a first voltage domain, a second circuit in the DAC operates in a second voltage domain, and the upper limit of the first voltage domain is lower than the upper limit of the second voltage domain. The line driver operates in the second voltage domain and generates a plurality of second output signals based on the first output signals, wherein each of the DAC and the line driver is implemented via a plurality of transistors corresponding to the first voltage domain.

An example memory device includes a first wafer that includes a first sub-memory block connected to first to n-th word lines, a first bit line, a first string selection line, and a first ground selection line, and a second wafer that is stacked on the first wafer in a vertical direction and includes a second sub-memory block connected to (n+1)-th to 2n-th word lines, a second bit line, a second string selection line, and a second ground selection line. The first to n-th word lines are respectively connected to the (n+1)-th to 2n-th word lines and share first to n-th word line drivers with the (n+1)-th to 2n-th word lines. The first bit line is connected to the second bit line and shares a first page buffer with the second bit line.

To provide a display device in which images can be rewritten for only an optional region, or a display device capable of partial driving in which a circuit structure including wires is simplified.SOLUTION: Shift of a selection signal in a shift register included in a scan line driving circuit and supply of the selection signal to a scan line are independently controlled. Thus, images can be rewritten only for an optional region. This operation is achieved by providing a wire that supplies a clock signal or a signal representing a fixed potential. Therefore, the display device including such wires is a display device capable of partial driving, in which a circuit structure including the wires is simplified.SELECTED DRAWING: Figure 3

A wired transmitter includes a digital-to-analog converter (DAC) and a line driver. The DAC generates first output signals according to a digital code, wherein a first circuit in the DAC operates in a first voltage domain and a second circuit of the DAC operates in a second voltage domain, and an upper limit of the first voltage domain is lower than an upper limit of the second voltage domain. The line driver operates in the second voltage domain, and generates second output signals according to the first output signals. Each of the DAC and the line driver is implemented by transistors corresponding to the first voltage domain.

A semiconductor memory device is provided. The device includes: first word lines in N layers, the first word lines extending from a first stack region toward first stair regions; second word lines in the N layers, the second word lines extending from a second stack region toward second stair regions; first memory cells provided in the first stack region; second memory cells provided in the second stack region; N first word line contacts connected to the first word lines in the first stair regions; and N second word line contacts connected to the second word lines in the second stair regions. A first word line in a Kth layer (K being an integer from 1 to N) among the first word lines and a second word line in an (N−K+1)th layer among the second word lines are commonly connected to one sub-word line driver.

A semiconductor device including a main word line driver connected to a metal line and configured to transmit a main word line signal to the metal line in order to access at least one of memory cells that are included in a core circuit, the core circuit connected to the metal line and configured to transmit, as a delay main word line signal, the main word line signal that is received through the metal line. The semiconductor device including a test mode control circuit connected to the metal line. The test mode control circuit configured to receive the delay main word line signal through the metal line. The test mode control circuit configured to perform a test mode in which the test mode control circuit drives the metal line in response to the delay main word line signal.

Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.