258 results about "Line driver" patented technology

A method of fabricating a semiconductor device includes forming a memory cell array stack including a vertical stack of pad portions over a first substrate, forming first bonding pads each coupled to a different one of the pad portions in the vertical stack, forming control circuits including a plurality of sub-word line drivers over a second substrate, forming multi-layer level metal wiring coupled to the sub-word line drivers, forming second bonding pads coupled to the multi-layer level metal wiring, and performing a wafer bonding process for electrical coupling between the memory cell array stack and the control circuits.

A memory device includes a peripheral circuit structure and a cell array structure, in which the cell array structure overlaps the peripheral circuit structure in a first direction, in which the cell array structure includes a merged sub array in which at least four sub array regions are merged, in which the merged sub array comprises a memory cell region including: a plurality of first bit lines and a plurality of second bit lines; and a plurality of first word lines and a plurality of second word lines, in which the peripheral circuit structure comprises a merged bank in which at least four banks are merged, and in the merged bank comprises: a first bit line sense amplifier (BLSA), a second BLSA, a first sub word line driver (SWD), a second SWD, and in which a spare space is defined between the first bit lines and the second bit lines.

A transmitter in an interface circuit includes a first retimer circuit configured to serialize data by interleaving even bits of the data and odd bits of the data into a first bitstream, a second retimer circuit configured to serialize the data by interleaving even bits of the data and inverted versions of the odd bits of the data into a second bitstream, and line driver circuits configured to transmit the first bitstream over a communication link.

A semiconductor memory device includes a first chip and a second chip. The first chip includes a first cell array mat and a second cell array mat adjacent to the first cell array mat. The second chip has a stacked structure with the first chip and includes a first sub-word line driver configured to generate a first drive signal applied to the first word lines from one side of each of the first and second cell array mats, and a second sub-word line driver configured to generate a second drive signal applied to the second word lines from an opposite side of each of the first and second cell array mats.

A memory device includes a row decoder connected to a plurality of word lines of each of a plurality of memory blocks. The row decoder includes a main word line driver circuit commonly connected to the plurality of memory blocks and configured to generate first main word line driving signals, second main word line driving signals, and sub-word line driving signals based on row address signals, and a sub-word line driving signal connected to each of the plurality of memory blocks and configured to activate one word line from among the plurality of word lines using a NOR logic circuit to which the first main word line driving signals, the second main word line driving signals, and the sub-word line driving signals are connected.

In certain aspects, a memory device includes memory strings each including a drain select gate (DSG) transistor, memory cells, and a source select gate (SSG) transistor, and a peripheral circuit coupled to the memory strings. The peripheral circuit is configured to, in a program operation, program a select memory cell of the memory cells in a select memory string of the memory strings, and inhibit an unselect memory cell of the memory cells in an unselect memory string of the memory strings. The peripheral circuit includes a word line driver configured to in a pre-pulse period and a post-pulse period in a first loop of the program operation, turn off the DSG transistor in the unselect memory string, and in at least one of a pre-pulse period or a post-pulse period in a second loop of the program operation after the first loop, turn on the DSG transistor in the unselect memory string.

The embodiment of the invention provides a memory, an operation method thereof and electronic equipment. The memory includes: a memory cell array including a plurality of memory cells organized into a plurality of memory cell sets, conductivity values of the memory cells in one memory cell set being determined based on a weight vector; word lines and bit lines coupled to the plurality of memory cells; the word line driver is coupled to the word lines, and is configured to apply a plurality of read voltages to the plurality of word lines coupled to each memory cell set, respectively, voltage values of some of the plurality of read voltages being determined based on an input vector; the reading circuit is coupled to the bit line and is configured to obtain a plurality of output currents of the bit line coupled to each memory cell set in the plurality of memory cell sets, and calculate and measure the plurality of output currents of each memory cell set to obtain a first measurement signal of each memory cell set; wherein different first measurement signals are used for representing different distances between the weight vector and the input vector.

The present disclosure provides a three-dimensional NAND memory device, comprising a memory array comprising blocks, each block includes first memory cells and second memory cells connected in series to a bit line, a word line driver, and a controller configured to control the word line driver to: performing a programming operation on a memory cell in the first memory cells, the memory cell is controlled by a selected word line of first word lines corresponding to the first memory cells, the first word lines comprising first unselected word lines adjacent to the selected word line, and the performing the programming operation comprises: applying a programming voltage signal to the selected word line to program the memory cell into a target state; applying a first pass voltage to the first unselected word lines; and applying a second pass voltage to second word lines corresponding to the second memory cells.

A microelectronic device includes a control circuitry structure and a memory array structure bonded to the control circuitry structure. The control circuitry structure includes a control circuitry region including two sense amplifier (SA) sub-regions including SA circuitry, and two sub-word line driver (SWD) sub-regions including SWD circuitry. The two SA sub-regions horizontally extend between opposing boundaries of the control circuitry region in a first direction. The two SWD sub-regions are interposed between the two SA sub-regions in a second direction and individually include a central region adjacent a respective one of the opposing horizontal boundaries of the control circuitry region, and two arm regions at opposing ends of the central region in the second direction and respectively horizontally protruding, in the first direction, from the central region. The memory array structure includes an array region horizontally overlapping the control circuitry region of the control circuitry structure and including memory cells.

A semiconductor device may include: a cell area in which a plurality of memory cells arranged in a first direction, a second direction and a third direction are disposed, the first direction and the second direction being parallel to an upper surface of a substrate and intersecting, and the third direction being perpendicular to the upper surface of the substrate; and a peripheral circuit area in which a word line driver connected to the plurality of memory cells through a plurality of word lines, a sense amplifier circuit connected to the plurality of memory cells through a plurality of bit lines, and a source line driver connected to the plurality of memory cells through a plurality of source lines, are disposed.

A line driver circuit include a multitude of PMOS and NMOS transistors. A first PMOS transistor receives an output voltage of a first level converter. A second PMOS transistor receives a first reference voltage. A third and fourth PMOS transistors receive an output voltage of a second voltage level converter. The source terminal of the first PMOS transistor receives the supply voltage. The drain terminal of the fourth PMOS transistor is coupled to an output terminal of the line driver circuit. A first NMOS transistor receives an input signal. A second NMOS transistor receives a second reference voltage. A third and fourth NMOS transistors receive an output voltage of a third level converter. The first NMOS transistor receives a ground potential. The drain terminal of the fourth NMOS transistor is coupled to the output terminal of the line driver. The first, second and third voltage converters receive the input signal.

The invention provides a memory. The memory comprises a memory array chip and a logic circuit chip which are bonded, each storage block corresponds to at least one row decoder, one secondary decoder and at least one word line driver, each row decoder provides a first number of main decoding signal lines, and the secondary decoder provides a second number of secondary decoding signal lines; the product of the sum of the number of main decoding signals of all row decoders corresponding to a single storage block and the second number is the same as the number of word lines of the single storage block; the word line drivers are used for driving the word lines of the corresponding storage blocks according to the main decoding signals and the secondary decoding signals, and the sum of the number of driving ports of all the word line drivers corresponding to a single storage block is the same as the number of the word lines of the storage block; the row decoder, the secondary decoder and the word line driver are all arranged on the logic circuit chip. According to the device, the delay between the row decoder and the word line driver can be reduced, the time sequence and the sensing margin of the memory are optimized, and the wiring difficulty of the main decoding signal line is reduced.

The embodiment of the invention discloses a delay adjustment circuit and a memory. The delay adjustment circuit comprises a detection circuit and a delay control circuit. And a detection circuit configured to detect an equivalent driving current of the target word line driver, and generate a selection control signal based on the equivalent driving current. The delay control circuit is coupled to the detection circuit and is configured to generate a corresponding delay signal in response to the selection control signal. Wherein the delay signal is output to the decoder and is used for applying delay to a decoding signal output to the target word line driver by the decoder.

Technology for driving word lines in 3D memory. Even numbered word lines in a 3D memory are biased from one end of the word lines and odd numbered word lines in the 3D memory are biased from the other end of the word lines. The word lines may reside in a stack of alternating conductive and dielectric layers, with the conductive layers serving as the word lines as well as select lines. The ends of the word lines on one side of the stack may form a first staircase and the ends of the word lines on an opposite side of the stack may form a second staircase. A first set of word line driver transistors connect to the even numbered word lines at the first staircase and a second set of word line driver transistors connect to the odd numbered word lines at the second staircase.

A word-line drive circuit, a word-line driver and a storage device are provided. The word-line drive circuit includes at least two SWDs. Each SWD is connected to an MWL for providing an enable signal and a sub word line. The SWD includes a holding transistor. A first end and a second end of the holding transistor are respectively connected to different sub word lines, and a gate receives a second drive signal. The SWD is configured to provide a first drive signal to a selected sub word line in response to the first drive signal and the enable signal, the selected sub word line being a sub word line connected to the first end or second end of the holding transistor, and to conduct the first end and the second end of the holding transistor in response to the first drive signal, the enable signal and the second drive signal.

A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.

Systems and methods for intelligent re-drivers capable of link monitoring and link training in accordance with embodiments of the invention are illustrated. A re-driver in accordance with a first embodiment includes a programmable linear equalizer capable of equalizing a transmitted analog signal to generate an equalized signal, and a variable gain amplifier capable of amplifying the equalized signal to produce an amplified signal. The re-driver further includes a line driver capable of generating an output signal based upon the amplified signal, and digital link adaptation circuitry that is capable of sampling the amplified signal to produce a sampled signal, generating programming parameters for the programmable linear equalizer based upon the sampled signal, and programming the programmable linear equalizer.

Disclosed herein is an electronic device, including a plurality of row decoders. Each row decoder includes decoder logic generating an initial word line signal and word line driver circuitry generating an inverse word line signal at an intermediate node from the initial word line signal, and generating a word line signal at a word line node from the inverse word line signal. A word line underdrive p-channel transistor has a source coupled to the intermediate node, a drain coupled to a word line underdrive sink, and a gate controlled based upon the inverse word line signal. Negative bias generation circuitry generates the negative bias voltage at a gate of the word line underdrive p-channel transistor when the initial word line signal is at a logic high, and couples the gate of the word line underdrive p-channel transistor to ground when the initial word line signal is at a logic low.

The display device includes: a flexible display panel including a display portion in which scanning lines and signal lines cross each other; a supporting portion for supporting an end portion of the flexible display panel; a signal line driver circuit for outputting a signal to the signal line, which is provided for the supporting portion; and a scanning line driver circuit for outputting a signal to the scanning line, which is provided for a flexible surface of the display panel in a direction which is perpendicular or substantially perpendicular to the supporting portion.

The present disclosure provides a memory circuit. The memory circuit includes: a plurality of word lines, a word line driver, and a first conductive line. The word line driver is electrically connected to the word lines. The word line driver includes: a plurality of first electronic components and a plurality of second electronic components. The plurality of first electronic components each electrically connected to the corresponding word line. The plurality of second electronic components each having a first terminal and a second terminal. The first terminal is electrically connected to the corresponding word line and the corresponding first electronic component. The first conductive line is electrically connected to the second terminal of the second electronic components. The first conductive line has a length proportional to the number of the word lines.

A semiconductor integrated circuit device capable of inputting a signal of a MEMS transducer 2 includes: a power supply circuit 11 for the MEMS transducer 2; an input amplifier 12 for inputting and amplifying a signal of the MEMS transducer 2; a line driver 13 for amplifying an output from the input amplifier 12 and allowing for driving of a load connected to an output terminal T3, the line driver 13 having an input terminal; and the output terminal T3 for outputting an output of the line driver 13, wherein the power supply circuit 11, the input amplifier 12, and the line driver 13 are integrally formed on a semiconductor substrate, and wherein a gain setting circuit 14 for determining gain of the line driver 13 and a DC potential of the output terminal T3 is connected to the input terminal of the line driver 13.

A memory device may be provided herein. The memory device may comprise a memory block configured to include a first select line, word lines, a second select line, a channel layer, first select transistors, second select transistors, and memory cells; a voltage generator configured to produce a turn-on voltage and a turn-off voltage applied to the first and second select lines, and to produce a programming voltage and a pass voltage applied to the word lines; a source line driver configured to produce a pre-charge voltage applied to the source line; and a side buffer group configured to apply a programming enable voltage and a programming lock voltage to bit lines.and a control circuit designed to determine a reference position and to control the voltage generator, source line driver, and side buffer group to adjust the time required to preload the channel layer.

The invention relates to a semiconductor device having a row decoder circuit. An example apparatus includes first and second arrays of memory cells arranged in a first direction; and a plurality of first and second sub-word line drivers, a plurality of main word line drivers, and a plurality of level shift circuits each disposed on an intermediate region between the first and second memory cell arrays. The first and second sub-word line drivers are arranged in a second direction and along the first and second memory cell arrays, respectively. The main word line drivers are arranged in the second direction and adjacently arranged along the plurality of second sub-word line drivers. The level shift circuits are arranged in the second direction and adjacently arranged along the plurality of first sub word line drivers. The level shift circuit is configured to provide voltage level shift signals to the plurality of main word line drivers, respectively.

The application relates to a line driver impedance calibration overvoltage protection circuit and method, which is applied to an Ethernet and comprises a first impedance calibration circuit and an overvoltage protection circuit. The first impedance calibration circuit comprises a plurality of first transmission gates, two ends of each first transmission gate are connected with a first resistor and a second resistor respectively, and the first transmission gate can be controlled to be turned on or turned off to adjust the impedance between the line driver and the first connection end to a preset value. The overvoltage protection circuit is used for detecting the amplitude of the opposite end signal received by the hybrid circuit, comparing the amplitude of the opposite end signal with a predetermined threshold value, outputting a comparison signal, and controlling the amplitude of the local end signal sent by the line driver according to the comparison signal. The application can realize impedance calibration, the transmission gate works at the intermediate voltage, the voltage interval range is smaller, the overvoltage of the transmission gate is protected, the tolerance of the reliability of the Ethernet is better, the amplitude of the local end is limited, and then the overvoltage protection of the impedance calibration is realized.

The application discloses a flat valve repairing device, which comprises a fixing device, a valve cover disassembling device, a valve seat disassembling device, a turnover device, a valve cover fastening device, a packing sealing device and an ultrasonic cleaning device. The fixing device is used for fixing the flat valve; the valve cover disassembling device is used for disassembling the valve cover of the flat valve; the valve seat disassembling device is used for disassembling the valve seat; the turnover device is used for rotating the flat valve; the valve cover fastening device is used for clamping the valve cover; the packing sealing device is used for sealing the packing into the valve cover of the flat valve; and the ultrasonic cleaning device is used for cleaning the disassembled parts. The application further discloses an automatic control system of the flat valve repairing device, which realizes the automatic disassembling, assembling and packing sealing of the flat valve through an industrial control touch screen, a PLC controller, an A / D converter, a signal conditioner, a circuit driver and a power component driver. The application realizes the automatic operation of the disassembling and packing sealing of the flat valve, has high working efficiency and low labor intensity, and is suitable for all scenes in which the flat valve needs to be disassembled.

A tunable termination resistor circuit associated with a line driver in a line on-chip is provided. The circuit includes a first current source and a first resistor coupled to the first current source and the line. The circuit also includes a first diode comprising a first terminal and a second terminal, the first terminal being coupled to the first resistor and the second terminal being coupled to a gate of a transistor, the gate being coupled to a gate voltage. The circuit also includes a capacitor coupled to the gate and the source of the transistor. The circuit also includes a third resistor coupled in series to a fourth resistor in the line each of the third resistor and the fourth resistor comprising a resistance changed by the gate voltage. There are other embodiments as well.

1. The name of the design product: cold light line driver. 2. The use of the design product: controller for controlling cold light line, cold light product, etc. 3. The design points of the design product: in shape. 4. The picture or photo that best shows the design points: perspective view 1.

A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.

A memory device with high storage capacity and low power consumption is provided. The memory device includes a first layer and a second layer including the first layer. The first layer includes a circuit, and the second layer includes a first memory cell. The circuit includes a bit line driver circuit and / or a word line driver circuit which transmits(s) a signal to the first memory cell. The first memory cell includes a first transistor, a second transistor, a conductor, and an MTJ element. The MTJ element includes a free layer. The free layer is electrically connected to the conductor. The first terminal of the first transistor is electrically connected to a first terminal of the second transistor through the conductor. The free layer is positioned above the conductor. The circuit includes a transistor containing silicon in a channel formation region, and each of the first transistor and the second transistor contains a metal oxide in a channel formation region.

A microelectronic device includes a memory array structure and a control circuitry structure overlying and bonded to the memory array structure. The memory array structure includes memory cells, digit lines, and word lines. The control circuitry structure includes a control circuitry region, digit line contact sections, and word line contact sections. The control circuitry region includes sense amplifier sections including sense amplifiers, and sub-word line driver sections including sub-word line drivers. The digit line contact sections are horizontally adjacent to the sense amplifier sections in a first direction and include contact structures coupled to the sense amplifiers and the digit lines. The word line contact sections are horizontally adjacent to the sub-word line driver sections in a second direction orthogonal to the first direction and include additional contact structures coupled to the sub-word line drivers and the word lines. Additional microelectronic devices, memory devices, and electronic systems are also described.