56 results about "Write-once" patented technology

In a preferred integrated circuit embodiment, a write-once memory array includes at least one test bit line which provides a respective test memory cell at the far end of each respective word line relative to its word line driver, and further includes at least one test word line which provides a respective test memory cell at the far end of each respective bit line relative to its bit line driver. An intra-layer short between word lines may be detected, such as during manufacturing testing, by biasing adjacent word lines to different voltages and detecting whether any leakage current flowing from one to another exceeds that normally accounted for by the memory cells and other known circuits. Intra-layer bit line shorts and inter-layer word line and bit line shorts may also be similarly detected. An "open" in a word line or bit line may be detected by trying to program the test memory cell at the far end of each such word line or bit line. If successfully programmed, the continuity of each word line and bit line is assured, and the programming circuitry for each word line and bit line is also known to be functional.

The invention discloses a fault-tolerance method for a high-reliability disk array. The fault-tolerance method comprises the following steps: when a data write error occurs, confirming storage space of a disk in which data with the write error is, and carrying out bad block marking on the storage space; when a data read error occurs, judging if the disk array is complete, if so, working out current position data by checking, writing the data in a corresponding position of the disk, and otherwise, carrying out bad block marking on the storage space with the data read error; and when a next write operation is carried out, carrying out the write operation on the storage space subjected to bad block marking, if the storage space is successfully written and the subsequent read operation is also successful, removing a bad block mark of the storage space, and on the contrary, remaining the bad block mark. According to the fault-tolerance method, the technical problems that only bad block information of read-write errors is recorded and bad blocks are not repaired in a disk array system and the disk array system is limited by a fault-tolerance range in the prior art are solved; and the fault-tolerance method is in particular suitable for occasions with low data accuracy requirements.

The concurrent memory control turbo decoder solution of this invention uses a single port main memory and a simplified scratch memory. This approach uses an interleaved forward-reverse addressing which greatly relieves the amount of memory required. This approach is in marked contrast to conventional turbo decoders which employ either a dual port main memory or a single port main memory in conjunction with a complex ping-ponged scratch memory. In the system of this invention, during each cycle accomplishes one read and one write operation in the scratch memories. If a particular location in memory, has been read, then that location is free. The next write cycle can use that location to store its data. Similarly a simplified beta RAM is implemented using a unique addressing scheme which also obviates the need for a complex ping-ponged beta RAM.

A secure boot method includes: obtaining a certificate digest at a digest processor from a write-once, always-on memory; calculating a flash digest using the digest processor by cryptographically processing a sensitive information image; and comparing, using the digest processor, the flash digest with the certificate digest.

A data processing apparatus acquires content, generates an encryption key by using an initial value written in an unwritten memory block in a write-once recording medium, encrypts the content by using the encryption key, and writes to the write-once recording medium the encrypted content and an address table for identifying the memory block storing the initial value used for generating the encryption key.

A method of recording a temporary defect list on a write-once recording medium, a method of reproducing the temporary defect list, an apparatus for recording and/or reproducing the temporary defect list, and the write-once recording medium. The method of recording a temporary defect list for defect management on a write-once recording medium includes recording the temporary defect list, which is created while data is recorded on the write-once recording medium, in at least one cluster of the write-once recording medium, and verifying if a defect is generated in the at least one cluster. Then, the method includes re-recording data originally recorded in a defective cluster in another cluster, and recording pointer information, which indicates a location of the at least one cluster where the temporary defect list is recorded, on the write-once recording medium.

There is provided an information management apparatus which can make it impossible to read out data recorded on a write-once type recordable optical disk as required and the usefulness thereof is enhanced. When recorded data is destroyed on the write-once type recordable optical disk, data modulated by a modulation system of the same run length restriction as run length restriction of a modulation system used for recording data is overwritten and recorded, data is overwritten and recorded by use of patterns in which the frequency of occurrence of spaces of the longest code is higher than the frequency of occurrence of the modulation system used for recording data, or data is overwritten and recorded by use of successive patterns of the shortest code in the run length restriction of the modulation system used for recording data.

The invention discloses a metadata management method and device, relates to the technical field of data storage, and the metadata management method and device are helpful for reducing read amplification and saving cache resources. The method comprises the steps of receiving a write request, wherein the write request comprises first data and a first logic address range; wherein the first logic address range is an address range of a storage space used for storing the first data in the main memory; determining a first address in a cache according to the write request, and writing the first data into a first data storage unit indicated by the first address; wherein the first address comprises an identifier of the first data storage unit, an initial storage position of the first data in the first data storage unit and the length of the first data; generating metadata of the first data and writing the metadata into a target metadata storage unit; wherein the preset logic address range corresponding to the target metadata storage unit comprises a first logic address range; establishing a sequential relationship between the metadata of the first data and the write-in time of the target metadata; wherein the target metadata is the metadata written into the target metadata storage unit last time.

The invention relates to the field of distributed storage, and provides a data access method and device, a client and a storage medium. The method comprises the steps of: obtaining to-be-written data, wherein the to-be-written data comprises a plurality of target data blocks organized by erasure codes, each target data block needs to be written into each storage node, each storage node comprises old data written last time; sending a write request to each storage node, so that each storage node writes the corresponding target data block based on the respective received write request and feeds back a write response message to the client; and if the number of the target storage nodes feeding back the write response message of successful writing is greater than a preset number, sending deletion commands to the target storage nodes according to the number of the target storage nodes, so that the target storage nodes delete respective old data according to the respective received deletion commands. According to the method, the high consistency of data writing can be ensured, and the requirement of high performance can also be ensured.

A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which a plurality of memory cells that can store multi-value data are arranged, the memory cells having a plurality of pages, and a controller that performs data transfer between a host apparatus and the second storing unit via the first storing unit. The controller includes a save processing unit that backs up, when, before data is written in the second storing unit in a write-once manner, data is written in a lower order page of a memory cell same as that of a page in which the data is written, the data of the lower order page and a broken-information-restoration processing unit that restores, when the data in the lower order page is broken, the broken data using the backed-up data.

An integrated-circuit device comprises a processor, a hardware key-storage system, and a key bus. The hardware key-storage system comprises a non-volatile key storage memory, which includes a key register, for storing a cryptographic key, and an address register, for storing a destination memory address for the cryptographic key. The hardware key-storage system further comprises output logic for sending the cryptographic key over the key bus to the destination memory address, and write-once logic for preventing an address being written to the address register unless the address register is in an erased state.

On the write-once recording medium (10), there are provided: a certain defect management area (13) for definitely recording defect management information therein; and a plurality of temporary defect management areas (14A, 14B, and 14C ) to temporarily record defect management information in it. If the recording medium (10) is not finished yet, whenever the defect management information is updated, the updated defect management information is recorded in any one of the plurality of temporary defect management areas. In addition, a state information recording area (15) is recorded on the recording medium (10), and state information for representing the following temporary defect management area is recorded in the state information recording area (15). The defect management information recorded last is recorded. By referring to the status information, the defect management information recorded at the end can be quickly specified.

A method for determining volume coherency is disclosed herein. Upon completing a first write job to a volume partition, the method makes a copy of a volume change reference (VCR) value associated with the volume. The VCR value is configured to change in a non-repeating manner each time content on the volume is modified. Prior to initiating a second write job to the volume partition, the method retrieves the copy and compares the copy to the VCR value. If the copy matches the VCR value, the method determines that a logical object on the partition was not modified between the first and second write jobs. If the copy does not match the VCR value, the method determines that the logical object on the partition was modified between the first and second write jobs. A corresponding system and computer program product are also disclosed herein.

The invention discloses a loss balancing method and device for a nonvolatile memory and a medium. When a small amount of data are written in a physical logic block at a high frequency, a plurality of logic nodes are used for writing from a first byte to a last byte of the physical logic block until the physical logic block is full, and an erasing operation does not need to be carried out every time the data is written. The erasing frequency can be greatly reduced, and the write data can uniformly cover the whole nonvolatile memory, so that the purpose of realizing loss balance in the nonvolatile memory is achieved, and the nonvolatile memory has the advantages of low cost and high efficiency.

The invention discloses a method for simulating power failure of a memory in an FPGA (Field Programmable Gate Array). The method comprises the following steps: 1) selecting an information memory in the FPGA to store information of the power failure memory; 2) when the power-down memory is in a power-down state, sending a power-down signal to reset the information memory to the power-down state; 3)when the power-down memory is in write operation, updating address state information in the information memory; and 4) when the address state information in the information memory is 1, reading datawritten last time, otherwise, reading random data or 0. According to the method for simulating the power failure of the memory in the FPGA, rich memory resources on the FPGA are used for replacing information storage of a register, so that resources are saved, and the requirement of a time sequence is better met; the randomized operation is carried out at the data reading end, so that the power failure behavior can be simulated more truly.