35 results about "Write-once" patented technology

The invention provides a processor memory access optimization implementation method and system with multi-channel concurrent instructions, and relates to the technical field of processor integrated circuits, and the method comprises the steps: obtaining a Load instruction and a Store instruction to be executed; distributing a plurality of memory access instructions to each memory access channel which is independently processed in parallel, wherein each memory access channel comprises a Load memory access channel and a Store memory access channel; an independent Load queue and an independent RAW check queue are arranged in the Load memory access channel, and an independent Store queue, an independent STD queue and an independent Store Buffer queue are arranged in the Store memory access channel; the Load instruction is sequentially subjected to an address generation stage, a TLB parallel query stage, an L1Cache access stage, a RAW check and data forward push stage and a data write-back stage in the Load memory access channel; according to the method, address and data separation processing is carried out on a Store instruction, an address part enters a Store queue, a data part enters an STD queue, then merging is carried out, multiple Store operations on the same Cache Line are merged into one-time writing, the merged data are written into a Store Buffer queue, and then the Store Buffer queue submits and caches in a unified mode.

The invention particularly relates to a distributed time series data cross-node atomic writing and transaction management method. According to the distributed time series data cross-node atomic writing and transaction management method, a coordination node receives a time series writing request, generates a unique TID and issues the unique TID; the storage node writes the data into a pre-write log WAL, marks the data as pending, and establishes mapping between the TID and log entries; the cooperative node sends a pre-submission instruction, and the node responds after being ready; and if verification is passed, broadcasting submission is carried out, a formal storage update version is written, otherwise, rollback is carried out, operation is cancelled according to WAL, and finally associated logs and states are cleared. According to the distributed time series data cross-node atomic write-in and transaction management method, end-to-end atomicity, consistency, low delay and rapid recovery of cross-node time series data write-in are achieved, a write-in path only needs one-time WAL write-in, synchronous blocking is avoided, and the concurrent throughput performance is remarkably improved; and the scheme does not invade an upper-layer application interface, and can be reused in any distributed storage system supporting the WAL.

The embodiment of the invention provides a memory system, an operation method thereof and electronic equipment. The memory system includes: a nonvolatile memory device including a plurality of pages; the preset number of pages form a storage group; the memory controller is coupled with the nonvolatile memory device and is configured to determine a reading voltage of the to-be-read data according to a first duration of a target storage group where the to-be-read data is located in a process of performing a reading operation on the nonvolatile memory device; the first duration is the time difference between the moment when the last write-in is completed in the target storage group and the reading operation starting moment.

The invention relates to the field of computer storage systems, in particular to a transparent compression and intelligent caching method of an SSD storage system. The method comprises the following steps of: compressing and storing one or more write-in requests of a logic page: caching one or more continuous write-in requests of the logic page by utilizing an aligned cache slot position corresponding to the logic page in a DRAM (Dynamic Random Access Memory) cache region, the aligned cache slot performs the following operations when caching the write-in request: monitoring a bitmap and a state identifier of the aligned cache slot, when the bitmap of the aligned cache slot displays that data are written into all the sub-data blocks or the difference between the first write-in timestamp or the latest write-in timestamp in the state identifier and the current time exceeds an overtime threshold, triggering aggregation submission of the aligned cache slot; the write-in data cached in the aligned cache slots are compressed, the compression operation of any aligned cache slot is triggered by the corresponding aggregation submission, and the compressed data are written into the SLC cache region.

Disclosed is a memory device which includes a plurality of memory cells, word lines electrically connected to rows of the plurality of memory cells, and bit lines and source lines electrically connected with columns of the plurality of memory cells. The plurality of memory cells include main memory cells of a main cell area that are configured to support a read operation and a write operation, and one time program cells of a one time program (OTP) cell area that are configured to support the write operation once and a one time program reference cell for the read operation of the one time program cells. Each of the main memory cells is electrically connected to a respective word line, and each of the one time program cells is electrically connected to at least two respective word lines of the word lines.

The application discloses a kind of hardware supplement method, system and circuit of space data processing and knowledge management system, belong to spaceborne data processing technical field, for solving existing spaceborne data processing relies on central processing unit and software architecture, it is easy to be affected by space single particle effect, space radiation interference and appear operation exception, real-time and reliability insufficient problem.The core method of the application includes: reading cache knowledge according to time decay calculation current confidence;Data packet hop count or survival time is directly discarded when exceeding limit;After inter-satellite link interruption recovers, master artificial intelligence node is elected according to preset rule and conflict is judged;When cache is written, it is accumulated to the minimum writing unit after being written once, and wear leveling is triggered according to the number of erasing and writing.The whole process of the application is automatically executed by pure hardware circuit, without central processing unit, without instruction execution, without software code running, with the characteristics of anti-radiation, high real-time, high reliability, can be adapted to space on-orbit environment.

A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

In some implementations, a controller may detect a power loss event on a non-volatile memory device. The controller may perform, based on detecting the power loss event, a first write operation to write data to a first portion of a block of the non-volatile memory device. Prior to the first write operation, the data may be stored in a memory of a controller of the non-volatile memory device. After the first write operation, the first portion of the block may include programmed wordlines. After the first write operation, a second portion of the block may include unprogrammed wordlines. The controller may perform a second write operation to write padding data to an unprogrammed wordline of the unprogrammed wordlines that is adjacent to a last programmed wordline of the programmed wordlines.

The application relates to the technical field of data storage, and discloses a flash memory detection method and a flash memory detection system. The flash memory detection method comprises the following steps: selecting a to-be-tested block from a to-be-tested Die, and establishing a bad block table; executing an erase command on the to-be-tested block in units of blocks, and updating the mark of a block with an erase error in the bad block table to a first mark; executing a write-read operation on the to-be-tested block passing the erase test, and determining the first bit flip number of a current page; repeatedly reading the original data of the current page, determining the second bit flip number according to the reading result, if the first bit flip number of the page exceeds a first preset threshold; and updating the mark of the block where the current page is located in the bad block table to a second mark, if the second bit flip number exceeds a second preset threshold. The technical scheme provided by the application further excavates the blocks which are unstable in performance and are prone to errors in practice although the blocks pass the erase read-write once, can more accurately screen the bad blocks, and makes the flash memory detection more thorough.

A platform security processor is activated and reads a set of write-once storage bits to obtain a minimum security patch level (SPL). The security processor then verifies that a table SPL of a firmware security table is greater than or equal to the minimum SPL. The firmware security table includes a plurality of firmware identifiers for firmware code modules, and a plurality of check SPL values ​​are each associated with a corresponding one of the firmware identifiers. The security processor verifies the SPL values ​​in the plurality of firmware code modules by, for each firmware code module, accessing the module to obtain its firmware SPL value and checking whether the corresponding firmware SPL value is equal to or greater than the corresponding check SPL value in the firmware security table.

In some implementations, a controller may detect a power loss event on a non-volatile memory device. The controller may perform, based on detecting the power loss event, a first write operation to write data to a first portion of a block of the non-volatile memory device. Prior to the first write operation, the data may be stored in a memory of a controller of the non-volatile memory device. After the first write operation, the first portion of the block may include programmed wordlines. After the first write operation, a second portion of the block may include unprogrammed wordlines. The controller may perform a second write operation to write padding data to an unprogrammed wordline of the unprogrammed wordlines that is adjacent to a last programmed wordline of the programmed wordlines.

In a data processing apparatus 11, a buffer memory BM including a first buffer memory RM1, a second buffer memory MM1, a third buffer memory RM2, and a fourth buffer memory MM2, stores therein data that is formed of a plurality of bits, and a CPU 11A reads the data from the buffer memory BM, performs bit inversion on the plurality of bits to generate bit inverted data in which a value of each of the bits is inverted, writes the bit inverted data in the buffer memory BM at a first time, reads the data from the buffer memory BM at a second time that is later than the first time, compares first data that is bit inverted data that is written in the buffer memory BM at the first time and second data that is bit inverted data that is read from the buffer memory BM at the second time, and determines presence of a failure in the buffer memory BM.

Memory blocks often consume many switch box resources. For example, an 8-bit memory using 8-bit addressing uses at least eight address lines, eight data lines, a write-enable line, and a read-enable line. Using an auto address mode, the address and data are multiplexed on the same lines. The initial address and a stride are provided before the writing process begins. Between writes, the address is incremented by the stride. Thus, the memory block is able to determine the address for the next write based on the starting address and the stride, and does not need to receive the new address on the address lines. The auto address mode may be implemented by including a logic block within the memory block. The logic block may be programmed for purposes other than an auto address mode.

This disclosure relates to the field of electronic digital data processing technology, and in particular to a cross-platform performance-portable programming method and apparatus based on unified optimization primitives. The method includes: receiving unified source code, which contains computational logic code and hardware optimization primitives, wherein the hardware optimization primitives are attached to the computational logic code in the form of independent declarative primitive chains, and the hardware optimization primitives are used to describe optimization strategies adapted to different hardware architectures; parsing the unified source code to construct an extended AST, which contains semantic information of the computational logic code and optimization instructions of the hardware optimization primitives; and generating target source code adapted to the target hardware platform based on the extended AST. This disclosure achieves the goal of "write once, execute efficiently on multiple platforms" by decoupling the computational logic code from the hardware optimization primitives, not only realizing cross-platform performance portability but also significantly reducing the complexity and development cost of manual optimization for heterogeneous hardware.

A data storage device comprises a disk array including a plurality of disks; and a redundant array of independent disks (RAID) controller configured to manage the disk array according to a RAID mode, wherein each of the plurality of disks includes: a nonvolatile memory device having a plurality of zones of which supports a sequential write operation; and a random write buffer associated to one of the plurality of zones, the random write buffer having a start address that is indicated by a write pointer, the write pointer indicating a location where a next write operation is to be performed.

The invention relates to the technical field of storage, and provides a data writing method, a storage controller and a storage device, the data writing method is applied to the storage device comprising the storage controller and a nonvolatile storage medium, and the method comprises the steps that the storage controller receives a termination command issued by a host and used for terminating a write command, the write command is used for temporarily storing data issued by the host to a preset memory area of the storage controller; if the data volume of the written data in the preset memory area is smaller than the size of the preset programming unit, the storage controller determines an offset address of the data written by the host next time in the preset memory area; and the storage controller records the offset address, so that the storage controller temporarily stores the data written by the host next time to the preset memory area according to the offset address. According to the method, the situation that when the data size of the host data is smaller than the size of the minimum programming unit, the DMA gets stuck, the NAND programming command needs to be cancelled, and the NAND writing command needs to be issued again, so that the performance is reduced is avoided, and the storage efficiency is improved.

A B+-tree-based data management method includes writing, when a first write operation on a node data of a B+ tree is detected, the node data to a base page of a disk, wherein the base page contains a pointer field configured to indicate an associated delta page; creating a first delta record in a delta page based on the base page, when a first write operation on a target entry in the base page is detected; creating a second delta record in the delta page when a second write operation on the target entry is detected, the second delta record is used to record second data corresponding to the second write operation. Accordingly, a waste of disk space may be reduced, and complexity of read-write operations may be lowered.

The application discloses a kind of storage methods of dynamic reconfiguration storage data, comprising the following steps: receiving data dynamic change timer to time message, read object ABC, initiate the request of object ABC re-write;After receiving the write request of object ABC, according to current time and object name hash modulo calculation obtains the storage algorithm index in storage algorithm table, if algorithm index is consistent with the algorithm index of last write, then re-calculate and obtain;Object ABC is sliced according to storage algorithm and is handled;According to strip, data block is encoded to obtain encoding block, and these encoding blocks are sent to different logical storage units;Wait until encoding block is successfully landed, record log, log format;T3=rand (X), restart timer, duration is T3.The storage method of dynamic reconfiguration storage data provided by the application has the advantages that the reliability of storage system is strong, the security of storage data is high.

The present application relates to big data processing and edge computing technical field, specifically to information big data management system based on edge computing, including mutation detection module, skip list management module and decision execution module, the mutation detection module carries out "noise-silence" dual-state detection to big data stream in edge node, only intercepts mutation micro-slice at state conversion and calculates 128 bit SimHash mutation fingerprint; the skip list management module weaves the "mutation fingerprint-physical block" bidirectional skip list with reversible fuse mark on local PCM, realizes the index of mutation fingerprint to physical block address; the decision execution module takes the skip list root handle as the entrance, drives the "write once" type edge inference machine to generate the immutable decision frame, writes back the data source terminal through the low delay channel and updates the fuse state, so as to complete the closed loop processing of cold mutation data.

The invention discloses a GPU (Graphics Processing Unit) equipment registration method and device, equipment and a medium, which are used for reducing code redundancy during GPU equipment registration. The method comprises the following steps: pre-deploying a default state which is suitable for whether general attribute nodes of most GPU equipment are exposed or not and each preset default function; according to the method, the default state of whether the universal attribute node is exposed or not or the preset default function is correspondingly replaced with the inconsistent actual state and actual use function of each attribute of the GPU equipment, so that the repeated writing of basic codes is avoided, the universal logic codes only need to be written once, and when the model of the GPU equipment is newly added, the writing efficiency is greatly improved. According to the method, only the model look-up table and the corresponding actual configuration need to be expanded, the whole drive registration process does not need to be rewritten, the problems of code redundancy and poor compatibility caused by writing an independent drive registration code for each GPU device in the prior art are solved, and the reusability and maintainability of the code are improved.

The embodiment of the invention provides a snapshot generation method and computing equipment, relates to the technical field of servers, and is used for reducing the time consumption of generating snapshots by multiple disks and improving the overall operation efficiency. The method comprises the following steps: in response to a received snapshot generation instruction, pausing write-in operation on a plurality of disks; performing snapshot operation on each disk in sequence to obtain snapshots corresponding to the plurality of disks; in the process of executing the snapshot operation on the plurality of disks, if the estimated snapshot time is less than or equal to the minimum predicted silence time, recovering the write-in operation on the plurality of disks; wherein the pre-estimated snapshot time is pre-estimated snapshot time required by an unexecuted disk which does not execute the snapshot operation in the plurality of disks; the minimum predicted silence time is the minimum predicted silence time in the predicted silence time corresponding to each unexecuted disk; the predicted silence time is the time from the predicted disk to the next write operation under the condition that the snapshot generation instruction is not received.

Methods, systems, and devices for systems and techniques for error testing are described. As part of a first write operation, a memory system may write data and associated error correction code (ECC) bits to a memory array. In accordance with a first portion of a test, the memory system may store a copy of the ECC bits to a register of the memory system. As part of a second write operation, the memory system may write an error vector to the memory array. In accordance with a second portion of the test, the memory system may store the previously-stored ECC bits from the register to the memory array. The memory system may subsequently access the error vector and the ECC bits from the memory array to support verification of error correction and detection performance of the memory system.

Writable memory sections of a PCM are coupled to a non-volatile memory storing information indicating whether a latest write operation to the writable memory section used a first or second set of current pulses (the second set using lower current values than the first set). In response to a command to perform a write operation on the writable memory section using pulses of the second set, and where the stored information indicates the latest write operation used pulses of the first set, a transition is made from the first set to the second set, a blanking current pulse is applied to cells of the writable memory section in the reset state; a write operation on the writable memory section is performed using the second set, and the non-volatile memory section is updated to indicate that the latest write operation was performed using the second set.

Memory blocks often consume many switch box resources. For example, an 8- bit memory using 8-bit addressing uses at least eight address lines, eight data lines, a write-enable line, and a read-enable line. Using an auto address mode, the address and data are multiplexed on the same lines. The initial address and a stride are provided before the writing process begins. Between writes, the address is incremented by the stride. Thus, the memory block is able to determine the address for the next write based on the starting address and the stride, and does not need to receive the new address on the address lines. The auto address mode may be implemented by including a logic block within the memory block. The logic block may be programmed for purposes other than an auto address mode.

The application discloses a method and a storage device for updating a P2L mapping table. The method comprises the following steps: receiving a current write command issued by a host and obtaining a current P2L mapping table of a current data block; determining a last write address in the current P2L mapping table; searching for a first overlapping address same as a current logical address of the current write command by traversing historical logical addresses in the current P2L mapping table from a first old mapping unit to a last mapping unit in the current P2L mapping table; marking an old mapping unit corresponding to the first overlapping address in the current P2L mapping table as invalid; and writing the current logical address into a new mapping unit of the current P2L mapping table. The application can effectively improve the sequential write performance of the storage device.

A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device initializes a block family associated with the memory device and a timer associated with the block family. In response to the timer reaching a soft closure value, the processing device performs a soft closure of the block family and a hard closure of the block family in response to a first of the timer reaching a hard closure value or the block family satisfying a hard closure criteria. The processing device detects a first write amplification of a previously closed block family that employed the hard closure value and increases the hard closure value by an amount of time calculated to reduce a second write amplification, of the block family, to below a threshold write amplification.

To provide a memory system that suppresses performance degradation caused by training operations. [Solution] The memory system controller is capable of performing either a first write operation or a second write operation. The first write operation includes a data-in operation and a program operation. The data-in operation is the operation of transferring data to the memory device by a data signal and a data strobe signal, and storing the data captured by the latch circuit in the memory device in a buffer circuit. In the second write operation, the controller performs the data-in operation, acquires the data captured by the latch circuit by the data-in operation, and obtains the number of error bits contained in the acquired data. Furthermore, the controller determines whether to perform a training operation or skip it depending on the number of error bits.