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Metadata management method and device

A management method and metadata technology, applied in digital data processing, data processing input/output process, instruments, etc., can solve problems such as large read amplification, waste of cache resources, and increased processor burden

Active Publication Date: 2020-01-24
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] This metadata management method has a large read amplification (that is, the amount of data read from the main memory is greater than the amount of data written in the write request), which increases the burden on the processor and wastes cache resources.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0053] like Figure 4 As shown, it is a schematic flowchart of a metadata management method provided in the embodiment of the present application. Exemplary, this embodiment can be applied to figure 1 , figure 2 The system architecture shown. Figure 4 The illustrated method may include the steps of:

[0054] S101: The cache controller receives a write request sent by the processor. The write request includes write request data and a logical address range of the write request data. Wherein, the logical address range of the write request data is the logical address range of the storage space used to store the write request data in the main memory.

[0055] When the cache controller is a write cache controller, in a write request scenario, after receiving the write request sent by the host, the processor sends the write request to the write cache controller.

[0056] When the cache controller is a read cache controller, and in the read request scenario, neither the read c...

Embodiment 2

[0090] Assume that the target metadata storage unit stores metadata of M times of writing cache data, wherein each writing of metadata includes a logical address range. M is an integer greater than or equal to 1, then, when the first logical address range includes one or more logical address ranges in the M logical address ranges, after S105 and before S106, the method further includes: deleting the one or Metadata where multiple logical address ranges reside.

[0091] Based on this, in S106, the target metadata is the latest metadata written in the metadata written to the cache for N times, wherein the metadata written in the cache for N times is deleted from the metadata written in the cache for M times The remaining metadata after the metadata corresponding to one or more logical address ranges.

[0092] Exemplarily, it is assumed that the first logical address range is 8KB-30KB, based on the example in Table 2. There are two logical address ranges in the target metadata ...

Embodiment 3

[0102] like Image 6 As shown in , it is a schematic flowchart of another method for managing metadata provided by the embodiment of the present application. This embodiment may be executed after the above-mentioned Embodiment 1 or Embodiment 2 is executed. Exemplary, this embodiment can be applied to figure 1 The system architecture shown. Image 6 The illustrated method may include the steps of:

[0103] S301: The cache controller acquires the quantity M of all metadata in the target metadata storage unit.

[0104] Optionally, when the logical address range in the read request received by the cache controller intersects with any logical address range stored in the target metadata storage unit, the cache controller obtains all metadata in the target metadata storage unit The number M, wherein the preset logical address range corresponding to the target metadata storage unit includes the logical address range in the read request.

[0105] Exemplarily, it is assumed that t...

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PUM

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Abstract

The invention discloses a metadata management method and device, relates to the technical field of data storage, and the metadata management method and device are helpful for reducing read amplification and saving cache resources. The method comprises the steps of receiving a write request, wherein the write request comprises first data and a first logic address range; wherein the first logic address range is an address range of a storage space used for storing the first data in the main memory; determining a first address in a cache according to the write request, and writing the first data into a first data storage unit indicated by the first address; wherein the first address comprises an identifier of the first data storage unit, an initial storage position of the first data in the first data storage unit and the length of the first data; generating metadata of the first data and writing the metadata into a target metadata storage unit; wherein the preset logic address range corresponding to the target metadata storage unit comprises a first logic address range; establishing a sequential relationship between the metadata of the first data and the write-in time of the target metadata; wherein the target metadata is the metadata written into the target metadata storage unit last time.

Description

technical field [0001] The present application relates to the technical field of data storage, and in particular to a metadata management method and device. Background technique [0002] In the storage node, the cache is a high-speed memory between the processor and the main memory, which is mainly used to improve the read and write performance of the system. A cache is used to store a portion of data in main memory. The cache controller is used to manage the data and metadata in the cache. Currently, cache controllers manage data and metadata at the granularity of preset logical address ranges in main memory. Specifically, assuming that each preset logical address range includes consecutive logical addresses of 128KB byte length, for example, 0KB-127KB is a preset logical address range, and 128KB-255KB is another preset logical address range, then, when When the processor receives a write request, and the logical address range of the data to be written included in the wr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06G06F12/02
CPCG06F3/061G06F3/0631G06F3/0652G06F3/0679G06F12/0246
Inventor 谭春华
Owner HUAWEI TECH CO LTD
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