115 results about "Cache controller" patented technology

The invention relates to a final-stage cache design method based on near memory calculation, and belongs to the technical field of near memory calculation. And compared with a near memory processor near a traditional main memory, data access and calculation can be carried out more quickly, and the calculation throughput rate can be improved. According to the near storage calculation, a near storage processor and a last-stage cache storage array are directly designed in an integrated mode, faster memory access is achieved through an internal bus interconnection mode, and the problem of a storage wall between the calculation speed and the memory access speed and the problem of a power consumption wall of data handling are relieved to a certain degree. The last-stage cache controller cooperates with the embedded processor, and can dynamically coordinate between a standard cache function and a calculation mode. Through a synchronization mechanism in a last-stage cache controller, a memory access request from a host CPU and a calculation task executed by an embedded processor in a last-stage cache are transparently balanced, so that efficient near-memory calculation under cache consistency is realized.

A storage device includes a non-volatile memory and a storage controller, wherein the storage controller includes a cache memory storing some of data stored in the non-volatile memory, an interface circuit receiving, from a first external host, a first request including a source address related to the external storage device, a destination address related to the storage device, and cache update information indicating an update method of the cache memory, provide a second request including the source address to the external storage device, and receive, from the external storage device in response to the second request, a response including first data corresponding to the source address, an address translation circuit generating a physical address of a first type based on the destination address, and a cache controller updating a cache area indicated by the physical address of the first type based on the cache update information.

A system includes a host device, a memory expanding device, and a switch connecting the host device and the memory expansion device, wherein the host device includes a cache controller including a prefetch support circuit configured to generate prefetch information, a root complex configured to transmit the prefetch information to the memory expanding device and receive prefetch data from the memory expanding device, and one or more prefetch buffers storing the prefetch data, and the memory expanding device includes a memory device and a memory controller including a prefetch decision circuit configured to read the prefetch data from the memory device based on the prefetch information received from the host device and prefetch the prefetch data to the host device.

The invention provides a code pattern data efficient processing system and method based on real-time compression and intelligent cache. The code pattern data efficient processing system comprises a code pattern processor, a compression module, a multi-level cache structure, a cache controller and a multi-channel interface. And the compression module is connected with the code pattern processor and is used for performing segmented compression processing on the pseudo-random code pattern data generated by the code pattern processor to obtain compressed data. The multi-level cache structure is connected with the compression module, and the cache controller is connected with the multi-level cache structure and the compression module and used for monitoring the compression state of the compression module and the occupation state of the multi-level cache structure in real time, dynamically adjusting a cache allocation strategy and sending a scheduling instruction to the multi-channel interface; and the multi-channel interface is connected with the cache controller and the multi-stage cache structure and is used for reading the compressed data from the multi-stage cache structure according to the scheduling instruction and executing multi-channel load balancing transmission. The problem that in the prior art, compression and caching are difficult to collaboratively optimize is effectively solved.

A system includes a multilevel memory such as a two level memory (2LM), where a first level memory acts as a cache for the second level memory. A memory controller or cache controller can detect a cache miss in the first level memory for a request for data. Instead of automatically performing a swap, the controller can determine whether to perform a swap based on a swap policy assigned to a memory region associated with the address of the requested data.

Cache memory systems employing multiple-level hierarchy cache coherency architecture, and related methods and computer-readable media. A processor-based system includes separate dies that each have a processor and local cache memory logically forming a portion of global cache memory for a system address space. To provide a single point of cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point of cache coherency in the global cache memory. Thus, a cache coherency protocol based on a single point of cache coherency can be implemented. However, the proxy cache controller circuits are also capable of locally servicing memory requests solely within its die, when possible to maintain cache coherency, to provide lower latency memory transactions

The invention provides a synchronous communication device and method based on multiple coprocessors, equipment and a storage medium. The device comprises a main processor which is configured to send a communication instruction to a primary buffer; the cache controller is configured to distribute the communication instruction from the first-level cache to the first second-level cache and the second second-level cache; the first coprocessor is configured to read the communication instruction from the first second-level buffer and configure the communication instruction to the first terminal node; the second coprocessor is configured to read the communication instruction from the second secondary buffer and configure the communication instruction to a second terminal node; and the synchronous triggering module is configured to control the first terminal node and the second terminal node to perform synchronous communication according to the communication instruction to obtain a communication result. Therefore, the first coprocessor and the second coprocessor can simultaneously configure the corresponding terminal nodes, so that the instruction sending time is shortened, and optical fiber bus communication for spaceflight control can be accelerated through the multiple coprocessors.

Methods, apparatus, systems and articles of manufacture to facilitate write miss caching in cache system are disclosed. An example apparatus includes a first cache storage; a second cache storage, wherein the second cache storage includes a first portion operable to store a first set of data evicted from the first cache storage and a second portion; a cache controller coupled to the first cache storage and the second cache storage and operable to: receive a write operation; determine that the write operation produces a miss in the first cache storage; and in response to the miss in the first cache storage, provide write miss information associated with the write operation to the second cache storage for storing in the second portion.

The invention discloses a cache controller for multi-control storage, a control method, a system and a server, is applied to the technical field of storage hardware, and aims to solve the problems of wiring complexity, cost reduction, cache utilization rate improvement and write-in delay of multi-control storage in related technologies. The cache controller comprises a switch supporting multi-host information sharing, a cache module connected with the switch and a central processing unit, the switch is provided with at least two first external bus interfaces used for being connected with storage controller nodes, and the central processing unit is connected with the cache module and the central processing unit. The division module is used for dividing a corresponding cache region for the storage controller node in the cache module under the condition that the switch detects that the storage controller node is accessed to the switch; the switch is used for acquiring the cache data sent by the storage controller node and writing the cache data into a cache region corresponding to the storage controller node in the cache module; the wiring complexity, the wiring cost and the writing delay can be reduced, and the cache utilization rate is improved.

Cache memory systems employing multiple-level hierarchy cache coherency architecture, and related methods and computer-readable media. A processor-based system includes separate dies that each have a processor and local cache memory logically forming a portion of global cache memory for a system address space. To provide a single point of cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point of cache coherency in the global cache memory. Thus, a cache coherency protocol based on a single point of cache coherency can be implemented. However, the proxy cache controller circuits are also capable of locally servicing memory requests solely within its die, when possible to maintain cache coherency, to provide lower latency memory transactions

An example system may include a first physical memory integrated within a first die, and a second physical memory integrated within a second die. The first die and second die are coupled in a stack arrangement. The system may also include a cache controller configured to implement a plurality of cache ways of a set associative cache. The plurality of cache ways include a first cache way defined within the first physical memory and a second cache way defined within the second physical memory.

The invention belongs to the technical field of chip testing, and discloses a testing device and method for an RISC-V chip instruction cache, and the device comprises a CPU core, a cache controller, a user-defined instruction execution module, and an instruction cache. The CPU core is used for receiving a test starting address and a test ending address; sending a clearing instruction to the instruction buffer; and executing a test step: generating an instruction reading address according to the test starting address, sending the instruction reading address to the cache controller until a test ending address, receiving a test instruction of the cache controller, judging whether the test instruction is a self-defined instruction, and if so, sending the test instruction to a self-defined instruction execution module to obtain an instruction execution result; and executing the test step again, and obtaining an instruction cache test result according to an obtained instruction execution result. The RISC-V chip instruction buffer test method and the RISC-V chip instruction buffer test device can realize comprehensive test of the RISC-V chip instruction buffer under the condition of avoiding increasing a large amount of chip cost area.

Provided is a semiconductor integrated circuit module including DRAM caches in a stacked structure, capable of preventing an increase in tag memory capacity on a processor side, reducing hit latency, and improving hit rate. A computing system (1000) is provided with a CPU (100), a main memory (300), and a cache DRAM circuit (400) stacked on the CPU (100). The cache DRAM circuit (400) operates as a group-connected cache memory. The address space of the main memory (300) is divided into a plurality of first sections, the address space of the cache DRAM circuit (400) is divided into a plurality of second sections in one-to-one correspondence with the first sections, and each second section comprises a plurality of paths. The cache controller (111) uniformly accesses rows in a plurality of paths corresponding to the address of the accessed main memory (300).

An example system may include a first physical memory integrated within a first die, and a second physical memory integrated within a second die. The first die and second die are coupled in a stack arrangement. The system may also include a cache controller configured to implement a plurality of cache ways of a set associative cache. The plurality of cache ways include a first cache way defined within the first physical memory and a second cache way defined within the second physical memory.

Cache memory systems employing a multi-level hierarchy cache coherency architecture, and related methods and computer readable media. A processor-based system includes multiple independent dies, each die having a processor and a local cache memory that logically forms part of a global cache memory in a system address space. To provide single point cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point cache coherency in the global cache memory. Thus, a single point cache coherency protocol can be implemented. However, the proxy cache controller circuits can also be able to locally service memory requests within their own die only, to provide lower latency memory transactions, while still being able to maintain cache coherency.

Methods and apparatus to reduce register access latency in split-die SoC designs. The method is implemented on a platform including a legacy socket and one or more non-legacy (NL) sockets comprising split-die System-on-Chips (SoC)s including multiple dielets interconnected with a plurality of Embedded Multi-Die Interconnect Bridges (EMIBs). The dielets include core dielets having cores, cache controllers and memory controllers. The method provides an affinity between a control and status registers (CSRs) memory range for the NL sockets such that CSRs in the memory controllers for multiple core dielets are programmed using transactions forwarded along core-to-cache controller datapaths that avoid crossing EMIBs. In one aspect, a transient map of address ranges is created that includes a respective Sub-NUMA Cluster (SNC) range allocated for the NL sockets, with a range of CSR addresses for accessing CSRs in the memory controllers for the NL sockets being stored in the respective SNC ranges.

If sufficient memory resources are allowed access, components on an IC chip can operate faster or provide higher performance relative to power consumption. However, if each component is provided with its own memory, the chip becomes expensive. In the described implementation, memory is shared among two or more components (110, 114, 116). For example, a processing component (116) may include computing circuitry (206) and memory (106) coupled thereto. A multi-component cache controller (114) is coupled to memory (106). Logic circuitry (202) is coupled to the cache controller (114) and memory (106). The logic circuitry (202) selectively divides memory (106) into multiple memory partitions (108). A first memory partition (108-1) may be allocated to computing circuitry (206) and provide storage for computing circuitry (206). A second memory partition (108-2) may be allocated to the cache controller (114) and provide storage for multiple components (110). The relative capacity of memory partitions is adjustable to accommodate fluctuating demand without having to dedicate separate memory to a component.

The embodiment of the invention discloses a GPU chip, a ray tracing method, a graphics card and computer equipment, and relates to the field of GPU graphic rendering. The GPU chip comprises a GPU core, an on-chip cache and a cache controller, the on-chip cache is used for storing ray tracing data required by ray tracing calculation; the GPU core is used for sending a data reading instruction to the cache controller; the cache controller is used for reading the ray tracing data from the on-chip cache based on the data reading instruction and sending the ray tracing data to the GPU core; and the GPU core is used for executing ray tracing calculation based on the ray tracing data. By adopting the GPU chip provided by the invention, a large amount of occupation of a GPU core in ray tracing calculation can be avoided, and a relatively high data access speed is achieved.

The present disclosure provides a cache architecture comprising a cache memory having a tag storage and a data storage, a miss status holding register (MSHR) configured to track memory requests where each memory request includes a NoFill field, a safe history buffer (SHB) configured to store safe memory addresses and generate cache line fetch requests based on the stored safe memory addresses, and a cache controller configured to prevent cache fills for memory requests having the NoFill field set, send data to a processor without filling the cache memory when the NoFill field is set, and fill the cache memory with cache lines retrieved by the cache line fetch requests generated by the SHB. The cache architecture provides security against cache timing attacks by decorrelating cache fills from actual memory requests while maintaining performance through the safe history buffer mechanism.

This application relates to methods and apparatus for facilitating write miss caches in a caching system. Example methods, apparatuses, systems, and articles of art are provided for facilitating write miss caches in a caching system. One example apparatus (110) includes: a first cache storage area (214); a second cache storage area (218), wherein the second cache storage area (218) includes a first portion and a second portion for storing a first set of data evicted from the first cache storage area (214); a cache controller (222) coupled to the first cache storage area (214) and the second cache storage area (218), and configured to: receive a write operation; determine that the write operation has resulted in a miss in the first cache storage area (214); and, in response to the miss in the first cache storage area (214), provide write miss information associated with the write operation to the second cache storage area (218) for storage in the second portion.

A microprocessor system (100) comprising: a cache (104-110) comprising: a plurality of cache lines, each characterized by a replacement priority level selected from a plurality of replacement priority levels, wherein the replacement priority level indicates a probability of replacing a cache line causing a rollback of a transaction, each cache line having priority bits (124) indicative of the replacement priority level identifying the cache line, wherein replacing the cache line having a higher replacement priority level has a lower probability of triggering a rollback of a transaction than replacing a cache line having a lower replacement priority level; and a cache controller (128) configured to (1) select a least recently used cache line from the plurality of cache lines having a highest available replacement priority level, and (2) replace the least recently used cache line having the highest available replacement priority level according to a replacement scheme.

Examples described herein relate to a cache fabric that includes a set of routers of a first tier and a plurality of cache controller clusters of a second tier. A router of the set of routers is accessible via an interface to receive a memory access request from a processor and select from a set of cache controllers based on a cluster identifier and a memory address, and provide the memory access request to the selected set of cache controllers. The selected set of cache controllers may receive memory access requests and serve memory access requests from the cache device, or forward memory access requests to a second cache controller or second cache device associated with the cache device.

Embodiments herein describe circuitry and techniques to implement shunt current control of an on-chip voltage regulator of a memory storage system using hardware components and computer software tools. Disclosed embodiments provide an on-chip voltage regulator with enhanced performance, reducing power requirements, and minimizing noise and voltage fluctuations of the regulator output, based on a cache activity signal produced by a cache controller.

The present invention relates to a cache device for a graphics processing system. A graphics processing system is disclosed, the graphics processing system having a cache system (24) arranged between a memory (23) and a graphics processor (20), the cache system comprising a first cache (53) for transferring data to and from the graphics processor (20) and a second cache (54) arranged and configured to transfer data between the first cache (53) and the memory (23). When data is to be written from the first cache (53) to the memory (23), a cache controller (55) determines the data type of the data and, depending on the data type, causes the data to be written to the second cache (54) without being written to the memory (23), or causes the data to be written to the memory (23) without being stored in the second cache (54). In an embodiment, the second cache (54) is allocated for write-only operation.

The invention provides a data reading processing method, a multi-level cache processor architecture, a cache controller and equipment, the method is applied to the multi-level cache processor architecture, and the multi-level cache processor architecture comprises special caches corresponding to processor cores and shared caches shared by the processor cores. The method comprises the following steps: under the condition that a write request hits shared-state first data in a special cache, the special cache sends an exclusive-state read request to a shared cache; and before the special cache receives the first data in the exclusive state returned by the shared cache, if the special cache receives the second data returned by the shared cache and confirms that the first data needs to be evicted when the second data is filled into the special cache, the special cache cancels the operation of sending the eviction request to the shared cache. According to the method, the problem of inconsistent cache data of the processor can be avoided.

The invention is suitable for the technical field of artificial intelligence, and relates to a model reasoning method and a model reasoning system. The method comprises the following steps: acquiring interlayer structure characteristics of a target model needing model reasoning and a first initial storage address of a first layer weight parameter of the target model in a persistent storage space through an address predictor; according to the first initial storage address and the interlayer structure characteristics, calculating a storage address offset corresponding to the weight parameter of each layer; according to the first initial storage address and the storage address offset corresponding to each layer of weight parameter, determining a first target storage address of each layer of weight parameter in the persistent storage space, and sending the first target storage address to a cache controller, each first target storage address is used for the cache controller to pre-fetch each layer of weight parameter from the persistent storage space for the calculation unit to use. The overall performance of model reasoning can be improved, and the method is particularly suitable for efficient deployment of a large-scale deep learning model on edge equipment or terminal equipment.

The invention provides a data processing method and device, electronic equipment and a storage medium, and the method comprises the steps: determining a target cache line matched with address information from a plurality of cached cache lines according to the address information in a received data processing request; determining a target sector matched with the address information from a plurality of sectors of the target cache line under the condition that the target cache line is determined to be in the effective state; and performing data processing in the target sector according to the sector state of the target sector. According to the mode, the data overhead for transmitting the whole cache line is avoided, so that the bandwidth utilization rate and the transmission efficiency are improved, the system power consumption is reduced, and the system performance is improved.

A cache controller of a cache assigns a dirty tracking bit for each dirty byte of a cache line. Once a predetermined interval has elapsed without any accesses to the cache line or to a cache set that includes the cache line, the cache controller compresses contiguous dirty tracking bits for each portion of the cache line. Compressing the dirty tracking bits for contiguous dirty portions of the cache line allows the cache to store more dirty data using fewer dirty tracking bits, reducing area cost and bandwidth among levels of a memory hierarchy.

Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device includes a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value based on the plurality of content costs. The cache controller circuit is further configured to evict the target cached data value from the cache memory device.

Providing content aware cache replacement and insertion policies in a processor-based device is disclosed. In some aspects, a processor-based device includes a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device based on a plurality of bit values for each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.