11 results about "Cache controller" patented technology

If sufficient memory resources are allowed access, components on an IC chip can operate faster or provide higher performance relative to power consumption. However, if each component is provided with its own memory, the chip becomes expensive. In the described implementation, memory is shared among two or more components (110, 114, 116). For example, a processing component (116) may include computing circuitry (206) and memory (106) coupled thereto. A multi-component cache controller (114) is coupled to memory (106). Logic circuitry (202) is coupled to the cache controller (114) and memory (106). The logic circuitry (202) selectively divides memory (106) into multiple memory partitions (108). A first memory partition (108-1) may be allocated to computing circuitry (206) and provide storage for computing circuitry (206). A second memory partition (108-2) may be allocated to the cache controller (114) and provide storage for multiple components (110). The relative capacity of memory partitions is adjustable to accommodate fluctuating demand without having to dedicate separate memory to a component.

This application relates to methods and apparatus for facilitating write miss caches in a caching system. Example methods, apparatuses, systems, and articles of art are provided for facilitating write miss caches in a caching system. One example apparatus (110) includes: a first cache storage area (214); a second cache storage area (218), wherein the second cache storage area (218) includes a first portion and a second portion for storing a first set of data evicted from the first cache storage area (214); a cache controller (222) coupled to the first cache storage area (214) and the second cache storage area (218), and configured to: receive a write operation; determine that the write operation has resulted in a miss in the first cache storage area (214); and, in response to the miss in the first cache storage area (214), provide write miss information associated with the write operation to the second cache storage area (218) for storage in the second portion.

Examples include techniques to implement a data-aware cache replacement policy. The techniques include indicating, to a cache controller, that data to be included in a cache line is likely to be reused. The indication of likely-to-be-reused data is to be used by the cache controller to determine when the data is to be evicted or replaced in the cache.

This invention relates to the field of system-on-chip (SoC) testing technology, specifically to a dynamic verification method for SoC chips based on a memory consistency model. The method includes collecting memory access data entering the cache controller and generating feature vectors; classifying the feature vectors using a decision tree to filter out risky memory data; expanding test cases based on the risky memory data to obtain test cases; testing the SoC chip based on the test cases; and iterating the decision tree model based on the test results. Addressing the problem that existing SoC verification test cases are ineffective against dynamically changing memory read / write patterns, this invention introduces a hardware monitoring unit into the cache controller to directly capture memory read / write data appearing in the cache. A decision tree model is then used to filter out risky memory data that may cause failures. Based on this, test cases are constructed and expanded to facilitate testing of the SoC's memory read / write mechanism, and the decision tree model is improved to obtain more test cases.

The application provides a data reading processing method, a multi-level cache processor architecture, a cache controller and equipment. The method is applied to the multi-level cache processor architecture. A transmission queue and a delivery queue are arranged in a first cache of the architecture. The transmission queue is used for storing return data corresponding to a first read request that is not hit in the first cache, and a return data packet is generated based on the return data and backfill requirements. The delivery queue is used for storing data requested by a second read request that is not hit in the first cache, and a return data packet is generated based on the requested data. The method comprises the following steps: in the case that the first cache receives return data corresponding to a target read request returned by a second cache, determining the request type of the target read request; in the case that it is determined that the target read request is a specific type of read request, storing target data requested by the target read request and the target read request into the delivery queue. The above method can improve the cache data reading efficiency and reduce the data reading delay.

The application discloses a kind of layered memory of CXL-SSD facing storage method and system, belong to CXL and flash storage cross technical field.The method includes: when host last stage cache is off target and target address is located in CXL device, cache controller queries sparse remapping table and routes access request;High-fidelity memory access profiler real-time capture page heat and intra-page sparsity;Dynamic slicing and asymmetric migration module identifies active slice and migrates to fast layer according to preset interval, updates mapping relationship;Write-sensitive degradation and eviction module filters sacrifice page through write-aware strategy, executes multi-stage degradation and eviction operation.The application solves the problem of resource occupation by cold data and accelerated device wear and tear in traditional solutions through fine-grained memory access perception, slice-level migration and write-sensitive management, achieving the coordinated optimization of system performance, space efficiency and device life, and is suitable for memory expansion scenarios in data-intensive applications such as artificial intelligence and high-performance computing.

In accordance with the described techniques, a processor includes a cache controller and a cache system having a cache level with multiple memory architectures exhibiting different memory access latency and memory capacity characteristics. The cache controller is configured to receive a memory access request to a memory address, and perform lookups for a tag of the memory address in the multiple memory architectures in parallel.

This application discloses a processor chip and a processor chip data prefetching method, relating to the field of integrated circuit technology, and is invented to improve the prefetching efficiency of data from memory to cache. The processor chip includes: a prefetch controller, used to determine whether there is an active memory row in the memory at the current time; if an active memory row exists, it determines whether the memory is currently occupied by an access request; if the memory is not currently occupied by an access request, it sends a prefetch request to the memory controller; the memory controller is used to obtain prefetched data from the active memory row according to the prefetch request and send the prefetched data to the cache controller; and the cache controller is used to receive the prefetched data and store it in the cache. This application is applicable to prefetching memory data.

This application relates to a domain-specific language compiler for cache coherence protocols, belonging to the field of computer architecture modeling and simulation technology. The compiler takes a high-level abstract specification of the cache coherence protocol as input and automatically converts it into cache controller and / or directory controller code executable by a periodic precision simulator. Through systematic mapping and translation of the protocol's finite state machine, event-triggered mechanism, concurrent transaction management, and asynchronous hardware interaction, it achieves event-driven, non-blocking control logic generation. Simultaneously, the compiler supports network communication code generation, debug tracing injection, and formal logical equivalence checks. Furthermore, it incorporates a performance constraint-aware optimization module to automatically optimize the generated state machine, thereby improving simulation efficiency, reducing development complexity, and enhancing verifiability while ensuring the semantic correctness of the protocol.