75 results about "Cache controller" patented technology

The invention relates to a final-stage cache design method based on near memory calculation, and belongs to the technical field of near memory calculation. And compared with a near memory processor near a traditional main memory, data access and calculation can be carried out more quickly, and the calculation throughput rate can be improved. According to the near storage calculation, a near storage processor and a last-stage cache storage array are directly designed in an integrated mode, faster memory access is achieved through an internal bus interconnection mode, and the problem of a storage wall between the calculation speed and the memory access speed and the problem of a power consumption wall of data handling are relieved to a certain degree. The last-stage cache controller cooperates with the embedded processor, and can dynamically coordinate between a standard cache function and a calculation mode. Through a synchronization mechanism in a last-stage cache controller, a memory access request from a host CPU and a calculation task executed by an embedded processor in a last-stage cache are transparently balanced, so that efficient near-memory calculation under cache consistency is realized.

A system includes a host device, a memory expanding device, and a switch connecting the host device and the memory expansion device, wherein the host device includes a cache controller including a prefetch support circuit configured to generate prefetch information, a root complex configured to transmit the prefetch information to the memory expanding device and receive prefetch data from the memory expanding device, and one or more prefetch buffers storing the prefetch data, and the memory expanding device includes a memory device and a memory controller including a prefetch decision circuit configured to read the prefetch data from the memory device based on the prefetch information received from the host device and prefetch the prefetch data to the host device.

The invention discloses a cache controller for multi-control storage, a control method, a system and a server, is applied to the technical field of storage hardware, and aims to solve the problems of wiring complexity, cost reduction, cache utilization rate improvement and write-in delay of multi-control storage in related technologies. The cache controller comprises a switch supporting multi-host information sharing, a cache module connected with the switch and a central processing unit, the switch is provided with at least two first external bus interfaces used for being connected with storage controller nodes, and the central processing unit is connected with the cache module and the central processing unit. The division module is used for dividing a corresponding cache region for the storage controller node in the cache module under the condition that the switch detects that the storage controller node is accessed to the switch; the switch is used for acquiring the cache data sent by the storage controller node and writing the cache data into a cache region corresponding to the storage controller node in the cache module; the wiring complexity, the wiring cost and the writing delay can be reduced, and the cache utilization rate is improved.

Cache memory systems employing multiple-level hierarchy cache coherency architecture, and related methods and computer-readable media. A processor-based system includes separate dies that each have a processor and local cache memory logically forming a portion of global cache memory for a system address space. To provide a single point of cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point of cache coherency in the global cache memory. Thus, a cache coherency protocol based on a single point of cache coherency can be implemented. However, the proxy cache controller circuits are also capable of locally servicing memory requests solely within its die, when possible to maintain cache coherency, to provide lower latency memory transactions

Provided is a semiconductor integrated circuit module including DRAM caches in a stacked structure, capable of preventing an increase in tag memory capacity on a processor side, reducing hit latency, and improving hit rate. A computing system (1000) is provided with a CPU (100), a main memory (300), and a cache DRAM circuit (400) stacked on the CPU (100). The cache DRAM circuit (400) operates as a group-connected cache memory. The address space of the main memory (300) is divided into a plurality of first sections, the address space of the cache DRAM circuit (400) is divided into a plurality of second sections in one-to-one correspondence with the first sections, and each second section comprises a plurality of paths. The cache controller (111) uniformly accesses rows in a plurality of paths corresponding to the address of the accessed main memory (300).

Cache memory systems employing a multi-level hierarchy cache coherency architecture, and related methods and computer readable media. A processor-based system includes multiple independent dies, each die having a processor and a local cache memory that logically forms part of a global cache memory in a system address space. To provide single point cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point cache coherency in the global cache memory. Thus, a single point cache coherency protocol can be implemented. However, the proxy cache controller circuits can also be able to locally service memory requests within their own die only, to provide lower latency memory transactions, while still being able to maintain cache coherency.

If sufficient memory resources are allowed access, components on an IC chip can operate faster or provide higher performance relative to power consumption. However, if each component is provided with its own memory, the chip becomes expensive. In the described implementation, memory is shared among two or more components (110, 114, 116). For example, a processing component (116) may include computing circuitry (206) and memory (106) coupled thereto. A multi-component cache controller (114) is coupled to memory (106). Logic circuitry (202) is coupled to the cache controller (114) and memory (106). The logic circuitry (202) selectively divides memory (106) into multiple memory partitions (108). A first memory partition (108-1) may be allocated to computing circuitry (206) and provide storage for computing circuitry (206). A second memory partition (108-2) may be allocated to the cache controller (114) and provide storage for multiple components (110). The relative capacity of memory partitions is adjustable to accommodate fluctuating demand without having to dedicate separate memory to a component.

The embodiment of the invention discloses a GPU chip, a ray tracing method, a graphics card and computer equipment, and relates to the field of GPU graphic rendering. The GPU chip comprises a GPU core, an on-chip cache and a cache controller, the on-chip cache is used for storing ray tracing data required by ray tracing calculation; the GPU core is used for sending a data reading instruction to the cache controller; the cache controller is used for reading the ray tracing data from the on-chip cache based on the data reading instruction and sending the ray tracing data to the GPU core; and the GPU core is used for executing ray tracing calculation based on the ray tracing data. By adopting the GPU chip provided by the invention, a large amount of occupation of a GPU core in ray tracing calculation can be avoided, and a relatively high data access speed is achieved.

The present disclosure provides a cache architecture comprising a cache memory having a tag storage and a data storage, a miss status holding register (MSHR) configured to track memory requests where each memory request includes a NoFill field, a safe history buffer (SHB) configured to store safe memory addresses and generate cache line fetch requests based on the stored safe memory addresses, and a cache controller configured to prevent cache fills for memory requests having the NoFill field set, send data to a processor without filling the cache memory when the NoFill field is set, and fill the cache memory with cache lines retrieved by the cache line fetch requests generated by the SHB. The cache architecture provides security against cache timing attacks by decorrelating cache fills from actual memory requests while maintaining performance through the safe history buffer mechanism.

This application relates to methods and apparatus for facilitating write miss caches in a caching system. Example methods, apparatuses, systems, and articles of art are provided for facilitating write miss caches in a caching system. One example apparatus (110) includes: a first cache storage area (214); a second cache storage area (218), wherein the second cache storage area (218) includes a first portion and a second portion for storing a first set of data evicted from the first cache storage area (214); a cache controller (222) coupled to the first cache storage area (214) and the second cache storage area (218), and configured to: receive a write operation; determine that the write operation has resulted in a miss in the first cache storage area (214); and, in response to the miss in the first cache storage area (214), provide write miss information associated with the write operation to the second cache storage area (218) for storage in the second portion.

Examples described herein relate to a cache fabric that includes a set of routers of a first tier and a plurality of cache controller clusters of a second tier. A router of the set of routers is accessible via an interface to receive a memory access request from a processor and select from a set of cache controllers based on a cluster identifier and a memory address, and provide the memory access request to the selected set of cache controllers. The selected set of cache controllers may receive memory access requests and serve memory access requests from the cache device, or forward memory access requests to a second cache controller or second cache device associated with the cache device.

Embodiments herein describe circuitry and techniques to implement shunt current control of an on-chip voltage regulator of a memory storage system using hardware components and computer software tools. Disclosed embodiments provide an on-chip voltage regulator with enhanced performance, reducing power requirements, and minimizing noise and voltage fluctuations of the regulator output, based on a cache activity signal produced by a cache controller.

The invention provides a data reading processing method, a multi-level cache processor architecture, a cache controller and equipment, the method is applied to the multi-level cache processor architecture, and the multi-level cache processor architecture comprises special caches corresponding to processor cores and shared caches shared by the processor cores. The method comprises the following steps: under the condition that a write request hits shared-state first data in a special cache, the special cache sends an exclusive-state read request to a shared cache; and before the special cache receives the first data in the exclusive state returned by the shared cache, if the special cache receives the second data returned by the shared cache and confirms that the first data needs to be evicted when the second data is filled into the special cache, the special cache cancels the operation of sending the eviction request to the shared cache. According to the method, the problem of inconsistent cache data of the processor can be avoided.

The invention is suitable for the technical field of artificial intelligence, and relates to a model reasoning method and a model reasoning system. The method comprises the following steps: acquiring interlayer structure characteristics of a target model needing model reasoning and a first initial storage address of a first layer weight parameter of the target model in a persistent storage space through an address predictor; according to the first initial storage address and the interlayer structure characteristics, calculating a storage address offset corresponding to the weight parameter of each layer; according to the first initial storage address and the storage address offset corresponding to each layer of weight parameter, determining a first target storage address of each layer of weight parameter in the persistent storage space, and sending the first target storage address to a cache controller, each first target storage address is used for the cache controller to pre-fetch each layer of weight parameter from the persistent storage space for the calculation unit to use. The overall performance of model reasoning can be improved, and the method is particularly suitable for efficient deployment of a large-scale deep learning model on edge equipment or terminal equipment.

The invention provides a data processing method and device, electronic equipment and a storage medium, and the method comprises the steps: determining a target cache line matched with address information from a plurality of cached cache lines according to the address information in a received data processing request; determining a target sector matched with the address information from a plurality of sectors of the target cache line under the condition that the target cache line is determined to be in the effective state; and performing data processing in the target sector according to the sector state of the target sector. According to the mode, the data overhead for transmitting the whole cache line is avoided, so that the bandwidth utilization rate and the transmission efficiency are improved, the system power consumption is reduced, and the system performance is improved.

A cache controller of a cache assigns a dirty tracking bit for each dirty byte of a cache line. Once a predetermined interval has elapsed without any accesses to the cache line or to a cache set that includes the cache line, the cache controller compresses contiguous dirty tracking bits for each portion of the cache line. Compressing the dirty tracking bits for contiguous dirty portions of the cache line allows the cache to store more dirty data using fewer dirty tracking bits, reducing area cost and bandwidth among levels of a memory hierarchy.

Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device includes a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value based on the plurality of content costs. The cache controller circuit is further configured to evict the target cached data value from the cache memory device.

The invention provides a packaging structure and a data access method, which can be applied to the technical field of hardware. The packaging structure comprises a substrate, a processing layer, a cache layer, an interconnection layer and a global cache controller, and the interconnection layer and the global cache controller are located on the substrate and connected with each other through a physical channel on the substrate; the processing layer is located on the side, away from the substrate, of the interconnection layer and connected with the interconnection layer; the cache layer is located on the side, away from the substrate, of the global cache controller and connected with the global cache controller; the global cache controller is used for executing an access operation on the cache layer according to an access request provided by the processing layer, and returning response data generated by the cache layer based on the access operation to the processing layer; and the interconnection layer is used for carrying out routing selection on data transmission between the processing layer and the global cache controller.

Various embodiments include systems and methods for improving Dynamic Random-Access Memory (DRAM) efficiency and Last Level Cache (LLC) utilization. A computing system may be configured to dynamically adjust DRAM efficiency calculations based on multiple system metrics and conditions (e.g., DDR frequency, density, refresh rates, etc.) for more accurate frequency settings and improved power consumption. The computing system may use a multi-stage approach that includes memory and cache allocation, bandwidth management, and frequency settings. The computing system may fine-tune the DRAM efficiency calculations based on various other factors (e.g., cache miss rates, power consumption, etc.), dynamically modify operational parameters (e.g., DDR frequencies, etc.) in response to specific events or computational tasks, and work in tandem with other system components (e.g., a Last-Level Cache Controller (LLCC), etc.) to improve resource allocation.

The invention discloses a high-performance cache fault tolerance method with a speculative execution mechanism. According to the method, a cache controller, a check code encoder, a check code decoder and an instruction submission unit check determiner are arranged in a cache mechanism; in a cache access stage, a cache controller adopts a speculative execution mechanism for data, assumes a successfully matched data field in a cache line as correct to-be-read data, and sends successfully matched cache line data to an instruction submission unit verification determiner; and in an instruction submission stage, an instruction submission unit verification determiner judges the correctness of speculative execution based on the error detection and correction information of the check code, and if an error is detected, a rollback recovery mechanism is triggered to recover the execution state. According to the method, check code coding and decoding logic is shifted out of a critical path of cache access through a speculation execution mechanism, so that the performance of a processor is improved; meanwhile, according to the method, through rollback operation, high performance is kept, and meanwhile the accuracy of data is fully guaranteed.

The application relates to the technical field of computer and big data management, and discloses a dynamic random access memory cache management method and system. The method comprises the following steps: collecting task access flow data in real time; quantifying the concentration or dispersion of the access based on Shannon entropy; dynamically adjusting the cache partition size according to the entropy value; synchronously and cooperatively optimizing the prefetching and replacement strategies in the partition; and continuously and adaptively adjusting through closed-loop control. The system comprises an access log module, an entropy calculation unit, a strategy scheduler and a cache controller. Through the above technical scheme, the application can realize double-elastic cooperative optimization of cache partition and management strategy, and significantly improve the cache hit rate, system stability and resource utilization efficiency.

The invention provides a data reading processing method, a multi-level cache processor architecture, a cache controller and equipment, the method is applied to the multi-level cache processor architecture, a transmission queue and a transfer queue are arranged in a first cache of the architecture, the transmission queue is used for storing return data corresponding to a first read request missed in the first cache, and the transfer queue is used for transmitting the return data corresponding to the first read request missed in the first cache. Generating a return data packet based on the return data and the backfilling requirement; the transfer queue is used for storing data requested by the missed second read request in the first cache, and generating a return data packet based on the requested data; the method comprises the following steps: under the condition that a first cache receives return data corresponding to a target read request returned by a second cache, determining a request type of the target read request; and storing the target data requested by the target read request and the target read request into a transfer queue under the condition that the target read request is determined to be the specific type of read request. According to the method, the cache data reading efficiency can be improved, and the data reading delay can be reduced.

The application is suitable for the field of microprocessor architecture, on-chip multi-core system and embedded real-time computing technology, and provides a fine-grained cache partition lock method based on RISC-V extension instruction and a processor, the method comprising: adding a Zicpl extension instruction family in the RISC-V instruction set architecture, the Zicpl extension instruction family comprising a LOCK.CP instruction, an UNLOCK.CP instruction, a TESTLOCK.CP instruction and a SET.CP instruction; adding a partition lock table on the cache controller side of the processor, the partition lock table comprising a plurality of entries, each entry comprising an owner field, a timeout field and a valid field; adding a lock flag and a partition identification field in the Tag area of the cache memory; the application can significantly improve the real-time performance and system energy efficiency, and has significant industrial and economic value.

The invention relates to a mirror image and weight file processing method and system, equipment and a storage medium. The method comprises the following steps: deploying a first target object in a container arrangement platform; in response to an event of creating or updating the CRD by a user, the central cache controller monitors and analyzes the event to obtain an instance resource, and pre-distributes the mirror image and the weight file based on the instance resource; a node cache agent on each working node monitors sub-instance resources matched with the working node, and pulls a mirror image or a weight file to a local cache based on the sub-instance resources to obtain a target mirror image and a target weight file; and in response to the training task or the reasoning task created by the user, loading the locally cached target weight file into the container instance created by the target mirror image. According to the scheme provided by the invention, the mirror image and the weight file can be decoupled, and efficient distribution and dynamic loading are realized.

Embodiments of the present disclosure disclose a data processing method, system, device, equipment and storage medium, wherein the data processing method comprises: in a geometry stage of a graphics rendering performed by a graphics processing unit, in response to a read application initiated by a geometry data processing module, allocating an interface for accessing a local storage system of the graphics processing unit to the read application; obtaining geometry data corresponding to the read application from the local storage system through an interface corresponding to the read application; caching the geometry data to a shared memory space of a geometry cache controller; and returning the geometry data in the shared memory space to the geometry data processing module.

The processing system (100) flushes cache lines (308, 309) from the cache (302) that share the same memory page (147) as the cache line (304) identified for eviction. The cache controller (175) of the processing system identifies the cache line as scheduled for eviction. In response, the cache controller identifies additional “dirty sacrifice” cache lines (cache lines that have been modified at the cache but not yet written back to memory) associated with the same memory page and writes each of the identified cache lines to the same memory page in memory (105). By writing each of the dirty sacrifice cache lines associated with the memory page to memory, the processing system reduces memory overhead and improves processing efficiency.

The invention relates to the technical field of industrial communication networks, in particular to a BootROM code patch loading method and system based on a CPU Cache mechanism, and the method comprises the steps: obtaining patch configuration data; a Cache controller of the CPU is initialized, an instruction Cache and a data Cache are enabled, and a write allocation strategy and a consistency monitoring mechanism are started; writing the patch code block into a target address of the address space of the BootROM, using the read-only attribute of the BootROM to enable the write-in operation to distribute a cache line in the data Cache to store the patch code block, and marking the patch code block as a modified state; and when the CPU executes to a target address, triggering the instruction Cache to be missing, obtaining patch code blocks from the data Cache through a consistency monitoring mechanism, and executing the patch code blocks, so that the BootROM codes are dynamically repaired. The system comprises a control module, a Cache management module, a bus interface module and a patch storage module. According to the method, online update of the BootROM code is realized through a Cache mechanism, and the technical problem that a read-only memory cannot be directly modified is solved.

A peripheral device includes a processor, a memory interface, a host interface and a cache controller. The processor executes software code. The cache memory caches a portion of the software code. The memory interface communicates with a NVM storing a replica of the software code. The host interface communicates with hosts storing additional replicas of the software code. The cache controller is to determine whether each host is allocated for code fetching, to receive a request from the processor for a segment of the software code, when available in the cache memory to fetch the segment from the cache memory, when unavailable in the cache memory and at least one host is allocated, to fetch the segment from the hosts that are allocated, when unavailable in the cache memory and no host is allocated, to fetch the segment from the NVM, and to serve the fetched segment to the processor.

The invention relates to a hardware architecture simulation tool oriented to system-level chip interconnection optimization, which is characterized in that a processor core, a cache controller, a memory controller and an on-chip interconnection network model with an accurate period are integrated in a full-system joint simulation framework, and the conversion between a cache consistency message and an interconnection data unit is realized through a network interface controller; network delay is fed back to a system simulation scheduler with cycle-level precision, an interconnection network adopts a router micro-architecture with an accurate cycle for modeling, key stages such as buffering, routing, virtual channel distribution, switch distribution and link traversal are finely depicted, and virtual channel flow control and a point-to-point sorting mechanism are combined, so that the routing efficiency is improved. And a power consumption analysis model based on activity counting is introduced, and the dynamic power consumption and the static leakage power consumption of the interconnection network are accurately evaluated. According to the application, various network topologies, routing strategies and hardware parameter configurations are supported, and the comprehensive influence of the interconnection architecture on the performance and energy efficiency of the chip is accurately evaluated at the system level.

The invention relates to dynamic allocation of cache memory as RAM. An apparatus includes a cache controller circuit and a cache memory circuit, the cache memory circuit further including a cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. The request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured to, in response to the request, convert the one or more cache lines to a directly addressable random access memory (RAM) by excluding the one or more cache lines from the cache operation.