9 results about "Dram cache" patented technology

The present disclosure provides a memory management method, an electronic device and a program product, and relates to the technical field of computers. The memory management method comprises the following steps: dividing a DRAM cache into a plurality of cache sets, and dividing each cache set into a plurality of logical subsets, each logical subset containing a plurality of physical cache paths; constructing a metadata tree corresponding to each cache set; in response to a memory access request, determining a physical address corresponding to the memory access request; determining a cache set corresponding to the memory access request; determining whether the memory access request is a hit; in the case that the memory access request is not a hit and there is no idle physical cache path, locating a target logical subset from the metadata tree according to path indication information; selecting a target physical cache path according to a reference prediction value; replacing the storage content of the target physical cache path with request data, and updating the reference prediction value of the target physical cache path to an initial value.

The application provides a cache access method, a DRAM cache, a cache management system and a computing device. The cache access method comprises receiving a memory access request, the request specifying a data size to be accessed; determining a corresponding granularity cache area in the DRAM cache according to the data size; and the granularity cache area is obtained by dividing the DRAM cache area according to different granularity sizes. Thus, the corresponding granularity cache area is selected according to the data size of the request, the appropriate cache block can be positioned more accurately, the opportunity of DRAM cache hit is increased, and the memory access delay is reduced. The proportion of useful data in the DRAM cache is improved, and the cache space utilization is improved.

The present disclosure relates to a DRAM cache management device. The DRAM cache management device includes: a processor; a main memory; a DRAM cache memory; a DRAM cache management unit connected to one or more cache frames that partition the DRAM cache memory; and a memory management unit configured to generate cache-miss information and transmit the generated cache-miss information to the DRAM cache management unit, wherein the DRAM cache management unit may be configured to receive the cache-miss information from the memory management unit, allocate a free cache frame from among the one or more cache frames upon receiving the cache-miss information, generate a data replication command, and update cache-main memory mapping information between the DRAM cache frames and one or more main memory frames that partition the main memory.

A high-capacity cache memory is implemented by multiple heterogenous DRAM dies, including a dedicated tag-storage DRAM die architected for low-latency tag-address retrieval and thus rapid hit / miss determination, and one or more capacity-optimized cache-line DRAM dies that render a net cache-line storage capacity orders of magnitude beyond that of state-of-the art SRAM cache implementations. The tag-storage die serves double-duty in some implementations, yielding rapid tag hit / miss determination for cache-line read / write requests while also serving as a high-capacity snoop-filter in a memory-sharing multiprocessor environment.

The invention provides a memory management method, electronic equipment and a program product, and relates to the technical field of computers. The memory management method comprises the steps that a DRAM cache is divided into a plurality of cache sets, each cache set is divided into a plurality of logic subsets, and each logic subset comprises a plurality of physical cache paths; constructing a metadata tree corresponding to each cache set; in response to the memory access request, determining a physical address corresponding to the memory access request; determining a cache set corresponding to the memory access request; judging whether the memory access request is hit; in the case of miss and no idle physical cache path, positioning from the metadata tree according to the path indication information to obtain a target logic subset; selecting a target physical cache path according to the rereference predicted value; and replacing the storage content of the target physical cache path with the request data, and updating the rereference predicted value of the target physical cache path to the initial value.

A dynamic random access memory (DRAM) device includes functions configured to aid with operating the DRAM device as part of data caching functions. The DRAM is configured to respond to at least two types of commands. A first type of command (cache data access command) seeks to access a cache line of data, if present in the DRAM cache. A second type of command (cache probe command) seeks to determine whether a cache line of data is present, but is not requesting the data be returned in response. In response to these types of access commands, the DRAM device is configured to receive cache tag query values and to compare stored cache tag values with the cache tag query values. A hit / miss (HM) interface / bus may indicate the result of the cache tag compare and stored cache line status bits to a controller.

This invention relates to a method and system for ensuring Quality of Service (QoS) for multi-tenant NVMe solid-state drives (SSDs) based on extended protection information (PI), belonging to the field of computer storage technology. The method includes: when sending I / O commands, the host side reuses the application tag in the NVMe standard protection information (PI) field to embed a custom QoS token, which contains I / O priority and tenant identifier; after enabling QoS-PI mode, the SSD controller parses the token and, based on the priority, queries a pre-defined policy to dynamically allocate hardware resources such as NAND channel access weights, garbage collection latency tolerance, and DRAM cache quotas. This invention achieves hardware-level, fine-grained performance isolation, effectively suppressing "noisy neighbor" interference, improving the determinism of high-priority application I / O, while eliminating the need for static partitioning, maintaining high resource utilization, and ensuring full compatibility with the NVMe protocol.

A high-capacity cache memory is implemented by one or more DRAM dies in which individual cache entries are split across multiple DRAM storage banks such that each cache-line read or write is effected by a time-staggered set of read or write operations within respective storage banks spanned by the target cache entry.

Disclosed are a DRAM cache system and an operating method thereof. The DRAM cache system includes a front-end module including a translation lookaside buffer (TLB) and a page table entry (PTE) and a back-end module, and the operating method includes checking, by the front-end module, the PTE when a TLB miss occurs in association with a memory request, calling, by the front-end module, a miss handler when a result of the checking the PTE is a tag miss, performing, by the front-end module, a tag update corresponding to the memory request through the miss handler, and offloading, by the front-end module, a cache-fill command to the back-end module.