21 results about "Dram cache" patented technology

Three-dimensional (3D) DRAM integrated in the same package as compute logic enable forming high-density caches. In one example, an integrated 3D DRAM includes a large on-de cache (such as a level 4 (L4) cache), a large on-die memory-side cache, or both an L4 cache and a memory-side cache. One or more tag caches cache recently accessed tags from the L4 cache, the memory-side cache, or both. A cache controller in the compute logic is to receive a request from one of the processor cores to access an address and compare tags in the tag cache with the address. In response to a hit in the tag cache, the cache controller accesses data from the cache at a location indicated by an entry in the tag cache, without performing a tag lookup in the cache.

Provided is a semiconductor integrated circuit module including DRAM caches in a stacked structure, capable of preventing an increase in tag memory capacity on a processor side, reducing hit latency, and improving hit rate. A computing system (1000) is provided with a CPU (100), a main memory (300), and a cache DRAM circuit (400) stacked on the CPU (100). The cache DRAM circuit (400) operates as a group-connected cache memory. The address space of the main memory (300) is divided into a plurality of first sections, the address space of the cache DRAM circuit (400) is divided into a plurality of second sections in one-to-one correspondence with the first sections, and each second section comprises a plurality of paths. The cache controller (111) uniformly accesses rows in a plurality of paths corresponding to the address of the accessed main memory (300).

A dynamic random access memory (DRAM) device includes functions configured to aid with operating the DRAM device as part of data caching functions. The DRAM, as part of a command seeking to access cache line data, provides information (cache hints) about the cache line status (e.g., valid / invalid, modified / unmodified, etc.) of cache lines that were not directly addressed by the command. These cache hints may be used to initiate operations / command, based on the cache hints, for “cleaning” modified (a.k.a., “dirty”) cache lines by reading the modified data and providing it to other memory levels (e.g., a higher cache level, main memory, backing store, etc.). The DRAM device implements commands that, based on information about a plurality of cache lines (e.g., cache lines stored in the same way of a set associative cache) select a cache line to be cleaned and / or provided for provision to other memory levels.

The invention discloses a BGA SSD power-down protection system and method, through monitoring a primary power supply of the system, the power-down monitoring time is earlier, and before the power supply of the system is not completely dropped to a voltage value at which the system cannot work, the power-down protection time is shorter than that of the primary power supply of the system. The central processing unit system is informed to complete data storage of the operating system in time, and the BGA SSD chip is informed to complete data write-back of the cache region in time, so that storage of system data is facilitated. The stored energy used for completing the related operation is the board-level inherent energy maintained by the time difference of the voltage drop, and through the architecture of the load switch and the energy storage capacitor module, the low-cost and low-complexity power-down protection design is realized, it is ensured that the BGA SSD chip has enough time to complete the DRAM cache data write-back work after receiving the power-down alarm signal, and the reliability of the BGA SSD chip is improved. And a data protection effect is achieved.

A high-capacity cache memory is implemented by multiple heterogenous DRAM dies, including a dedicated tag-storage DRAM die architected for low-latency tag-address retrieval and thus rapid hit / miss determination, and one or more capacity-optimized cache-line DRAM dies that render a net cache-line storage capacity orders of magnitude beyond that of state-of-the art SRAM cache implementations. The tag-storage die serves double-duty in some implementations, yielding rapid tag hit / miss determination for cache-line read / write requests while also serving as a high-capacity snoop-filter in a memory-sharing multiprocessor environment.

The present disclosure provides a memory management method, an electronic device and a program product, and relates to the technical field of computers. The memory management method comprises the following steps: dividing a DRAM cache into a plurality of cache sets, and dividing each cache set into a plurality of logical subsets, each logical subset containing a plurality of physical cache paths; constructing a metadata tree corresponding to each cache set; in response to a memory access request, determining a physical address corresponding to the memory access request; determining a cache set corresponding to the memory access request; determining whether the memory access request is a hit; in the case that the memory access request is not a hit and there is no idle physical cache path, locating a target logical subset from the metadata tree according to path indication information; selecting a target physical cache path according to a reference prediction value; replacing the storage content of the target physical cache path with request data, and updating the reference prediction value of the target physical cache path to an initial value.

The application provides a cache access method, a DRAM cache, a cache management system and a computing device. The cache access method comprises receiving a memory access request, the request specifying a data size to be accessed; determining a corresponding granularity cache area in the DRAM cache according to the data size; and the granularity cache area is obtained by dividing the DRAM cache area according to different granularity sizes. Thus, the corresponding granularity cache area is selected according to the data size of the request, the appropriate cache block can be positioned more accurately, the opportunity of DRAM cache hit is increased, and the memory access delay is reduced. The proportion of useful data in the DRAM cache is improved, and the cache space utilization is improved.

Various embodiments are provided for providing a dynamic random access memory ("DRAM") cache as a second type of memory in a computing system by a processor. One or more free bits of the DRAM, a data compression operation, or a combination thereof can be used to clear a selected amount of bytes in a memory row. Cache directory and data can be stored in the memory row. The DRAM cache is configured as a cache of the second type of memory.

A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive non-volatile memory. Local controller manages communication between the DRAM cache and non-volatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.

The present disclosure relates to a DRAM cache management device. The DRAM cache management device includes: a processor; a main memory; a DRAM cache memory; a DRAM cache management unit connected to one or more cache frames that partition the DRAM cache memory; and a memory management unit configured to generate cache-miss information and transmit the generated cache-miss information to the DRAM cache management unit, wherein the DRAM cache management unit may be configured to receive the cache-miss information from the memory management unit, allocate a free cache frame from among the one or more cache frames upon receiving the cache-miss information, generate a data replication command, and update cache-main memory mapping information between the DRAM cache frames and one or more main memory frames that partition the main memory.

A high-capacity cache memory is implemented by multiple heterogenous DRAM dies, including a dedicated tag-storage DRAM die architected for low-latency tag-address retrieval and thus rapid hit / miss determination, and one or more capacity-optimized cache-line DRAM dies that render a net cache-line storage capacity orders of magnitude beyond that of state-of-the art SRAM cache implementations. The tag-storage die serves double-duty in some implementations, yielding rapid tag hit / miss determination for cache-line read / write requests while also serving as a high-capacity snoop-filter in a memory-sharing multiprocessor environment.

The invention provides a memory management method, electronic equipment and a program product, and relates to the technical field of computers. The memory management method comprises the steps that a DRAM cache is divided into a plurality of cache sets, each cache set is divided into a plurality of logic subsets, and each logic subset comprises a plurality of physical cache paths; constructing a metadata tree corresponding to each cache set; in response to the memory access request, determining a physical address corresponding to the memory access request; determining a cache set corresponding to the memory access request; judging whether the memory access request is hit; in the case of miss and no idle physical cache path, positioning from the metadata tree according to the path indication information to obtain a target logic subset; selecting a target physical cache path according to the rereference predicted value; and replacing the storage content of the target physical cache path with the request data, and updating the rereference predicted value of the target physical cache path to the initial value.

A dynamic random access memory (DRAM) device includes functions configured to aid with operating the DRAM device as part of data caching functions. The DRAM is configured to respond to at least two types of commands. A first type of command (cache data access command) seeks to access a cache line of data, if present in the DRAM cache. A second type of command (cache probe command) seeks to determine whether a cache line of data is present, but is not requesting the data be returned in response. In response to these types of access commands, the DRAM device is configured to receive cache tag query values and to compare stored cache tag values with the cache tag query values. A hit / miss (HM) interface / bus may indicate the result of the cache tag compare and stored cache line status bits to a controller.

This invention relates to a method and system for ensuring Quality of Service (QoS) for multi-tenant NVMe solid-state drives (SSDs) based on extended protection information (PI), belonging to the field of computer storage technology. The method includes: when sending I / O commands, the host side reuses the application tag in the NVMe standard protection information (PI) field to embed a custom QoS token, which contains I / O priority and tenant identifier; after enabling QoS-PI mode, the SSD controller parses the token and, based on the priority, queries a pre-defined policy to dynamically allocate hardware resources such as NAND channel access weights, garbage collection latency tolerance, and DRAM cache quotas. This invention achieves hardware-level, fine-grained performance isolation, effectively suppressing "noisy neighbor" interference, improving the determinism of high-priority application I / O, while eliminating the need for static partitioning, maintaining high resource utilization, and ensuring full compatibility with the NVMe protocol.

A high-capacity cache memory is implemented by one or more DRAM dies in which individual cache entries are split across multiple DRAM storage banks such that each cache-line read or write is effected by a time-staggered set of read or write operations within respective storage banks spanned by the target cache entry.

Apparatus and methods are disclosed, including sending, by an application executing on a processor of a computing system to a dynamic random access memory (DRAM), a memory operation indicating a DRAM cache line stored in the DRAM; receiving, by the processor, DRAM metadata stored in the DRAM for the DRAM cache line; identifying, by the processor, a tiered memory region of multiple tiered memory regions storing a tiered memory cache line containing target data of the memory operation when the DRAM metadata indicates that the target data is not stored in the DRAM cache line; and loading the tiered memory cache line containing the target data into the DRAM, loading the DRAM cache line into the identified tiered memory region, and updating the DRAM metadata.

Disclosed are a DRAM cache system and an operating method thereof. The DRAM cache system includes a front-end module including a translation lookaside buffer (TLB) and a page table entry (PTE) and a back-end module, and the operating method includes checking, by the front-end module, the PTE when a TLB miss occurs in association with a memory request, calling, by the front-end module, a miss handler when a result of the checking the PTE is a tag miss, performing, by the front-end module, a tag update corresponding to the memory request through the miss handler, and offloading, by the front-end module, a cache-fill command to the back-end module.

A memory controller includes an interface to couple to storage class memory (SCM) space and dynamic random access memory (DRAM) space. At least a portion of the DRAM storage space is configured as a cache for the SCM storage space. The interface to receive an incoming tag address for a read operation. Tag comparison circuitry performs a comparison of the incoming tag address to stored tag addresses associated with the DRAM cache. The data in the addressed DRAM cache space is selectively provided directly to the memory controller as first read data based on the results of the comparison.

The invention discloses a distributed metadata and data unified storage system and method based on PMem. The system comprises a metadata and data collaborative management module, a distributed storage cluster adaptation layer, a DRAM cache control module, a PMem acceleration engine module and an SSD persistent storage module. The access delay of data and metadata is greatly reduced through the DRAM cache control module and the PMem acceleration engine module; data popularity value evaluation and a storage medium allocation formula are applied, so that the data can be accurately stored in the most appropriate storage medium, and the system performance is further optimized; and different characteristics of the DRAM cache control module, the PMem acceleration engine module and the SSD persistent storage module are fully played, and the storage medium is dynamically allocated according to the data heat value, so that the waste of storage resources is avoided. The overuse of expensive storage media is reduced, and meanwhile, the high-performance access of the hotspot data is ensured.

The invention relates to a fixed ratio memory tiering with variable cache line size. Apparatuses and methods are disclosed that include sending, by an application executing on a processor of a computing system, a memory operation to a dynamic random access memory (DRAM) indicating a DRAM cache line stored in the DRAM; receiving, by the processor, DRAM metadata of the DRAM cache line stored in the DRAM; when the DRAM metadata indicates that target data of the memory operation is not stored in the DRAM cache line, identifying, by the processor, a hierarchical memory region of a plurality of hierarchical memory regions storing a hierarchical memory cache line containing the target data; and loading the hierarchical memory cache line containing the target data into the DRAM, loading the DRAM cache line into the identified hierarchical memory region, and updating the DRAM metadata.

A non-volatile dual in-line memory module (NVDIMM) supporting a DRAM cache mode and an operating method for the NVDIMM are provided. The NVDIMM includes a DRAM chip, an NVM chip, and a controller that controls the DRAM chip to operate as a cache memory for the NVM chip. When the read latency (RL) of the DRAM chip and the write latency (WL) of the NVM chip are consistent with each other, the controller sends a read command to the DRAM chip with reference to the cache address of data requested to be written from the host to the NVM chip, and sends a write command to the NVM chip with reference to the address of the data requested to be written.