Dram/nvm hierarchical heterogeneous memory access method and system with software-hardware cooperative management

Abstract

The present invention provides a DRAM/NVM hierarchical heterogeneous memory system with software-hardware cooperative management schemes. In the system, NVM is used as large-capacity main memory, and DRAM is used as a cache to the NVM. Some reserved bits in the data structure of TLB and last-level page table are employed effectively to eliminate hardware costs in the conventional hardware-managed hierarchical memory architecture. The cache management in such a heterogeneous memory system is pushed to the software level. Moreover, the invention is able to reduce memory access latency in case of last-level cache misses. Considering that many applications have relatively poor data locality in big data application environments, the conventional demand-based data fetching policy for DRAM cache can aggravates cache pollution. In the present invention, an utility-based data fetching mechanism is adopted in the DRAM/NVM hierarchical memory system, and it determines whether data in the NVM should be cached in the DRAM according to current DRAM memory utilization and application memory access patterns. It improves the efficiency of the DRAM cache and bandwidth usage between the NVM main memory and the DRAM cache.

Description

TECHNICAL FIELD[0001]The present invention belongs to the field of cache performance optimization in a DRAM / NVM heterogeneous memory environment, and in particular, a DRAM / NVM hierarchical heterogeneous memory access method and system with software-hardware cooperative management schemes are designed, and an utility-based data fetching mechanism is proposed in this system.BACKGROUND ART[0002]With the development of the multi-core and multi-threading technology, Dynamic Random Access Memory (DRAM) can no longer meet the growing memory demand of applications due to restrictions in terms of power consumption and techniques. Emerging Non-Volatile Memories (NVMs), such as Phase Change Memory (PCM), Spin Transfer Torque Magneto resistive Random Access Memory (STT-MRAM), and Magnetic Random Access Memory (MRAM), have features such as byte-addressable, comparable read speed with DRAM, near-zero standby power consumption, high density (storing more data per chip), and high scalability, and m...

AI Technical Summary

Benefits of technology

[0018](1) The system modifies the TLB data structure and extends the page table, which enable uniform management of DRAM cache pages and NVM main memory pages, and eliminates hardware costs in a conventional DRAM / NVM hierarchical memory system while reducing memory access delay.

[0019](2) The system monitors memory accesses using some TLB reserved bits, and eliminates huge hardware costs compared with the conventional DRAM / NVM heterogeneous memory system that monitors the page access frequency in the memory controller.

[0020](3) The system develops a utility-based cache fetching method, and a dynamic fetching threshold adjustment algorithm is designed to dynamically adjust the fetching threshold according to application memory access locality and utilization of the DRAM cache, which improves utilization of the DRAM cache and bandwidth usage between the NVM main memory and the DRAM cache.

Problems solved by technology

With the development of the multi-core and multi-threading technology, Dynamic Random Access Memory (DRAM) can no longer meet the growing memory demand of applications due to restrictions in terms of power consumption and techniques.

However, compared with the DRAM, these new non-volatile memories still have a lot of disadvantages: (1) a relatively high read / write delay, where the read speed is approximate twice slower than that of DRAM, and the write speed is almost five times slower than that of the DRAM; (2) high write power consumption; and (3) a limited endurance life.

Therefore, it is unfeasible to directly use these emerging non-volatile memories as the computer main memory.

Therefore, one page migration operation may generate four times of page replication, and thus the time cost of the migration operations are relatively large because the reading phase and the writing phase are performed sequentially.

Besides, if a memory system supports 2 MB or 4 MB superpage to reduce TLB miss rate, the hot page migration mechanism can leads to tremendous time and space overhead.

This implies that the hierarchical heterogeneous memory system has a relatively long access delay when a DRAM cache miss occurs.

In big data environments, a lot of applications have poor temporal / spatial locality, and such data fetching mechanism would aggravate cache pollution.

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