22results about How to "Reduce access latency" patented technology

This invention discloses a cache adjustment method, apparatus, device, and computer-readable storage medium, comprising: collecting access characteristic data from the client layer, object storage daemon layer, and device layer respectively; determining the object access mode of the system based on the access characteristic data; and adjusting the cache priority of each access task, the cache capacity ratio between the client layer and the object storage daemon layer, and the data residence time in the cache layer according to the object access mode; wherein the cache layer includes the client layer and the object storage daemon layer. This invention improves cache hit rate and overall read / write throughput performance, and reduces access latency.

This application proposes a method, apparatus, electronic device, and storage medium for arranging vector elements. The method includes: acquiring vector elements to be processed, and determining the levels of each switching node (SN) unit in a butterfly network based on the number of vector elements to generate the butterfly network; wherein the butterfly network is used to arrange the vector elements; determining the input-output mapping relationship between the levels of each switching node (SN) unit in the butterfly network; determining the target state of the SN unit in each level based on the input-output mapping relationship; arranging the vector elements based on the target state, and performing data processing based on the arranged vector elements. Therefore, this scheme enables the arranged vector elements to be transmitted non-blockingly in the butterfly network, thereby enabling the mapping of complex and variable large model workloads onto vector hardware to achieve efficient data processing execution.

The application relates to the technical field of vehicles, in particular to a vehicle-mounted video sharing method based on a PCIe bus, an automobile central platform, an electronic device and a computer readable storage medium. The method comprises the following steps: a plurality of system-level chips are connected in communication through a PCIe switch; in each system-level chip, an independent shared memory space is respectively allocated for each camera; when any system-level chip acquires video data, the video data is stored in the local shared memory space, and the video data is transmitted to a PCIe domain space through direct memory access after address mapping; other system-level chips acquire the video data from the PCIe domain space and store the video data in the local shared memory space; and in response to a reading request of the video data of an application program running on any system-level chip, the video data is read from the local shared memory space by the application program.

The application discloses a file processing system based on Internet of Things, and relates to the technical field of Internet of Things, which comprises a processing carrier and a plurality of terminals, the processing carrier is used for sending protocols to each terminal, and sharing data and files within a specified range; after accepting the protocols, the plurality of terminals mirror backup internal files and data, each terminal acquires a plurality of sets of marking information, each set of information represents the file and data classification of the terminal, and each terminal marks each working state of itself to acquire working information Z; each terminal comprises a processing module, a receiving module and a mutual inductance module. When working, each terminal in the application collects data or files generated during its own work, classifies and assigns weights to the data or files, and transmits the files and their attached information between the remaining terminals and the processing carrier, so that the working state change speed between different terminals can be improved.

This disclosure relates to the field of semiconductor technology, providing a semiconductor device to address the technical problem that high-bandwidth memory technology still has significant room for improvement. The semiconductor device includes a chip stack structure, comprising: a first semiconductor chip and a second semiconductor chip stack structure stacked along a first direction; the first semiconductor chip includes a controller, a computing module, and an interface module; the controller is configured to: perform a first access operation on stored data in the second semiconductor chip stack structure and send the stored data to the interface module to allow external devices to access the stored data in the second semiconductor chip stack structure through the interface module; and perform a second access operation on the stored data in the second semiconductor chip stack structure and send the stored data to the computing module to allow the computing module to perform computational operations on the stored data. This improves integration and shortens data transmission paths, reducing bandwidth consumption and energy loss.

The invention discloses a GPU memory optimization method and system, and the method comprises the steps: obtaining the real-time change characteristics of a task load through obtaining the dynamic data flow information of the task load and an intermediate data generation rule; according to the real-time change characteristics of the task load, an optimization algorithm based on gradient descent is adopted to determine the distribution proportion and the reserved space of a memory pool, and adjusted memory pool configuration is obtained; extracting available memory block information from the adjusted memory pool configuration, and compressing the intermediate data with low access frequency by adopting a Huffman coding algorithm to obtain a compressed intermediate data storage unit; and if the access frequency of the compressed intermediate data storage unit is lower than a preset threshold value, temporarily storing the compressed intermediate data storage unit to a low-speed storage area, and reallocating memory resources according to the task priority to obtain an optimized memory allocation scheme. According to the method, the memory utilization rate is remarkably improved, the access delay is reduced, and efficient memory resource management is realized.

The application realizes a satellite cloud-oriented distributed file system through a method in the field of distributed systems.The system is composed of five components: a metadata management module, a StorageEngine, a Policy, a client and a satellite topology service module; the metadata management module stores metadata, the Storage Engine is a data storage module, the Policy is a strategy module, the user uses the client to interact with the satellite cloud file system, the satellite topology service module is specially designed for the satellite cloud scene to provide the satellite cloud network topology information for the satellite cloud file system, and the modules communicate with each other through a special file system interface using RPC.The method provided by the application guarantees efficient reading and reliability of metadata for the satellite communication scene, maximally reduces the communication cost and energy loss of replica placement by using the network topology characteristics of the satellite cloud, and maximally reduces the access delay.

The invention discloses a matrix multiplication optimization method and system oriented to an RISC-V architecture, and the method comprises the steps: detecting the hardware characteristics of a target RISC-V platform, and adaptively configuring optimization parameters according to a detection result; performing memory layout and data rearrangement on the input matrix B to realize memory optimization; a multi-level partitioning strategy is adopted to adapt to a memory hierarchical structure, and multi-level partitioning calculation is achieved; carrying out RVV vectorization core calculation by using RISC-V vector instruction extension to realize data-level parallel optimization; the instruction delay is hidden through loop expansion and a software assembly line, and a data prefetching mechanism is adopted to realize instruction-level parallel optimization; performing multi-core parallel computing by using an OpenMP multi-thread technology to realize thread-level parallel optimization; and calculating residual elements by using a vector register to realize tail processing optimization. According to the method, the cache hit rate and the calculation performance degree are improved, the hardware potential is fully excavated, and the method is suitable for edge devices with high requirements.

This application discloses a processing component, a chip, a board, a device, and a processing method for the processing component, relating to the field of chips. The processing component includes: a storage queue consisting of a first-level storage queue and a second-level storage queue, and an output unit. The first-level storage queue includes n entries, and the second-level storage queue includes m entries, where n is less than m. The first-level storage queue is used to perform a read operation based on a query instruction, obtain a first operation result, and send the first operation result to the second-level storage queue and the output unit. The second-level storage queue is used to perform a read operation based on the query instruction and the first operation result, obtain a second operation result, and send the second operation result to the output unit. The output unit is used to return a forward result to the loading pipeline based on the first operation result and the second operation result, wherein the forward result includes first data corresponding to the first operation result or second data corresponding to the second operation result.

The invention is suitable for the technical field of artificial intelligence, and relates to a storage controller, a storage system, computer equipment and a storage access method. The memory controller comprises a controller chip and a memory chip, the random access memory chip is bonded on the controller chip, the random access memory chip and the controller chip adopt the same address coding rule, and the random access memory chip comprises a first random access memory space used for storing a logic address mapping table; the second random access storage space is used for storing command queues corresponding to different storage channels, each storage channel is connected with at least one storage chip, and the command queues are used for caching operation commands issued by the controller chip to the storage chips; and the third random access storage space is used for storing read data returned by the storage chip in response to the operation command or storing write data required to be written by the storage chip in response to the operation command. According to the method, the strict requirements of a large-scale neural network model on high-bandwidth and low-delay storage access can be met.

A method for remote storage of node metadata partition, which binds independent logical acceleration pool for object storage device process based on mechanical hard disk to remotely store metadata. In the formatting stage, a globally unique identifier is generated, virtual block devices are created for database and log partition respectively, and acceleration pool is connected; continuous address space is divided into discrete storage objects according to preset object size, and a mapping relationship between logical offset and object and object internal offset is established; database label and log clipping record are written into corresponding objects of acceleration pool. When a write request is received, log entries are written into log storage objects according to the mapping, and after the memory table is flushed as a sorted string table, the database storage objects are written according to the mapping; when a read request is received, data is read from the acceleration pool according to the mapping relationship, and pre-reading cache is used for acceleration. The method can eliminate the single point failure risk of local high-speed storage medium, realize the pooling sharing and elastic expansion of storage resources, and guarantee the metadata access performance.

This invention discloses a GPU memory optimization method and system. By acquiring dynamic data flow information and intermediate data generation patterns of the task load, the real-time variation characteristics of the task load are obtained. Based on these characteristics, a gradient descent-based optimization algorithm is used to determine the memory pool allocation ratio and reserved space, resulting in an adjusted memory pool configuration. Available memory block information is extracted from the adjusted configuration, and a Huffman coding algorithm is used to compress low-access-frequency intermediate data, resulting in compressed intermediate data storage units. If the access frequency of the compressed intermediate data storage units is lower than a preset threshold, the compressed intermediate data storage units are temporarily stored in a low-speed storage area, and memory resources are reallocated according to task priority, resulting in an optimized memory allocation scheme. This invention significantly improves memory utilization, reduces access latency, and achieves efficient memory resource management.

The application provides a structured information layered digital content access management method, and relates to the technical field of data processing.The method comprises the following steps: step 1, scanning a media file directory, identifying an index file carrying a preset brand logo, extracting a storage path attribute and a logo visual feature of the index file, and obtaining an entry identification data set; step 2, based on the entry identification data set, combining a user permission level and a device display parameter, calculating a content level weight distribution value, and storing layered metadata containing the weight distribution value through a blockchain to obtain an initial content tree structure.The application realizes the accurate, safe and standardized management of digital content access through the whole-process structured layered management and the combination of the blockchain storage, and improves the efficiency of digital content management and the copyright protection strength.

Embodiments of the present disclosure relate to a cloud service access processing method and device, equipment and a storage medium. The method comprises: receiving, by a virtual switch, a cloud service access message for indicating access to a target cloud service having a target virtual network address, the target cloud service being deployed in a plurality of availability zones, and a target mapping relationship being maintained for the target cloud service, the target mapping relationship recording a physical network address of an availability zone in which the target cloud service is deployed, which is assigned to a source availability zone according to a geographical location proximity principle; determining, according to the target mapping relationship, a physical network address of an availability zone in which the target cloud service is deployed, which is assigned to an availability zone to which the virtual switch belongs, as a target physical network address; sending the cloud service access message to the availability zone corresponding to the target physical network address, and processing the cloud service access message by a server in which the target cloud service is deployed in the availability zone. It can be seen that the embodiments of the present disclosure can reduce the cloud service access delay and improve the access efficiency.

The present application belongs to the field of electric communication, and particularly relates to a CDN burst traffic coping method based on regional hotspot event sensing, comprising the following steps: obtaining original data of a hotspot event, extracting event semantic categories, social media propagation speed, initial user sentiment polarity and geographical user density distribution, and constructing a multi-dimensional event feature vector; inputting the multi-dimensional event feature vector as an initial state into a preset traffic time sequence generation adversarial network to obtain a content request probability distribution sequence of the hotspot event in a future time window; and according to the content request probability distribution sequence, when a predicted content request cumulative probability of a state-oriented long connection service is higher than a first preset threshold, instantiating a VNF service chain in a VM form. The present application can complete resource deployment and path pre-planning in advance, thereby reducing user access latency, guaranteeing service quality of the service, and improving overall utilization of network resources.

The invention provides a data transmission method and device, electronic equipment and a medium, and relates to the technical field of chips. Comprising the steps that a first descriptor in a buffer area is written into a descriptor storage area, a write pointer in a local register is updated, the write pointer indicates the position of the first descriptor in the descriptor storage area, and the first descriptor indicates storage information of data to be transmitted; and pushing the write pointer to a local mirror image register of the sending end to form a write pointer mirror image in the mirror image register, wherein the write pointer mirror image is used for the sending end to read the first descriptor from the descriptor storage area to obtain the to-be-transmitted data. According to the data transmission method provided by the invention, the mirror image register is locally maintained to store the pointer mirror image of the opposite end, and the pointer does not need to be acquired from the opposite end across a bus, so that the descriptor interaction rate is accelerated; software participation is not needed, complex software and hardware interaction is reduced, software overhead is effectively reduced, and the cross-domain interaction rate of the descriptors is improved.

This invention discloses a parallel processing system and method for CKKS fully homomorphic cryptography key switching. The system includes an NTT processing unit, a parallel modular reduction hardware unit, a base transformation parallel processing hardware unit, a point-value multiplication unit, and a control unit. The parallel modular reduction hardware unit contains L+1 parallel operation units, each including a shift-addition module, an accumulation module, and a Barrett modular reduction module. It utilizes a special form of small modulus property to convert multiplication into shift and addition operations, performing modular reduction of RNS base extension in parallel. The base transformation parallel processing hardware unit includes an inverse pre-computation module, a temporary matrix calculation module, a matrix multiplication module, and a storage unit. It accelerates base transformation through a parallel Barrett modular multiplication unit and a multiply-accumulate operation array. This invention decomposes large integer modular operations into multiple independent small modulus operations, avoiding carry chain delays and significantly accelerating key switching efficiency while saving hardware resources.

This application provides a chip-based JTAG system. The chip includes: a first JTAG interface forming a first JTAG chain, a first CPU core group, and a first JTAG-bus conversion unit; the first JTAG-bus also couples to at least one hardware resource within the chip that needs to be accessed by the first JTAG interface, the hardware resource not being linked to the first JTAG chain; the first JTAG interface accesses the first CPU core group and the first JTAG-bus conversion unit in a chained manner; the first JTAG-bus conversion unit, in response to recognizing a first access request received through the first JTAG link indicating access to the hardware resource, accesses the hardware resource, and sends the access result to the first JTAG interface through the first JTAG chain.

The application discloses a real-time data high-speed encryption method suitable for a high-speed network and belongs to the technical field of real-time data encryption. The method comprises the following steps: obtaining a high-speed network real-time data stream, segmenting the high-speed network real-time data stream to obtain high-speed network segments, extracting features to obtain behavior features of the high-speed network segments, calculating the behavior features by using a sliding incremental updating method to obtain behavior evolution labels of the high-speed network segments, constructing a key rotation trigger rule based on the behavior evolution labels and generating a trigger token, performing double-state parallel encryption on the high-speed network segments based on the trigger token to obtain high-speed network encrypted segments, performing consistent packaging on the high-speed network encrypted segments and generating a key identifier, decrypting the high-speed network encrypted segments based on the key identifier, and obtaining the high-speed network real-time data stream. The high-speed network encrypted segments are generated by double-state parallel encryption, and the encryption of the high-speed network real-time data stream is realized.

This invention relates to a data query method for a distributed database and a distributed database. The data query method includes: a computing node querying metadata information corresponding to a received query request; the computing node searching for data page information based on business information and regional information in the metadata information; the computing node determining the IP address corresponding to the data page information based on the correspondence between the data page information and IP addresses; the computing node sending the query request to the data node corresponding to the IP address; and the data node retrieving hot data corresponding to the query request from the data page corresponding to the IP address in its corresponding synchronization cache pool and returning it. This embodiment avoids retrieving hot data across shards or IPs, reducing the scale of distributed access, shortening access latency, and distributing concurrency pressure.

The invention is suitable for the technical field of artificial intelligence acceleration and storage calculation fusion, and provides a hybrid reasoning method of a target large model, and a model reasoning system and device.The method comprises the steps that a first operator set and a second operator set corresponding to a target reasoning task are obtained in response to a reasoning instruction sent by a second processor; performing reasoning operation on parameters corresponding to a first operator set in the parameter set by using an in-storage accelerator in the storage unit to obtain a first operation result of the first operator set; performing reasoning operation on parameters corresponding to a second operator set in the parameter set by using the first processor to obtain a second operation result of the second operator set; processing the first operation result and the second operation result to obtain a target reasoning result corresponding to the target reasoning task; and sending the target reasoning result to the second processor to instruct the second processor to determine the output content of the target large model according to the target reasoning result. According to the scheme, the model reasoning efficiency can be improved.

The invention relates to an HBF chip intelligent cache prefetching and replacement strategy method and system, and the method comprises the following steps: carrying out the access frequency statistics of cache prefetching data, obtaining a data access sequence table, and carrying out the time access analysis of the cache prefetching data based on the data access sequence table, and obtaining a data heat distribution diagram; performing priority ranking analysis on the cached prefetched data based on the data popularity distribution diagram to obtain a cache priority list; performing partition management on a cache space of the HBF chip based on the cache priority list to obtain a cache partition mapping table; according to the cache partition mapping table, replacement position selection is carried out on the data blocks newly entering the cache, so that preferential residence of the high-heat data blocks and directional replacement of the low-heat data blocks are achieved, and the technical problems that in the prior art, the cache hit rate is decreased, and bandwidth is wasted are solved.