35results about How to "Low latency" patented technology

The application provides an RGB-based self-adaptive translation flat display picture method and system. By writing the horizontal and pitching deviation into a memory, combining the layout characteristics of the flat display picture, and adjusting the position of the starting point of the distortion correction based on the FPGA, the self-adaptive compensation of the flat display part machining and assembly error is realized without increasing the operation amount and the delay, and the translation process correctness monitoring is performed. The application can be applied to the compensation of the machining and assembly error of the large field of view digital flat display, increases the margin of the flat display part machining and assembly, and further reduces the cost.

The invention discloses a method and a device based on Interlanceamp. The invention discloses an infrared detector driving imaging method in a Binning mode. According to the method, a pair of complete image data is generated, a detector needs to carry out integration operation twice, and effective data of different subframes can be generated after each time of integration is completed. Effective data generated by the first integration is a first sub-frame, and the sub-frame is all even-numbered lines of the complete image. Effective data generated after the second integration time is completed are second subframes, and the subframes are all odd-numbered lines of the complete image. According to the method, image data of a first sub-frame and image data of a second sub-frame output by an infrared detector are cached respectively, odd-even row sorting, time sequence recombination processing and the like are carried out on cached effective image data of the first sub-frame and the second sub-frame, and finally a complete image with the size of 640 * 512 is obtained. And the image is finally output through an image format of a camera link interface protocol.

This application relates to a 10G network underlying packet high-speed filtering and interception system and method based on FPGA architecture, including a client MAC module, set at the data link layer, for receiving raw data packets in Ethernet frame format sent by the physical layer, inserting a count value as the identity identifier of the raw data packet to obtain an extended data packet; a risk control module, set at the data link layer and associated with the transport layer, for generating detection results and matching the detection results with the corresponding identity identifier; a MAC parsing module, set at the data link layer and associated with the transport layer, for parsing the extended data packet and obtaining the packet length field of the TCP packet; a forwarding control module, set at the data link layer, for calculating the delay duration, sending the MAC frame containing the TCP packet after the delay duration ends, and determining whether the MAC frame containing the TCP packet has been modified; and a market-side MAC module, set at the data link layer, for receiving the extended data packets sent by the forwarding control module, realizing high-speed packet filtering and interception at the 10G network underlying layer.

The application belongs to the technical field of artificial intelligence, and discloses a question and answer identification method and device, electronic equipment and readable storage medium, the method comprises the following steps: receiving a question and answer request for a target question; based on the question and answer request for the target question, a pre-trained question and answer model is used to determine the answer corresponding to the target question; wherein the question and answer model is a student model obtained based on a second sample data set and a teacher model, and the teacher model is constructed based on a first sample data set and a transformer-based bidirectional encoding representation model. In this way, when question and answer identification is performed, the response speed of question answering can be improved and resource consumption can be reduced.

The application discloses a kind of positioning method and related equipment based on image, method includes: shooting environment, obtain the mark image for the positioning image of pre-set, wherein the positioning image includes DM code from inside to outside, circular mark and several mark blocks;Based on the circular mark, the mark image is carried out ellipse detection, and ellipse position information is obtained;According to the ellipse position information, the mark three-dimensional coordinates corresponding to the DM code are extracted;And, according to the ellipse position information, the block coordinate information corresponding to the mark block in the mark image is determined;According to the block coordinate information, the mark two-dimensional coordinates corresponding to the positioning image are calculated;According to the mark two-dimensional coordinates and the mark three-dimensional coordinates, the positioning information corresponding to the mark image is calculated.The application can significantly improve the speed and accuracy of positioning.

This invention relates to the field of data transmission technology, specifically to a performance optimization system and method for single-QP scenarios based on RDMA. The system includes an electrically connected HCA network interface card (NIC) and a host. The HCA NIC internally includes an electrically connected DB_PROC module, a WQE_PROC module, and a PKT_ENG module. The WQE_PROC module contains a WQE_CACHE cache space. The DB_PROC module obtains the scheduling request for the target QP. The WQE_PROC module queries the WQE_CACHE cache space to check if the target work queue element WQE corresponding to the target QP exists. If it exists, it reads it from the WQE_CACHE cache space; otherwise, it reads it from the host. This invention reduces the latency of reading WQE from the host, thereby improving bandwidth performance in single-QP scenarios and enhancing data processing efficiency.

The embodiment of the application discloses a kind of attention structure's compilation optimization method, device, equipment, medium and program, method includes: obtaining the attention event monitoring data generated by real-time monitoring of current running model by performance monitoring unit, and according to attention event monitoring data generation attention execution configuration file;Performance monitoring unit includes event sampling module, event sampling module includes a group of first register, each first register is used to record and store attention event monitoring data in real time;According to attention execution configuration file, the parallel optimization branch of current attention structure branch in current running model is generated;According to the branch flow data of the parallel optimization branch of current attention structure branch, the pre-fetching processing of current attention structure branch is carried out.The technical scheme of the embodiment of the application can improve the efficiency of instruction-level parallel and pipeline of attention structure, and then improve the hardware resource utilization rate of the execution of attention structure in model.

The application provides a data processing method for a multi-grain chip and the multi-grain chip, and relates to the chip technical field.The method comprises the following steps: firstly, in response to a computing core of a first grain, a memory access transaction is initiated to a target storage controller of a second grain, and a shared attribute identifier is determined.Then, when the shared attribute identifier indicates that the memory access data is non-shared data, a shunting processing procedure is executed: if it is a write transaction, write request data is split into a control packet and a first data packet, the control packet is sent to the target storage controller through a home agent node, and after a write response is received, the first data packet is sent to the target storage controller through a data path bypassing the home agent node; if it is a read transaction, read request data is sent to the target storage controller through the home agent node, and a second data packet returned by the target storage controller through a data path bypassing the home agent node and a read response returned through the home agent node are received.The scheme can reduce the serialization processing overhead of cross-grain memory access in the multi-grain chip.

Embodiments of the present application disclose a communication device, method, electronic equipment, storage medium and program. The communication device is integrated in a processor and is configured to receive a current instruction and determine an instruction type of the current instruction; in a case where the instruction type of the current instruction is determined to be a non-aligned instruction, send the current instruction to a lower module for a subsequent instruction processing flow; in a case where the instruction type of the current instruction is determined to be an aligned instruction, obtain an instruction execution result of a preceding target associated instruction of the current instruction, and in a case where the instruction execution results of the preceding target associated instruction of the current instruction are all determined to be execution completed, execute an aligned instruction processing flow of the current instruction. The technical scheme of the embodiments of the present application can efficiently ensure that the instructions are completed in order, reduce the delay of instruction in-order processing, and thus improve the overall communication performance.

This application provides an image filtering method, apparatus, device, storage medium, and program product, relating to the field of image processing technology. The method includes: shifting data in a filtering data buffer unit according to the filtering sliding direction of an image filtering unit, wherein the filtering data buffer unit and the image filtering unit are of the same size; updating the data in the filtering data buffer unit based on current pixel data and historical pixel data in the acquired image data stream; acquiring the updated data in the filtering data buffer unit; filtering the updated data in the filtering data buffer unit using the image filtering unit; and outputting the filtered image data. This application provides a technical solution that reads each pixel data in an image only once and can continuously perform image filtering processing.

The application discloses an intelligent ring, a hand posture recognition method and an interaction system.The intelligent ring comprises a ring body, a sensor module arranged on the surface of the ring body and an inertial measurement unit integrated in the interior of the ring body.The sensor module is arranged on the surface of the ring body, and when a user wears the intelligent ring, the hand posture can be recognized according to the data information fed back by the sensor module and the data information fed back by the inertial measurement unit, so that the data calculation amount in the inertial measurement unit is reduced, the power consumption of the intelligent ring is reduced, the system delay of the intelligent ring is reduced due to the reduction of the data calculation amount in the inertial measurement unit, the response rate of the intelligent ring is improved, and the robustness of the intelligent ring is improved.

The utility model provides an image splicing system and electronic equipment. The image splicing system comprises a plurality of cameras, wherein each camera comprises a synchronous input interface and a data output interface; the controller comprises a synchronous signal output circuit and a plurality of data receiving circuits, first ends of the plurality of data receiving circuits are connected with all the data output interfaces in a one-to-one correspondence manner, and the synchronous signal output circuit is connected to each synchronous input interface; the controller is used for outputting a synchronous signal to each synchronous input interface through the synchronous signal output circuit, so that all the cameras synchronously output image data through the data output interface, and the controller is also used for carrying out image splicing on the image data received by each data receiving circuit through the data output interface. According to the image splicing system provided by the invention, the equipment size can be effectively reduced, and image splicing with lower time delay can be realized.

This disclosure provides embodiments of a video encoding / decoding and display method, apparatus, electronic device, and computer-readable medium. One specific implementation of the method includes: splitting each video frame to be encoded to obtain a set of video frame blocks; determining a set of video frame block encoding channels that meet interrupt triggering conditions; performing key video frame block peak shifting processing on each video frame block to be encoded to obtain a set of key video frame encoding blocks and a set of channel delay encoding time differences; performing video encoding on each video frame block to be encoded to obtain a set of video frame block channel bitstreams; determining the decoding and splicing threads for the video frame block channel bitstream set to obtain a set of decoding and splicing threads; performing video frame block decoding and splicing on the video frame block channel bitstream set to obtain a decoded video; and performing video frame display processing on the decoded video. This implementation can improve the balance of the bitstream after video encoding, improve the stability and real-time performance of transmitted video, and reduce video transmission latency.

The invention relates to the technical field of radars, in particular to a radar and multi-camera combined perimeter security monitoring device and method, and the device comprises a radar module which is used for detecting a perimeter monitoring region and obtaining the target point cloud data of a target object; the visual camera module comprises a plurality of long-focus cameras which are connected in parallel, and the plurality of long-focus cameras are configured in a manner that field angles of the plurality of long-focus cameras are jointly spliced so as to cover a preset azimuth range of the perimeter monitoring area and output video data in the preset azimuth range; and the processing module is used for receiving the target point cloud data of the radar module and the video data of the visual camera module, and performing coordinate conversion and data fusion processing on the target point cloud data and the video data so as to realize real-time monitoring and identification of the target. According to the scheme, the time delay of the cameras can be reduced through splicing of multiple groups of long-focus cameras and combination of the radar, so that the monitoring efficiency of the perimeter area is improved.

This invention discloses a communication network rate control system and method based on multi-agent reinforcement learning. The system includes: a source node for sending data packets at a first transmission rate sent by a central server; multiple intermediate nodes for obtaining their own second transmission rate through a policy network based on received observations; and forwarding data packets according to the obtained second transmission rate; a central server for collecting observations and action values ​​from all nodes, learning a function network and a policy network based on these observations and action values, sending the learned policy network parameters to the intermediate nodes, and sending the first transmission rate to the source node. This invention centrally trains network parameters and distributes the learned parameters to the nodes, enabling inter-node collaboration and cooperation, improving network throughput and reducing network latency, thereby enhancing network performance. This invention can be widely applied in the field of wireless network congestion control.

The invention discloses a detection comparison circuit, a detection comparison method and an electronic device. The detection comparison circuit comprises an input clamping circuit used for receiving a first voltage and a reference voltage, and the input clamping circuit is configured to output the first voltage when a difference value between the first voltage and the reference voltage is smaller than a preset threshold value; when the difference value between the first voltage and the reference voltage is larger than a preset threshold value, second voltage is output, the second voltage is within a preset range, and the preset range is a voltage range comprising the reference voltage; and the comparison circuit is used for receiving the reference voltage and the first voltage or the second voltage and outputting a comparison result. According to the technical scheme, high-speed signal detection can be realized.

The application provides a control system of a converter, a pole control device and a valve control device, which comprises a pole control device layer, the pole control device layer comprises a pole control device, the pole control device comprises a pole control module, which is used for completing control and adjustment tasks of a direct current power transmission system and average voltage balance control of a converter bridge arm, converter bridge arm circulating current control and oscillation damping control; and a valve control function module is integrated in the pole control module and is used for collecting average voltage of the converter bridge arm and collecting device state information and fault / alarm state information. According to the technical scheme of the application, the device floor space is reduced, and the link delay is greatly reduced.

This disclosure provides a data synchronization method, a baseband unit, an electronic device, and a storage medium. The method includes: an auxiliary unit generating synchronization information and transmitting the synchronization information to a host unit via a synchronization interface; the host unit obtaining the synchronization information from the auxiliary unit via the synchronization interface; the host unit performing synchronization processing based on the synchronization information to synchronize the host unit with the auxiliary unit; the host unit generating a synchronization pointer based on the synchronization information; and the host unit sending baseband data based on the synchronization pointer. This method simplifies the processing procedure of the auxiliary unit and reduces the latency introduced during data processing between the baseband data and the auxiliary unit.

The invention discloses a task generation method, a task generation device, a processor and computer equipment, and relates to the technical field of processor circuits. The task generation method comprises the steps that in the process of packaging a first task, a second task with used resources meeting the resource requirement of the first task is inquired from all active tasks being executed; in response to the queried second task, pre-allocating a first resource meeting the requirement of the first task in the resources used by the second task to the first task before execution of the second task is completed; and under the condition that the second task is executed, issuing the first task to the task execution unit according to the first resource.

The application provides a cache system and method based on three-dimensional dynamic random access memory, which comprises a plurality of dies, each of which has a plurality of processor units; a three-dimensional dynamic random access memory, a cache controller and a direct memory access engine are arranged on the processor unit; on the same processor unit, the direct memory access engine is connected with the three-dimensional dynamic random access memory and the cache controller respectively; the direct memory access engines on different processor units are connected; the direct memory access engine receives a cache request, determines a data block of a victim cache line and a position of the data block; if the victim cache line is in a modified state, the data block is removed and written into a data buffer of the direct memory access engine; the data to be stored in the cache request is written into the position of the data block; the data block is written back to a global memory, and the cache operation is completed; the cache system structure is reliable and can simultaneously meet the requirements of large capacity and low latency.

This application discloses a method, apparatus, electronic device, and readable storage medium for real-time localization and map construction, belonging to the field of communication technology. The method includes: determining the initial pose information of the acquired i-th frame image based on the final pose information of the acquired (i-1)-th frame image, where i is an integer greater than 1; fusing the initial pose information of the i-th frame image with a first interpolation variable to obtain the final pose information of the i-th frame image, where the first interpolation variable is the last interpolation variable obtained before acquiring the i-th frame image, and is an interpolation variable between the initial pose information of the first image and the target pose information; the first image is a keyframe image among the images acquired before the i-th frame image, and the target pose information is the pose information optimized from the initial pose information of the first image; and performing real-time localization and map construction based on the final pose information of the i-th frame image and the i-th frame image.

The application discloses a high-speed low-power approximate multiply-accumulate operator for image convolution processing, which processes 8bit signed number*8bit unsigned number. The multiply-accumulate operator is composed of a multiplier and an adder, and is divided into four stages of partial product generation, partial product compression, carry addition and accumulation. In the partial product generation stage, an approximate base-8 Booth algorithm is used, and in the carry addition and accumulation stages, an approximate 4-carry adder is used. The multiplier of ±3 times is approximated to ±2, and the multiplier of ±4 times. Due to the delay of the shift operation, the power consumption is small. Through the approximation, the complexity of the circuit can be reduced, the speed can be improved, and the power consumption can be reduced. For nbit addition operation, n-1bit carry is required; for 16bit addition operation, 4bit carry is used, the delay is reduced, and the calculation speed is improved. Through approximate calculation, the speed of the multiply-accumulate operator is improved, the power consumption is reduced, and the image convolution processing with high speed, low power consumption and certain error tolerance is suitable.

The invention provides a semiconductor device, a manufacturing method thereof and a memory system. The semiconductor device comprises a first semiconductor structure with a peripheral circuit, wherein the first semiconductor structure comprises a substrate, a first dielectric stack layer, a second dielectric stack layer and a conductive column; wherein the substrate is provided with a first surface and a second surface which are oppositely arranged, and a first device structure is formed on the first surface; the first dielectric stack layer is located on the first surface, an interconnection structure is arranged in the first dielectric stack layer, and the first dielectric stack layer is located on the side, away from the substrate, of the first device structure and connected with the first device structure; the second dielectric stack layer is located on the second surface, and a first bonding pad structure is arranged in the second dielectric stack layer and is exposed on the surface, away from the substrate, of the second dielectric stack layer; the conductive pillar extends in a direction perpendicular to the first face and penetrates through the substrate, one end of the conductive pillar extends to the first dielectric stack layer and is connected to the interconnection structure, and the other end of the conductive pillar extends to the second dielectric stack layer and is connected to the first pad structure.

The application discloses a data synchronization method and device, a data synchronization system. The method comprises the following steps: reading a database log by using a database pipeline process, wherein the log is used for recording the dependency relationship of data in the database, and is used for recording the query statement information of the update in the database, and the dependency relationship is used for indicating the flow direction of the data in the database; analyzing the log to obtain the flow direction of the data in the database, and generating a directed acyclic graph according to the flow direction of the data; storing the data in the database in a message middleware indicated by the directed acyclic graph, and synchronizing the data in the database and the message middleware. The application solves the technical problem of long delay time of data synchronization caused by real-time access to the database for data synchronization.

The application provides a data read-write method, a data reading method, a three-dimensional memory and an electronic device. The data read-write method comprises the following steps: a logic chip determines first write data; the logic chip compresses the first write data according to sample data to obtain a redundancy code; the bit difference between the first write data and the sample data is within a preset range; the redundancy code and the storage address of the sample data are stored in a redundancy storage area of a storage chip; and the logic chip and the storage chip are three-dimensionally integrated. The method of the application can realize high compression rate, reduce the delay of memory access data, and reduce the power consumption of a CPU. In addition, when the capacity of the cache area is insufficient, the method of the application can transfer at least part of the data, expand the storage capacity, and reduce the CPU overhead.

An imaging device (100) includes a plurality of pixels (110) arranged in a matrix, each of the plurality of pixels (110) including a photoelectric conversion section (1) that converts light into signal charge and a charge accumulation section (FD) that accumulates the signal charge, and a control circuit that causes, until a trigger signal for instructing start of exposure is accepted, pixels belonging to at least one row among the plurality of pixels (110) to sequentially perform, in units of rows or in units of multiple rows, a reset operation that initializes a potential of the charge accumulation section (FD), and that, after the trigger signal is accepted, causes the plurality of pixels (110) to simultaneously perform an exposure operation that accumulates the signal charge to the charge accumulation section (FD) without causing the pixels belonging to at least one row among the plurality of pixels (110) to perform the reset operation.

The application provides a message information processing method, an acceleration processing unit and a computer storage medium. The method comprises the following steps: querying a message scheduling table based on each field of a serial transmission message to obtain a first table lookup result corresponding to the field, wherein the message scheduling table indicates a mapping relationship between each field of the message and an identifier of each parallel processing queue; analyzing each field of the message and judging whether the field is a preset index field; screening the preset index field and outputting, to a storage unit, a parallel processing queue identifier indicated by the first table lookup result of the preset index field and associated with the message, wherein the identifier of the parallel processing queue in which the message is located corresponds to an access address of the message in the storage unit. The method can improve the speed of table lookup on the message and reduce the delay.

The application relates to a storage device, a storage system and a write method of the storage device. The storage device comprises a front-end module, a back-end module, a cache module, a storage medium and a processor. The cache module is connected with the front-end module, the processor and the back-end module, the back-end module is connected with the processor and the storage medium, the cache module comprises a cache management unit, a first cache and a second cache, the capacity of the second cache is greater than or equal to that of the first cache, and the read-write speed of the second cache is less than that of the first cache. The front-end module transmits to-be-written data to the first cache. The cache management unit controls mutual transfer of the to-be-written data between the first cache and the second cache. The back-end module writes target to-be-written data into the storage medium through the first cache. The application uses the first cache with high read-write speed and the front-end module and the back-end module to form a write channel, the delay is small, the second cache with large capacity and the first cache are used to mutually transfer data to increase cache data, and the write performance is effectively improved.

The embodiment of the invention discloses a communication device and method, electronic equipment, a storage medium and a program, and the communication device is integrated in a processor, and is used for receiving a current instruction, and determining the instruction type of the current instruction; when it is determined that the instruction type of the current instruction is a non-aligned instruction, the current instruction is sent to a subordinate module for a subsequent instruction processing flow; under the condition that the instruction type of the current instruction is determined to be an alignment instruction, obtaining an instruction execution result of a preorder target associated instruction of the current instruction, and under the condition that the instruction execution result of the preorder target associated instruction of the current instruction is determined to be execution completion, executing the current instruction; and executing an alignment instruction processing flow of the current instruction. According to the technical scheme, it can be efficiently guaranteed that the instructions are completed in sequence, the time delay of instruction order-preserving processing is shortened, and then the overall communication performance is improved.

The application relates to the technical field of intelligent manufacturing, and discloses a kind of automobile disassembly production line multi-device linkage intelligent scheduling method and system.The method comprises the following steps: obtaining multi-source operation data to obtain equipment load distribution matrix and material flow vector; according to the equipment load distribution matrix and the material flow vector, a particle swarm algorithm is used to obtain a task scheduling priority matrix and determine a linkage bottleneck area; a deep reinforcement learning model is used to output a task allocation scheme in a virtual simulation environment; according to the task allocation scheme, determine the congestion area and generate the path correction vector; schedule available alternative equipment to perform load transfer to obtain load adjustment parameters; calculate the progress deviation vector according to the load adjustment parameters and update the operation parameters of multi-device cooperation. This method can solve the cascading imbalance problem caused by the difference in the capabilities of heterogeneous devices in the disassembly line.