382 results about "Peripheral" patented technology

The invention discloses a FeFET-based XNOR calculation unit, an array and a working method of the FeFET-based XNOR calculation unit. The unit comprises a FeFET transistor F1, a FeFET transistor F2 and an NMOS transistor M0. The source electrode of the F1 is connected to a bit line BL, the source electrode of the F2 is connected to a bit line BLB, the grid electrode of the F2 and the grid electrode of the F1 are jointly connected to a word line WL, and the drain electrode of the F2 and the drain electrode of the F1 are jointly connected to a node X. The grid electrode of the M0 is connected with the node X, the drain electrode is grounded, and the source electrode is connected to the shared charge line Scl. F1 and F2 are configured to store a weight bit, and by applying a read voltage to WL and applying a voltage corresponding to an input bit to BL and BLB, a voltage level of Scl outputs an XNOR logic calculation result. The array includes a plurality of XNOR computing units arranged in m rows * n columns. WL and Scl ends of each unit are shared in each column, and BL and BLB are shared in each row. According to the invention, the control peripheral circuit of the array word line is simplified, the variability of current is effectively avoided, and the problems of hardware overhead and the like are effectively solved.

An improved electronic wager-based gaming machine (EGM) is disclosed. The EGM supports multiple concurrent players and maintains a plurality of distinct virtual meters, each exclusively associated with a distinct, concurrent game session on a single EGM. The server processes financial transactions, such as deposits and withdrawals using the EGM's cash handling peripherals, against a specific virtual meter and a corresponding player's casino account, which is maintained separate from the EGM's operational funds. This enables the EGM to act as a financial terminal for the player's account. Concurrently, data derived from the virtual meters is transformed and aggregated into a single, unified regulatory meter for compliance reporting, which is distinct from the virtual meters. The EGM provides a shared multiplayer interactive control interface to solve the technical problem of supporting multiple, independent player sessions concurrently on a single EGM.

The invention relates to a method for deploying a spiking neural network to a hardware device. The method includes providing the spiking neural network, training the spiking neural network to obtain a trained spiking neural network, mapping neurons and synapses in the trained spiking neural network to corresponding components of the hardware device, simulating deployment of the trained spiking neural network on a hardware device using the obtained mapping, and deploying the trained spiking neural network to the hardware device using the mapping and the simulation. The training, mapping, simulation and deployment steps are executed by using hardware information of the hardware device; wherein the hardware information comprises at least one of hardware resource constraints, hardware connection constraints, dynamic range of hardware design parameters, characterization or statistics of neurons and synapses, reconfigurability, programmability, yield, computing resources, temporal characteristics, constraints on pre-processing, interfaces and peripheral devices, and available encoders and / or decoders.

The invention provides a quick start and security verification method and equipment for an embedded device, a medium and a program product, in the method, firmware is divided into a core start module and a non-core function module in advance, and the core start module and the non-core function module are respectively stored in a high-speed access area and a common storage area of a nonvolatile memory; after the embedded device is powered on, initialization of the key peripheral is completed; when firmware is started or updated for the first time, security verification based on a digital signature is executed on the core starting module, if verification is passed, a mirror image of the core starting module is written into a running cache partition of the nonvolatile memory, and an integrity label is generated; in the subsequent starting process, the mirror image is loaded from the running cache partition, and the integrity label is used for executing rapid verification; after loading of the core starting module is completed, the non-core function module is loaded, and lightweight check is executed. According to the method, the security of the core module is ensured, the performance and security requirements of the non-core module are considered, and the calculation and storage overhead is reduced.

The embodiment of the invention provides a chip, a control method and equipment, the chip comprises an event triggering unit and a plurality of peripherals, the event triggering unit is connected with the peripherals, and to-be-executed events of the peripherals have a set execution sequence. The event triggering unit is used for receiving a state synchronization signal sent by the execution peripheral of the previous event, and the state synchronization signal is sent by the execution peripheral of the previous event after the event execution state of the execution peripheral of the previous event meets a preset condition. The event triggering unit is further used for responding to a state synchronization signal sent by the execution peripheral of the previous event and sending an event triggering signal to the execution peripheral of the later event, and the event triggering signal is used for triggering the execution peripheral of the later event to execute the later event. Through the above technical scheme, the event triggering of the peripheral can be realized based on a hardware mode, the processor does not need to participate, the real-time performance is higher, and the resource consumption of the processor is reduced.

The invention relates to the technical field of embedded system development and verification, and discloses an embedded software full-digital excitation deployment method, system, device and medium, and the method comprises the steps: based on a virtualization modeling technology of a multi-core heterogeneous system, simulating a CPU architecture, an operating system, board card peripherals and peripheral interfaces of a target processor, constructing a general digital target machine; a cross-platform communication framework is established based on a real-time communication transmission technology of direct digital frequency synthesis, and real-time synchronization of data of a virtual environment and an interaction object is completed; and through cooperation of the general digital target machine and the cross-platform communication framework, full-digital deployment and verification of the embedded software are completed. According to the method, full-digital development and verification of the embedded software can be realized, a research and development mode of parallel hardware development, software development and system function verification is met, and the research and development efficiency of the embedded software is improved.

The invention belongs to the technical field of robot communication interaction, and relates to an equipment capability self-description and negotiation method and device, an upper computer and a storage medium. The peripheral equipment is powered on to issue an equipment access instruction, so that the upper computer obtains the types and the number of the peripherals in the system in real time; state and capability information is obtained based on a unified standard frame, operation parameters and controllable range structuring are achieved, and a basis is provided for unified control; a control instruction template is automatically generated according to the information, multiple sets of adaptive logics are not needed, cross-device instruction and strategy multiplexing is supported, and the extension and operation and maintenance cost is reduced; the target execution instruction is issued through the preset verification strategy, problems can be found in advance when parameters cross boundaries or condition conflicts occur, wrong execution is avoided, the system stability is improved, peripheral automatic identification, capability unified expression, instruction template automatic generation and safe execution are achieved, and the compatibility and reliability of a robot system in a multi-device environment are enhanced.

A device connectable between a host computer and a computer peripheral over a standard bus interface is disclosed, used to improve security, and to detect and prevent malware operation. Messages passing between the host computer and the computer peripherals are intercepted and analyzed based on pre-configured criteria, and legitimate messages transparently pass through the device, while suspected messages are blocked. The device communicates with the host computer and the computer peripheral using proprietary or industry standard protocol or bus, which may be based on a point-to-point serial communication such as USB or SATA. The messages may be stored in the device for future analysis, and may be blocked based on current or past analysis of the messages. The device may serve as a VPN client and securely communicate with a VPN server using the host Internet connection.

Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.

The invention provides a low-power-consumption management method for cloud computer equipment. The method comprises the following steps: monitoring a user operation behavior and a system running state in real time through a client; generating a hierarchical dormancy decision based on the user operation behavior and the system operation state; when the hierarchical dormancy decision meets a preset first dormancy threshold value, the system is controlled to enter a first dormancy state, and the first dormancy state comprises closing non-core peripherals and keeping internal memory power supply and network connection; in the first dormancy state, when the hierarchical dormancy decision meets a preset second dormancy threshold value, the system is controlled to enter a second dormancy state, and the second dormancy state comprises the steps that all the application sub-processes and the system service process store data and exit, all the peripheral modules enter the dormancy state, and main power supply of all the peripheral modules is powered off. The problems that an existing low-power-consumption management method for the cloud computer equipment is single in dormancy condition, cannot adapt to complex use scenes and is prone to causing task interruption or mistaken dormancy are solved.

The invention relates to the technical field of intelligent peripherals, in particular to a user-oriented interaction information expansion method, which comprises the following steps that: each keycap acquires displacement and pressure, generates an event packet, uploads the event packet through an optical wireless link, and obtains a clock and supplies power; constructing a keycap graph by a master controller, obtaining an intention vector through graph convolution and pooling, inputting the intention vector into a cyclic network to generate a pixel matrix and a phase matrix, and downlink after Bernoulli sparse coding; performing key cap side orthogonal matching pursuit decoding and four-round gradient optimization, and outputting a differential pixel set, a differential phase set and a synchronization mark; the master control refreshes the digital micromirror array and the ultrasonic phased array in a differential manner, locks a frame-level time sequence through a synchronization pulse, compensates link delay and hardware drift in real time based on Kalman filtering, and keeps an optical-acoustic alignment error to be less than 100 microseconds; degradation monitoring enables a link to be automatically switched to a pre-carved character layer and to be quickly recovered when the link is abnormal, and a keyboard interaction information expansion scheme with low delay and high consistency is provided.

An electronic device includes a slave interface configured for coupling to a machine controller of a machine via a multi-drop bus (MDB), a host interface configured for coupling to a first peripheral device of the machine, and memory storing one or more programs to be executed by the one or more processors and comprising instructions for: registering the electronic device as a slave to the machine controller, registering the first peripheral device as a slave to the electronic device, receiving from a mobile device a request to access signals generated by the first peripheral device, validating the request, and sending a reset command to the first peripheral device via the host interface, the reset command including a directive to update a signal destination address of the first peripheral device from a controller address of the machine controller to a device address of the electronic device.

The embodiment of the invention provides a memory which at least comprises a first memory area, a peripheral circuit area and a second memory area which are arranged in the first direction, the peripheral circuit area is located between the first memory area and the second memory area, the first memory area is provided with a plurality of repetitive units in the second direction, and the repetitive units are arranged in the second direction. Each repeating unit is composed of at least two storage banks arranged in the first direction; wherein the first direction is perpendicular to the second direction.

Providing processor core fault recovery without requiring system resets in multicore processor-based devices is disclosed herein. In some aspects, a processor-based device provides a plurality of processor cores that comprise a first processor core and a second processor core, with the first processor core configured to operate as a bootstrap processor core (BSP). The first processor core is configured to receive an interrupt corresponding to a registered timer event from a timer peripheral circuit, and, responsive to receiving the interrupt, transmit an interprocess interrupt (IPI) to the second processor core. The first processor core then determines whether a status update was successfully received from the second processor core in response to the IPI. If not, the first processor core performs one or more migration operations on the second processor core, masks the second processor core as offline for scheduling purposes, and blocks the second processor core from further health monitoring.

The invention discloses a low-cost satellite-borne core circuit, an operation method and an electronic device, and belongs to the field of satellite communication circuit design, the low-cost satellite-borne core circuit comprises an embedded MCU, a peripheral circuit and embedded MCU software, the peripheral circuit is connected with the embedded MCU, and the embedded MCU software is loaded and operated by the MCU. According to the invention, based on a new generation of vehicle-gauge-level embedded MCU and peripheral components, the cost of components applied to low-orbit satellite-borne products is greatly reduced; according to the circuit design, multiple redundancy reinforcement technical means such as MCU processor redundancy backup, external interface circuit redundancy backup, software program storage redundancy backup and software triple modular redundancy reinforcement are adopted, and the operation reliability of a core circuit in a low-orbit satellite-borne environment is ensured.

A system and method of software control and autonomy of a disinfection module for an autonomous or semi-autonomous cleaning device. The disinfection module control software resides on a computer with processor and memory. The disinfection module is connected to peripherals for sensing and localizing in the environment and controlling the actuators for the motion of the cleaning device. The disinfection module control software processes the sprayer's status, follows and plans paths to move the cleaning device to the spray targets, generates appropriate motion commands, and controls the disinfection module's pump, fan, LED, and electrostatic generator states.

The invention relates to the technical field of computer hardware, and provides a peripheral starting control method, circuit and device, a medium and a program product, and the method comprises the steps: monitoring a power state signal and a received external reset signal; when it is monitored that the power state signal is in a stable state, generating an internal reset control signal for indicating reset release; and controlling the internal hardware logic circuit to release the reset according to an internal reset control signal for indicating the release of the reset so as to trigger the internal hardware logic circuit to execute an initialization starting operation before the external reset signal is released from the reset. Before the external reset signal is released, the stable state of the power supply state signal is utilized to trigger the initialization starting of the internal hardware logic circuit in advance, so that the starting moment of the external internal core logic and the releasing moment of the external reset signal are decoupled; and sufficient time is reserved for the initialization operation which consumes long time by starting in advance, so that the peripheral starting reliability is improved.

The invention discloses a communication debugging method and device, electronic equipment and a storage medium, and relates to the technical field of communication, and the method comprises the steps: integrating a to-be-tested design and a transaction processor to a top layer module of a simulation environment, and mapping the top layer module to a hardware acceleration simulation platform; a simulation database corresponding to the top layer module is generated on the hardware acceleration simulation platform; loading the simulation database to a hardware acceleration simulation platform, and starting a runtime environment; calling an application program interface provided by the transaction processor through the test code to set communication parameters; starting simulation to realize communication debugging between the to-be-tested design and the transaction processor; wherein the transaction processor is used for realizing a communication link in a virtualization mode. According to the method and the device, the dependence on physical peripherals is eliminated, and efficient and flexible communication debugging is realized on the premise that actual hardware connection is not needed.

A base mechanism is adapted for a function module and an device main part and includes a mount and a connecting component, the mount is partially disposed in the device main part, the connecting component is connected to the function module and movably disposed on the mount, and the function module is movable with respect to the mount via the connecting component.

The invention is suitable for the technical field of computer system starting, and provides an OpenSBI starting method and system of an RISC-V SoC based on an FPGA, the system comprises a hardware abstraction layer, a boot loading layer, a privilege management layer and a kernel execution layer, and each layer realizes data interaction and process connection through a standardized interface; through the hierarchical design of FPGA hardware initialization, SPL / U-Boot firmware loading, OpenSBI privileged mode configuration and kernel startup, modular management of a startup process is realized, the system coupling degree is reduced, multiple storage medium and operating system types are supported, hardware abstraction is realized through an OpenSBI standard interface, subsequent extension of new peripherals or upgrading of an RISC-V architecture version is facilitated, and the development of the RISC-V architecture is facilitated. The standardized starting process reduces the adaptation workload of hardware and firmware, and debugging and rapid iterative development are facilitated.

The invention relates to the technical field of HID peripheral connection, in particular to a switching control method and device for HID peripherals among different system devices, equipment and a storage medium, and the method comprises the steps: virtualizing the HID peripherals as virtual nodes in main control system equipment; establishing a communication route between the virtual node and other preset system equipment; wherein the main control system equipment is in communication connection with the other system equipment, and a first equipment system carried by the main control system equipment is different from a second equipment system carried by the other system equipment. According to the method and the device, when the HID is externally arranged among different system devices for switching, the hardware cost is prevented, and the switching efficiency is improved.

The invention discloses computer peripheral interface management and control equipment based on fingerprint identification. The computer peripheral interface management and control equipment comprises an FPGA main controller, a fingerprint identification module, a user interaction module, a peripheral interface output module, a host interface input module and a power management module, in the working process, the fingerprint identification module compares user fingerprint information, confirms the identity and notifies the FPGA main controller, a USB input interface and an HDMI input interface of the host interface input module are connected with a USB output interface, an HDMI output interface and a VGA output interface of the peripheral interface output module, and a user is notified through a state indicator lamp of the user interaction module; and when the user leaves, a locking key of the user interaction module is clicked, and after receiving a locking key signal, the FPGA main controller cuts off USB (Universal Serial Bus) and HDMI (High-Definition Multimedia Interface) input interfaces of the host interface input module and USB, HDMI and VGA (Video Graphics Array) output interfaces of the peripheral interface output module, and notifies the user through a state indicator lamp of the user interaction module. External connection of the computer peripheral interface can be cut off through one key, and attack of a hardware layer can be defended.

The present application relates to the technical field of computer data processing, and especially relates to an intelligent agent system for automatically identifying, downloading and installing self-controllable peripherals, which comprises a device information acquisition module for collecting data to generate hardware identification data; a driver compatibility determination module for comparing a pre-stored self-controllable peripheral list to match a driver resource to generate a resource identification; a secure downloading module for establishing an encrypted connection to download a driver file, storing the driver file in an isolated sandbox after hash verification and digital certificate verification; a driver migration module for simulating a system call environment through an operating system compatibility layer in the driver migration module, and converting a driver instruction into a host system instruction by using a user-level binary translator in the driver migration module; and an automatic installation module for calling a system interface to deploy the driver and verifying an installation state. The present application realizes closed-loop automatic processing from identification to installation of a peripheral driver, and solves the problem of compatibility between a Linux system and a Windows driver.

To provide a mechanism capable of preventing an expiration date exceeding a compromise period of an algorithm used for issuance processing of an electronic certificate from being set as the expiration date of the electronic certificate.SOLUTION: The multifunction peripheral 101 generates a public key pair. Further, the multifunction peripheral 101 generates, in accordance with an instruction by the user, an issuance request for an electronic certificate for certifying the validity of the multifunction peripheral 101, which is an issuance request including a certificate signing request generated based on the public key in the public key pair. The multifunction peripheral 101 performs control for preventing an expiration date exceeding the compromise time of the algorithm used for the issuance processing of the electronic certificate from being included in the issuance request for the electronic certificate as the expiration date of the electronic certificate.SELECTED DRAWING: Figure 3

The invention belongs to the field of computer system compatibility and peripheral interfaces, and relates to a domestic desktop terminal peripheral compatibility method and system based on protocol reverse mapping and a computer readable storage medium. According to the method, after peripheral access, three-layer analysis of physical layer signal reversal, data link layer structure reversal and application layer semantic reversal is carried out in sequence, and an equipment interface type, a frame structure and instruction semantics are dynamically identified. And based on the reverse result, dividing the equipment into a standard protocol or a private protocol through a protocol type decision, respectively routing the protocol to a drive straight-through module or an instruction translation executor for processing, and finally providing compatible services for a domestic service system through a unified virtual equipment interface. According to the method, the adaptation problem of a document-free private protocol is solved, plug and play of a Wintel peripheral by a non-x86 architecture domestic terminal is achieved, the protocol compatibility coverage rate is remarkably increased, meanwhile, the CPU occupancy rate is reduced, and the harsh requirement for millisecond response of specific industries such as electric power is met.

The invention provides a connecting device for cooperative work of double computers. The connecting device comprises a first USB interface expansion module, a video acquisition module, a USB keyboard and mouse protocol conversion module and a second USB interface expansion module. A first external USB interface of the first USB interface expansion module is connected with an external master control computer, an HDMI output interface of the first USB interface expansion module is connected with an external display, and a first internal data interface and a second internal data interface of the first USB interface expansion module are respectively connected with an output end of the video acquisition module and an input end of the USB keyboard and mouse protocol conversion module. A second external USB interface of the second USB interface expansion module is connected with an external controlled computer, and a third internal data part interface and a fourth internal data part interface of the second USB interface expansion module are respectively connected with the input end of the video acquisition module and the output end of the USB keyboard and mouse protocol conversion module. According to the invention, a network is not needed, a controlled computer does not need software, a display and a keyboard and a mouse of one computer can be used as peripheral equipment of the other computer, fusion display and seamless operation of images of the two computers are realized, and the working efficiency and the safety are effectively improved.

Systems, devices, methods, and circuits for managing failures of in-memory computing (IMC) devices. An example memory device includes: a plurality of memory units and a circuitry configured for execution of a computing instruction in one or more memory units. A memory unit includes: a memory cell array and a peripheral circuit including a plurality of subcircuits coupled to the memory cell array. Each subcircuit includes: one or more internal sense amplifiers, one or more latches, and one or more multipliers. The circuitry is configured to: determine whether a subcircuit is defective by determining whether at least one of an internal sense amplifier, a latch, or a multiplier in the subcircuit is defective using an external sense amplifier external to the memory unit, and in response to determining that the subcircuit is defective, perform one or more corresponding actions including replacing the subcircuit with a redundant subcircuit in the peripheral circuit.

The invention provides a DMA controller unified management scheduling system and a use method thereof, and relates to the technical field of computers, the system comprises a DMA controller management scheduling module and a DMA controller driving module, the system is used for unified management scheduling and adapting to different DMA controllers, a unified operation interface is provided for a user to use a DMA channel to carry out data transmission, and the DMA controller driving module is used for driving the DMA controllers to carry out data transmission. Unified descriptors and transitions between the unified descriptors and DMA controller custom descriptors are provided for different DMA controllers. By using the system, the difference of the DMA controller arranged at the bottom layer of the system can be shielded for the user application, the decoupling of the user application and the specific DMA controller is realized, and the development difficulty of the user application and the hardware upgrading and maintenance cost are reduced.

This invention relates to the field of artificial intelligence application technology, specifically to a method and system for automatically delivering AI-generated content to a target computer application, comprising the following steps: S100, responding to a natural language command input by a user on a first terminal, acquiring target text content generated by a large language model, and providing editing and confirmation operations for the target text content in the interactive interface of the first terminal; This invention constructs an end-to-end delivery solution from AI content generation to automatic filling of target applications by organically integrating a large language model, computer vision positioning, and underlying USBHID device simulation technology. This solution relies on a hardware bridging module as a standard peripheral to access the target computer, achieving high compatibility across operating systems without the need to install any customized software or drivers, and ensuring the system security of the target device.

This invention discloses a multi-dimensional dynamic peripheral security verification method and system for the boot phase of wireless communication devices, belonging to the field of embedded system security technology. The method is executed after the second stage of the U-Boot boot process of the wireless communication device and before jumping to the operating system kernel. It includes: triggering a security verification process and reading a trusted peripheral whitelist, where each entry contains the peripheral's fingerprint information; collecting fingerprint information for the peripheral to be verified using a differentiated method based on its interface type, comparing it with the whitelist entries, and performing a logical consistency check for USB interface peripherals; and determining the peripheral's risk level and executing corresponding security response actions based on a comprehensive assessment of firmware hash consistency, timing feature deviation, and logical consistency check results. By integrating multi-dimensional dynamic fingerprint verification, this invention enables deep security verification of peripherals during the embedded boot phase, effectively preventing identifier forgery and firmware tampering, and improving device boot security.