646 results about "Peripheral" patented technology

The invention discloses a FeFET-based XNOR calculation unit, an array and a working method of the FeFET-based XNOR calculation unit. The unit comprises a FeFET transistor F1, a FeFET transistor F2 and an NMOS transistor M0. The source electrode of the F1 is connected to a bit line BL, the source electrode of the F2 is connected to a bit line BLB, the grid electrode of the F2 and the grid electrode of the F1 are jointly connected to a word line WL, and the drain electrode of the F2 and the drain electrode of the F1 are jointly connected to a node X. The grid electrode of the M0 is connected with the node X, the drain electrode is grounded, and the source electrode is connected to the shared charge line Scl. F1 and F2 are configured to store a weight bit, and by applying a read voltage to WL and applying a voltage corresponding to an input bit to BL and BLB, a voltage level of Scl outputs an XNOR logic calculation result. The array includes a plurality of XNOR computing units arranged in m rows * n columns. WL and Scl ends of each unit are shared in each column, and BL and BLB are shared in each row. According to the invention, the control peripheral circuit of the array word line is simplified, the variability of current is effectively avoided, and the problems of hardware overhead and the like are effectively solved.

Disclosed are a method and apparatus for identifying peripheral configuration of server, a method and apparatus for laying out peripheral silkscreen, and a server. The method includes: determining a PCIE external interface of each central processing unit on the basis of configuration requirement information of a server to be identified; determining, in sequence according to a level state of each peripheral ID signal transmitted by each PCIE external interface, a peripheral type that is capable of being configured for a peripheral bandwidth corresponding to the peripheral ID signal, allocating corresponding serial numbers to peripherals of different peripheral types, generating a peripheral silkscreen including all peripheral sequences managed by the server to be identified; sending the peripheral silkscreen to a basic input output system and / or a baseboard management controller, and allowing the basic input output system and / or the baseboard management controller to unify respective default silkscreen into the peripheral silkscreen.

An improved electronic wager-based gaming machine (EGM) is disclosed. The EGM supports multiple concurrent players and maintains a plurality of distinct virtual meters, each exclusively associated with a distinct, concurrent game session on a single EGM. The server processes financial transactions, such as deposits and withdrawals using the EGM's cash handling peripherals, against a specific virtual meter and a corresponding player's casino account, which is maintained separate from the EGM's operational funds. This enables the EGM to act as a financial terminal for the player's account. Concurrently, data derived from the virtual meters is transformed and aggregated into a single, unified regulatory meter for compliance reporting, which is distinct from the virtual meters. The EGM provides a shared multiplayer interactive control interface to solve the technical problem of supporting multiple, independent player sessions concurrently on a single EGM.

An electronic device detects that alert criteria have been met for a charging case, wherein the charging case is a charging case for a peripheral that is paired with the electronic device; and the alert criteria are based on the charging case having a battery charge level that is below a first threshold. In response to detecting that the alert criteria have been met, the electronic device displays a first alert that indicates that the battery charge level of the charging case for the peripheral is below the first threshold.

Techniques and apparatuses are described that implement software-defined hardware. In example aspects, a hardware manager can enable and disable different combinations of peripherals coupled to a host device. Software can be executed on different enabled combinations of peripherals to determine which combinations best meet the requirements of a product. Combinations of peripherals can be updated with alternative or new peripherals that have new features or replace obsolete peripherals. Thus, the hardware manager can provide a modular validation platform that allows a manufacturer of electronic devices to skip a prototype phase, qualify new peripherals as replacements for existing peripherals that may become obsolete, and iterate between different combinations of peripherals to determine ideal combinations. The disclosed techniques and systems can therefore reduce resources, time, and costs associated with design and testing phases of electronic devices.

The invention relates to a method for deploying a spiking neural network to a hardware device. The method includes providing the spiking neural network, training the spiking neural network to obtain a trained spiking neural network, mapping neurons and synapses in the trained spiking neural network to corresponding components of the hardware device, simulating deployment of the trained spiking neural network on a hardware device using the obtained mapping, and deploying the trained spiking neural network to the hardware device using the mapping and the simulation. The training, mapping, simulation and deployment steps are executed by using hardware information of the hardware device; wherein the hardware information comprises at least one of hardware resource constraints, hardware connection constraints, dynamic range of hardware design parameters, characterization or statistics of neurons and synapses, reconfigurability, programmability, yield, computing resources, temporal characteristics, constraints on pre-processing, interfaces and peripheral devices, and available encoders and / or decoders.

According to the equipment authorization method and device, the storage medium and the computer equipment provided by the invention, when the equipment is authorized, the authorization permission service is started after the equipment authorization file is generated according to the equipment information of the target host equipment and the authorization information of the client equipment, so that complete private deployment of the service is realized; the equipment authorization file data is grouped and encrypted into an encrypted file set by adopting a preset encryption strategy, and then the encrypted file set is stored in a local cache, so that peripheral equipment can be avoided to realize complex authorization communication work, the data security is ensured, and the operation convenience and deployment flexibility are improved; then, a platform main service is started, and connection is established between the two services based on the local cache, so that the target host equipment performs authorization service, and the requirement of an enterprise for efficient and stable authorization service is met; besides, authorization information verification is carried out on the service regularly, and the authorization service is quitted when an authorization result is abnormal, so that unauthorized access and use are avoided, and the security of the equipment is further enhanced.

The invention relates to the technical field of robot control, and discloses a robot peripheral control method and system based on machine learning. The system comprises an environment perception module, a dynamic decision-making module and an execution optimization module, wherein the environment perception module is used for acquiring real-time multi-modal data, including visual image sequences, depth information, temperature gradient distribution and sound field spectrum characteristics, of an external environment and inputting the real-time multi-modal data into a machine learning model; the dynamic decision module processes data through a multi-task joint trained neural network model, and outputs a preliminary control strategy containing a peripheral type identifier, an action sequence template and an initial parameter set; and the execution optimization module combines the current attitude dynamics constraint and the energy distribution state of the robot, corrects the preliminary strategy, generates an executable control instruction, and sends the executable control instruction to the target peripheral. The system adapts to control requirements in a complex environment through multi-link cooperation, and is suitable for various robot application scenes.

The invention discloses a device wakeup method and a related device.According to the method, peripherals in an electronic device can be divided into necessary wakeup peripherals and non-necessary wakeup peripherals, when the electronic device detects wakeup operation, the necessary wakeup peripherals can be waken up, process scheduling of the necessary wakeup peripherals can be recovered, and the non-necessary wakeup peripherals can be waken up; and recovering the process scheduling of the peripheral which is not required to be awakened, and controlling the system to enter a working state after the process scheduling of the peripheral which is required to be awakened is recovered. Therefore, the electronic equipment does not need to wait for all peripherals to be awakened, but only needs to awaken part of the peripherals and recover the process scheduling, so that the subsequent awakening process can be executed, the number of the peripherals needing to be awakened before the system enters the working state is reduced, and the equipment awakening speed is increased.

The invention provides a quick start and security verification method and equipment for an embedded device, a medium and a program product, in the method, firmware is divided into a core start module and a non-core function module in advance, and the core start module and the non-core function module are respectively stored in a high-speed access area and a common storage area of a nonvolatile memory; after the embedded device is powered on, initialization of the key peripheral is completed; when firmware is started or updated for the first time, security verification based on a digital signature is executed on the core starting module, if verification is passed, a mirror image of the core starting module is written into a running cache partition of the nonvolatile memory, and an integrity label is generated; in the subsequent starting process, the mirror image is loaded from the running cache partition, and the integrity label is used for executing rapid verification; after loading of the core starting module is completed, the non-core function module is loaded, and lightweight check is executed. According to the method, the security of the core module is ensured, the performance and security requirements of the non-core module are considered, and the calculation and storage overhead is reduced.

The present disclosure relates to an in-memory computing architecture and an operation strategy thereof, the in-memory computing architecture comprising: a memory array comprising a memory string, a source line, a word line, and a bit line; the storage string comprises a plurality of storage units which are connected in series along a first direction, each storage unit comprises a storage transistor and a bypass resistor which are connected in parallel, the storage string is connected with a source line through a lower gate tube and is connected with a bit line through an upper gate tube, and a control end of each storage unit is connected with a word line; the driving and detecting circuit is connected with the source line, and the driving and detecting circuit is configured to inject reading current into the source line and detect and output a voltage signal of the source line; and a peripheral circuit connected to the word line and the bit line, the peripheral circuit configured to control voltages of the word line and the bit line. According to the technical scheme, the framework of the storage array can be used for executing the calculation task, the multiple storage strings can be operated in parallel, the voltage change of the source line corresponding to each storage unit is detected, the calculation result is read out from the source line, and high calculation efficiency is achieved.

The invention discloses a data calibration compensation method for an off-axis magnetic encoder, and the method comprises the following steps: S1, calibration initialization: carrying out the initialization of used peripherals, calibration parameters and an encoder chip, and making preparations for calibration; s2, forcibly dragging the motor to align: forcibly dragging a motor rotor to rotate to a position 0 of a nearest electrical angle by adopting a non-inductive control mode, and recording a calibration initial position; s3, calculating calibration data by rotating the motor: recording a data compensation result of the encoder by taking the original data of the encoder as an index; the calibration method does not need other equipment to drive the motor to coaxially rotate for calibration, the stator magnetic field is directly utilized to calibrate the motor, system errors caused by external equipment are avoided, the accurate relative position relation between the electron magnetic field and the rotor magnetic field can be obtained, the driving efficiency is higher, the driving dead zone is smaller, and the calibration precision is higher. And various coaxiality and roundness error data of the off-axis magnetic encoder can be improved.

The embodiment of the invention provides a chip, a control method and equipment, the chip comprises an event triggering unit and a plurality of peripherals, the event triggering unit is connected with the peripherals, and to-be-executed events of the peripherals have a set execution sequence. The event triggering unit is used for receiving a state synchronization signal sent by the execution peripheral of the previous event, and the state synchronization signal is sent by the execution peripheral of the previous event after the event execution state of the execution peripheral of the previous event meets a preset condition. The event triggering unit is further used for responding to a state synchronization signal sent by the execution peripheral of the previous event and sending an event triggering signal to the execution peripheral of the later event, and the event triggering signal is used for triggering the execution peripheral of the later event to execute the later event. Through the above technical scheme, the event triggering of the peripheral can be realized based on a hardware mode, the processor does not need to participate, the real-time performance is higher, and the resource consumption of the processor is reduced.

Provided are a Peripheral Component Interconnect Express (PCIe) device and a method of operating the same. The PCIe device may include a performance analyzer, a delay time information generator and a command fetcher. The performance analyzer may measure throughputs of a plurality of functions, and generate throughput analysis information indicating a comparison result between the throughputs of the plurality of functions and throughput limits corresponding to the plurality of functions. The delay time information generator may generate a delay time for delaying a command fetch operation for each of the plurality of functions based on the throughput analysis information. The command fetcher may fetch a target command from a host based on a delay time of a function corresponding to the target command.

The invention relates to the technical field of embedded system development and verification, and discloses an embedded software full-digital excitation deployment method, system, device and medium, and the method comprises the steps: based on a virtualization modeling technology of a multi-core heterogeneous system, simulating a CPU architecture, an operating system, board card peripherals and peripheral interfaces of a target processor, constructing a general digital target machine; a cross-platform communication framework is established based on a real-time communication transmission technology of direct digital frequency synthesis, and real-time synchronization of data of a virtual environment and an interaction object is completed; and through cooperation of the general digital target machine and the cross-platform communication framework, full-digital deployment and verification of the embedded software are completed. According to the method, full-digital development and verification of the embedded software can be realized, a research and development mode of parallel hardware development, software development and system function verification is met, and the research and development efficiency of the embedded software is improved.

The embodiment of the invention discloses a memory device, an operation method, a memory system and a computer system. The memory device includes: a memory array including a first sub-array and a second sub-array; the first sub-array comprises a plurality of first storage unit rows; the second sub-array comprises a plurality of second storage unit rows; the peripheral circuit comprises a plurality of redundant control switch assemblies which are coupled with the plurality of second storage unit rows one by one; and a word line driving component coupled to each of the plurality of redundant control switch components; each redundancy control switch assembly is configured to respond to a first redundancy selection signal in a conduction state and transmit a corresponding redundancy control signal to the corresponding word line driving assembly; the corresponding word line driving component is configured to drive a second memory cell row, which is configured to replace the first memory cell row indicated by the input address information, in the plurality of second memory cell rows in response to the redundancy control signal.

The utility model provides a BMC module based on a Loongson processor and hardware equipment, and relates to the technical field of computers.The BMC module based on the Loongson processor comprises the Loongson processor, a memory chip, a memory module, an analog-digital conversion module, a network module, a power module and a connector; the Loongson processor is electrically connected with the memory chip, the memory module, the analog-digital conversion module, the network module and the connector. According to the BMC module provided by the invention, based on the Loongson processor, peripherals such as a memory, a display and a network can be integrated in the BMC module, various peripheral interfaces are connected, and the function diversity of the BMC module is improved. Meanwhile, the BMC module is independent of a server mainboard and is interconnected by adopting a connector, so that independent maintenance and management are facilitated; and abundant peripheral interfaces are reserved through the connector, so that secondary development is facilitated, and the universality and practicability of the BMC module are improved.

The invention belongs to the technical field of data exchange, and discloses a data exchange method, which is applied to a data exchange device, and the data exchange device comprises a main control module, an exchange module and a plurality of receiving modules. The method comprises the following steps: a first receiving module receives multiple pieces of time slice data of a first peripheral, and analyzes and recombines each piece of time slice data with a predetermined identifier based on an exchange instruction to obtain insertion data comprising a destination address; determining a first transmission link according to the switching instruction and the destination address, and sending the first transmission link to a switching module; the switching module determines a second transmission link according to the switching instruction and the destination address, and sends the switching instruction to the main control module or the second receiving module through the second transmission link; and the second receiving module determines a corresponding output node and a second peripheral according to the destination address, unpacks the inserted data and sends the unpacked inserted data to the second peripheral. According to the invention, the method can achieve the recognition and processing of the inserted data of the peripheral, and the receiving and output of the time slice data at different rates.

Managing a configuration of a docking station and computing peripherals, including performing, at a first time, a calibration and configuration of a configuration management model, including identifying contextual data associated with the docking station and the computing peripherals; training, based on the contextual data, the configuration management model, including generating a configuration policy including configuration rules, the configuration rules for performing computer-implemented actions to automatically configure the docking station and the computing peripherals; performing, at a second time, a steady-state management of the docking station and the computing peripherals, including monitoring the contextual data of the docking station and the computing peripherals; and accessing the configuration management model including the configuration policy, identifying the configuration rules based on the monitored contextual data, applying the configuration rules to perform the computer-implemented actions to configure the docking station and the computing peripherals.

The embodiment of the invention relates to the technical field of integrated circuits, in particular to a system-level verification method and test system for an RISC-V reconfigurable multi-core processor chip, and the method comprises the steps: firstly, verifying a hardware state; the hardware state comprises core configuration of the reconfigurable multi-core processor, internal storage, interruption, states of a plurality of cores and configuration of a control state register; then, verifying the basic software; the verification of the basic software comprises the following steps of: lightening a chip of the reconfigurable multi-core processor, starting an operating system, and verifying bottom-layer driving software and a board-level support package; and finally, verifying cooperative work of the upper software and the multi-core chip software and hardware system. According to the system-level verification method provided by the embodiment of the invention, verification of a system-level peripheral scheme and verification of basic software adaptation are carried out on the RISC-V reconfigurable multi-core processor chip by simulating related hardware peripherals, and compatibility and continuous optimization between software and hardware are ensured.

The invention belongs to the technical field of robot communication interaction, and relates to an equipment capability self-description and negotiation method and device, an upper computer and a storage medium. The peripheral equipment is powered on to issue an equipment access instruction, so that the upper computer obtains the types and the number of the peripherals in the system in real time; state and capability information is obtained based on a unified standard frame, operation parameters and controllable range structuring are achieved, and a basis is provided for unified control; a control instruction template is automatically generated according to the information, multiple sets of adaptive logics are not needed, cross-device instruction and strategy multiplexing is supported, and the extension and operation and maintenance cost is reduced; the target execution instruction is issued through the preset verification strategy, problems can be found in advance when parameters cross boundaries or condition conflicts occur, wrong execution is avoided, the system stability is improved, peripheral automatic identification, capability unified expression, instruction template automatic generation and safe execution are achieved, and the compatibility and reliability of a robot system in a multi-device environment are enhanced.

Systems and methods for configuring peripherals in response to accidents are described. In some embodiments, an Information Handling System (IHS) may include: a processor; and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution by the processor, cause the IHS to: obtain a notification of a shock event of the IHS; communicate information regarding the shock event to peripheral firmware of one or more peripherals of the IHS. The peripheral firmware may receive the information regarding the shock event of the IHS from the IHS; and responsive to the information, perform a corrective action. In some embodiments, the corrective action includes a configuration update and a communication to the IHS of the configuration update, a self-test scan for health of the peripheral, shutting off port or data access to the peripheral, and / or collection of telemetry of the peripheral.

A device may generate a link training and status state machine (LTSSM) test configuration that includes states and paths connecting the states, and may provide the LTSSM test configuration for tracing through by a device under test. The device may receive results associated with tracing through of the LTSSM test configuration by the device under test, and may modify, based on the results, one of the paths of the LTSSM test configuration to include a different one of the states and to generate a modified LTSSM test configuration. The device may provide the modified LTSSM test configuration for tracing through by the device under test.

The utility model belongs to the technical field of computer peripherals and man-machine interaction equipment, and particularly relates to an adjustable mouse bottom plate with multiple PCB installation positions and a mouse. The PCB is arranged on the bottom plate main body; the bottom plate comprises a bottom plate body and a plurality of PCBs arranged on the bottom plate body, the sensors are arranged on the PCBs, the bottom plate body is provided with a plurality of PCB installation positions used for selectively installing the PCBs on any PCB installation position according to user operation requirements, the bottom of each PCB installation position is provided with an optical sensor window matched with the position of the corresponding sensor, and the optical sensor windows are used for allowing light of the sensors to penetrate through and receiving reflected light. The technical problem that in the prior art, the position of a mouse sensor is fixed and cannot be adjusted according to the operation habit of a user, so that the user experience and operation flexibility are insufficient is solved, the control precision and smoothness of the mouse are improved, and the requirements of the user in different use scenes are met.

The invention discloses a peripheral interface module of computer equipment, which comprises a module side expansion interface, and the module side expansion interface is connected with a host side expansion interface of the computer equipment in a physical plugging mode; each of the host side expansion interface and the module side expansion interface comprises a module function signal and is used for identifying a protocol type supported by the peripheral interface module; and the protocol self-matching system is used for automatically identifying the protocol type of the peripheral interface module according to the module function signal and switching the corresponding controller configuration to realize a plug-and-play function. After the interface is replaced, the interface output from the processor is lower in delay, no external extra equipment exists, carrying is more convenient, management and maintenance are convenient, meanwhile, the interface is used for self-defining, secondary development and transformation of a notebook computer interface according to self requirements, the interface adapts to application scenarios of non-standard peripherals, different function protocol modules are automatically recognized, and the interface switching efficiency is improved. The switching of the corresponding controllers is completed, and the plug and play of the module is realized.

A device connectable between a host computer and a computer peripheral over a standard bus interface is disclosed, used to improve security, and to detect and prevent malware operation. Messages passing between the host computer and the computer peripherals are intercepted and analyzed based on pre-configured criteria, and legitimate messages transparently pass through the device, while suspected messages are blocked. The device communicates with the host computer and the computer peripheral using proprietary or industry standard protocol or bus, which may be based on a point-to-point serial communication such as USB or SATA. The messages may be stored in the device for future analysis, and may be blocked based on current or past analysis of the messages. The device may serve as a VPN client and securely communicate with a VPN server using the host Internet connection.

The invention discloses a module schematic diagram automatic design method suitable for electronic product design, and belongs to the technical field of electronic design automation. The method aims at solving the problems that traditional manual schematic diagram design is low in efficiency, prone to errors and highly dependent on experience of engineers. The method comprises the following steps: firstly, carrying out structured information modeling on a design demand, a design template and a to-be-generated module; secondly, according to the design requirement after modeling, all candidate main chip sets meeting the conditions are screened out from a device library; then, aiming at each candidate main chip, automatically constructing a peripheral circuit of the candidate main chip through a template matching process; and finally, calculating the general device in the template according to the parameters of the main chip and replacing the general device with an actual device with a specific model. According to the method, various module schematic diagram schemes which conform to specifications and can be optimized can be quickly and accurately generated according to a single design requirement, the automation level and efficiency of electronic design are remarkably improved, and the design threshold is reduced.

In accordance with some embodiments, systems, apparatus, interfaces, methods, and articles of manufacture are provided for creating shared experiences using peripheral devices. In various embodiments, data is captured about a first user's peripheral usage and environment. A determination is made based on the data as to the first user's current experience. Aspects of the first user's experience are then recreated for a second user. In various embodiments, the experience is shared with the second user via peripherals and output devices.

The invention discloses a shared peripheral control method of a single-chip multi-core system, electronic equipment and a medium. The method comprises the following steps: determining a use priority of each core to a shared peripheral based on a performance parameter of each core; when the shared peripheral is not used and the first core is started, a hardware spin lock is obtained, the shared peripheral is initialized, a control authority of the shared peripheral is granted to the first core, and the hardware spin lock is released; when any second core is started, the second core obtains a hardware spin lock, the target core occupying the control authority of the shared peripheral is re-determined based on the initialization state of the shared peripheral, the second use priority and the first use priority, and peripheral use interfaces of the remaining cores point to a proxy communication interface of the target core. According to the method, the target core occupying the control authority of the shared peripheral is dynamically adjusted based on the use priority of each core using the shared peripheral to the shared peripheral, each core has an opportunity to take over the agent of the shared peripheral, and the system power consumption is reduced.

Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.