499results about How to "Reduce area" patented technology

The invention relates to a power supply module which comprises an inductance circuit, a switch circuit, a check driving circuit and a controller, wherein the inductance circuit is provided with an inductor and a voltage feedback line, and the voltage feedback line feeds back the end voltage of the inductor. The switch circuit is electrically connected with the inductance circuit to drive the inductance circuit. The check driving circuit is electrically connected with the switch circuit and the voltage feedback line, and the check driving circuit controls the switch circuit and generates a current feedback signal according to the end voltage of the inductor. The controller is electrically connected with the check driving circuit, and controls the check driving circuit according to the current feedback signal.

The invention discloses a diffractive optical waveguide and a preparation method thereof, and a head-mounted display device, and relates to the technical field of augmented reality, and the preparation method of the diffractive optical waveguide comprises the steps: obtaining a target eye box range adaptive to a target crowd; according to the human eye parameters of each user group in the target group, splitting the target eye box range to obtain sub-eye box ranges adapted to each user group; diffractive optical waveguides adapted to the user groups are prepared based on the sub-eye box ranges, and the area of a coupled-out grating in each diffractive optical waveguide is smaller than the area of a coupled-out grating of an optical waveguide designed for covering the target eye box range. The optical efficiency and uniformity of the diffractive optical waveguide can be ensured, and the diffractive optical waveguide is prevented from generating obvious rainbow lines, so that the use experience of a user is improved.

The embodiment of the invention provides a single-bus communication method and device, a chip and a medium, and the method comprises the steps: enabling a host to enter an initialization mode after the host confirms that an internal power supply and a clock of a slave are stable; the host sends a wake-up code to the slave within a set time to wake up the slave, and releases the bus to enter a normal communication mode; the host sends a communication signal to the slave through the improved communication frame; after the host receives a response signal of the slave, the host releases the bus, the bus is pulled to a high level from an external pull-up resistor, and the transmission is ended; wherein the format of the improved communication frame comprises ten codes, one code corresponds to one bit, and the ten codes sequentially comprise one start bit, six address bits, one read-write control bit, one data bit and one response bit. A wake-up code is set before communication between the host and the slave, so that the slave is prevented from being mistakenly waken up. According to the communication mode, the coding mode is simplified, the chip area is reduced, and the transmission speed of the chip is also improved.

The invention provides a PQC and SM2 / 9 cooperative operation cryptographic chip and method based on an RISC-V architecture, and belongs to the technical field of cryptographic security. The chip comprises an RISC-V core and a configurable password collaborative operation unit, wherein the configurable password collaborative operation unit comprises a collaborative control state machine and a unified operation unit capable of being dynamically reconfigured. The method comprises the following steps: receiving and decoding a single cooperative operation instruction from an RISC-V core through a cooperative control state machine, and obtaining operation data feature information; the data length and the security level identification are extracted, and the optimal collaborative operation process is selected in a self-adaptive mode through comparison with a preset threshold value; and finally, dynamically configuring and scheduling a unified operation unit according to the selected process, and completing cooperative operation of the post-quantum cryptography algorithm and the SM2 / SM9 algorithm in an atomization mode. According to the method, deep fusion and intelligent scheduling of the two algorithms are realized on the hardware level, and the efficiency, the resource utilization rate and the safety of cooperative operation are improved.

This invention relates to the field of biopharmaceutical technology, providing a self-assembled peptide-rhein conjugate, its formulation, preparation method, and applications. The MMP-9-responsive self-assembled peptide-rhein conjugate of this invention, with the sequence Rhein-GFFPLGLAGACE, can respond to abnormally activated MMP-9 in atherosclerotic plaques, self-assembling in situ into a stable nanofiber structure at the lesion site. The rhein in this conjugate exhibits significant anti-inflammatory and antioxidant functions, but its water solubility and oral bioavailability are low. These are significantly improved after conjugation with the peptide, achieving targeted delivery and prolonging retention time. The introduction of the tripeptide ACE, which mimics the function of glutathione, further enhances the conjugate's ability to resist oxidative stress. Furthermore, this conjugate exhibits excellent anti-inflammatory and antioxidant effects, scavenging ROS, inhibiting inflammatory pathways, regulating macrophage phenotype, and inhibiting apoptosis, providing a new strategy for the treatment of atherosclerosis.

This application provides a voltage conversion circuit and electronic device, including: a controller, a terminating resistor, a plurality of first resistors, a plurality of second resistors, and a plurality of control switches. The first end of the terminating resistor is grounded; the first resistors are connected in series, and the first end of the first first resistor is connected to the second end of the terminating resistor; the first end of one second resistor is connected to the first end of the first first resistor, and the first end of each of the other second resistors is connected to the second end of the first resistor respectively; the first end of each control switch is connected to the second end of one of the second resistors respectively, and the second end of the control switch is connected to or grounded to a preset reference voltage according to a control signal sent by the controller; one of the plurality of control switches is set as a modulation switch, which is used to receive a modulation signal sent by the controller, and both the modulation switch and the modulation signal are determined based on nonlinear error.

A liquid crystal display (LCD) designed to save energy during operation is characterized by comprising: a plurality of liquid crystal cells; a plurality of liquid crystal control units that control the plurality of liquid crystal cells respectively; and a positive and negative voltage source driving circuit, wherein the positive and negative voltage source driving circuit comprises: a bandgap reference circuit operating between a positive voltage VSP and a ground potential GND to provide a positive reference voltage +VREF; a reference voltage generating circuit for receiving the positive reference voltage +VREF and outputting a positive reference voltage VREF_VGMP to a positive operational amplifier and outputting a negative reference voltage VREF_VGMN to a negative operational amplifier; and the positive and negative operational amplifiers respectively outputting a positive voltage and a negative voltage to one of the plurality of liquid crystal control units to control the grayscale level of one of the plurality of liquid crystal cells.

This disclosure provides a DC-DC converter and chip, wherein the DC-DC converter includes a bootstrap boost circuit, a charge pump boost circuit, a high-side drive circuit, a low-side drive circuit, a high-side power transistor, and a low-side power transistor. The bootstrap boost circuit provides a first boost voltage to the high-side drive circuit. The high-side drive circuit outputs a first high-side drive voltage to the control electrode of the high-side power transistor based on the first boost voltage. The charge pump boost circuit generates a second boost voltage through a charge pump and outputs a second high-side drive voltage to the control electrode of the high-side power transistor based on the second boost voltage. The second boost voltage is greater than the first boost voltage. The first electrode of the high-side power transistor is coupled to the input voltage terminal, and the second electrode is coupled to the first electrode of the low-side power transistor via a switching node. The high-side power transistor is turned on or off according to the first and second high-side drive voltages. One end of the bootstrap boost circuit and one end of the charge pump boost circuit are respectively coupled to the switching node.

The utility model discloses a kind of car sunroof guide rails with buffering noise reduction structure, it is related to sunroof guide rail field, this kind of car sunroof guide rail with buffering noise reduction structure includes the guide rail main body extending along first direction, outwardly extending mounting plate is formed on the guide rail main body one side outer wall, multiple mounting holes are opened on mounting plate, for bolt connection frame, bolt is passed in mounting hole when connecting;This kind of car sunroof guide rail with buffering noise reduction structure forms three-dimensional grid structure by buffer groove and extension groove, main rubber pad absorbs vertical impact, extension rubber pad inhibits longitudinal vibration, double elastic deformation greatly reduces the area of mounting plate contact part after installation with frame, blocks vibration transmission path, rubber ring in the protruding part groove isolates bolt and mounting plate metal contact, eliminates high-frequency friction abnormal sound.

This disclosure provides an ESD protection circuit, including a discharge branch, a detection branch, and an amplification branch. The discharge branch consists of a discharge transistor; the detection branch consists of a detection capacitor between the gate and source or gate and drain of the discharge transistor and a corresponding detection resistor connected in parallel between the gate and drain or gate and source of the discharge transistor. In the detection branch of this disclosure, the parasitic capacitance between the gate and source or gate and drain of the discharge transistor is used as the detection capacitor, eliminating the need for additional capacitors coupled to the detection resistor to generate a detection voltage, thereby reducing the overall area of ​​the ESD protection circuit.

The turbocharger comprises a turbine shaft (1), a turbine (2) is arranged at the output end of the turbine shaft (1), a middle body (3) is arranged on the side, close to the turbine shaft (1), of the turbine (2), the turbine shaft (1) is rotationally connected to the axis of the middle body (3), an air cooling air channel (3.1) is arranged at the end, close to the turbine (2), of the middle body (3), and the air cooling air channel (3.1) is communicated with the air cooling air channel (3.1). The air cooling air channel (3.1) is in a U shape and is arranged in the circumferential direction of the turbine shaft (1). The utility model provides a turbocharger with an air cooling intermediate, which is used for cooling the turbocharger in an air cooling manner so as to reduce the production cost of the turbocharger.

This disclosure provides a reference current generation circuit for tracking word line voltage and a non-volatile memory. The reference current generation circuit includes a voltage clamping circuit, and a correction voltage adjustment circuit, a read operation current generation circuit, and a current mirror circuit electrically connected to the voltage clamping circuit. The correction voltage adjustment circuit is used to receive an input voltage and generate a correction voltage under the drive of the input voltage. The voltage clamping circuit clamps the voltage at the correction voltage based on a negative feedback loop. The read operation current generation circuit receives the read operation voltage of the memory cell in the non-volatile memory and generates a read operation current matching the read operation transconductance of the memory cell based on the read operation voltage and the correction voltage. The current mirror circuit mirrors the read operation current to generate and output a reference current that tracks the word line voltage. This disclosure avoids the risk of voltage stress and ensures sufficient current margin when the word line voltage changes, effectively improving read operation accuracy and read speed.

This application discloses an amplifier and a method for controlling its common-mode voltage. The amplifier includes: a positive-terminal P-type transistor; a negative-terminal P-type transistor; a positive-terminal N-type transistor having a drain coupled to the drain of the positive-terminal P-type transistor and outputting a positive output signal; a negative-terminal N-type transistor having a drain coupled to the drain of the negative-terminal P-type transistor and outputting a negative output signal; a first resistor coupled between the gate of the negative-terminal N-type transistor and the negative input signal; a second resistor coupled between the gate of the negative-terminal N-type transistor and the positive output signal; a third resistor coupled between the gate of the negative-terminal P-type transistor and the negative input signal; and a fourth resistor coupled between the gate of the negative-terminal P-type transistor and the positive output signal.

The invention discloses a voltage-controlled oscillator circuit, comprising: a current control circuit module configured to receive an input voltage and generate a control current responsive to the input voltage; the ring oscillator circuit module is connected with the current control circuit module and comprises a multi-stage inverter and a current adjusting unit which are connected in series to form a ring; the current adjusting unit is respectively connected to the current control circuit module and each stage of the multi-stage phase inverter, and is configured to synchronously and symmetrically adjust the pull-up current and the pull-down current of each stage of phase inverter in the multi-stage phase inverter in response to the control current; and the output driving circuit module is connected with an output node of the ring oscillator circuit module so as to shape and drive the oscillation signal generated by the ring oscillator circuit module and output a clock signal with a duty ratio of 50%. The circuit structure is simplified, the chip area is saved, the oscillator is allowed to directly work at the target frequency instead of double frequency, and the overall power consumption is reduced.

This utility model relates to the field of medical device technology and discloses a dressing change kit for infants and young children with persistent seepage at deep vein catheter insertion sites. The kit includes a dressing bag, an inner wall with a sterilization pack, a skin protective dressing, an exposed catheter patch, and a sterile gauze sleeve. Elastic strips are fixedly connected to both the front and back sides of the sterile gauze sleeve. A hemostatic component for the puncture site and continuous bleeding is provided on the inner wall of the dressing bag. This hemostatic component includes a stretchable adhesive tape, the outer side of which is placed on the inner wall of the dressing bag. A pressable circular plate is fixedly connected to the bottom of the stretchable adhesive tape. In this utility model, the operator passes the catheter through the skin protective dressing, the exposed catheter patch wraps around the dialysis catheter, and then the dialysis catheter is inserted into the sterile gauze sleeve, thus securing the dialysis catheter and achieving fixation of the catheter, which cannot be cut.

The invention provides a valve group and a valve tower, and belongs to the field of semiconductor devices. The valve group comprises coolers arranged at intervals in the thickness direction, damping capacitors and damping resistors, the damping capacitors are arranged between every two adjacent coolers in a crossing mode, capacitor supports used for installing the damping capacitors are arranged on the side faces of the coolers, and the two ends of each damping capacitor are connected with the capacitor supports on the two coolers respectively. In the two capacitor supports at the two ends of the damping capacitor, one is a conductive support, the other is an insulating support, one end of the damping capacitor is communicated with the corresponding cooler through the conductive support, the other end of the damping capacitor is communicated with one end of the damping resistor through a wire or a conducting bar, and the other end of the damping resistor is communicated with the cooler where the insulating support is located. The valve tower comprises the valve group. The valve bank is integrally designed, so that the structure of the valve bank is more compact, and the area required for construction of a valve tower is reduced.

The invention provides a rising edge trigger and a low noise amplifier. The rising edge trigger comprises a first phase inverter, a second phase inverter, a capacitor, a Schmitt trigger, a phase inverter circuit, an NAND gate and a third phase inverter, the input end of the first phase inverter is used for accessing an enable signal for controlling the low-noise amplifier to work; the power supply end of the second phase inverter is used for being connected to the current outflow end of a current source for providing reference current for the low-noise amplifier; the first input end of the NAND gate is connected to the output end of the inverter circuit, and the second input end of the NAND gate is connected to the output end of the first inverter; the input end of the third phase inverter is connected to the output end of the NAND gate, and the output end of the third phase inverter is used for outputting a delay control signal. According to the rising edge trigger, the area of the capacitor can be reduced according to the magnitude of the current of the accessed current source for providing the reference current for the low-noise amplifier, so that the occupied area of the rising edge trigger is reduced.

The application discloses a neodymium-iron-boron magnet material and a preparation method thereof, and an electronic device containing the same. The neodymium-iron-boron magnet material comprises the following components: R: 28.0-32.0 wt%, R comprises Nd, R further comprises Tb and / or Dy, the content of Nd is greater than or equal to 27.0 wt%; Cu: 0.16-0.40 wt%; Ga: 0.07-0.24 wt%; Al: less than or equal to 0.10 wt%; B: 0.96-1.10 wt%; Co: 0.15-2.0 wt%; M: 0.10-0.25 wt%, M is selected from at least one of Ti, Zr and Nb; and a phase with a chemical composition of R w Fe 100‑w‑x‑y‑z Co x Cu y Ga z is contained in the two-particle grain boundary of the neodymium-iron-boron magnet material. The neodymium-iron-boron magnet material in the application can realize a significant improvement in coercive force under the condition of adding a small amount of heavy rare earth element Tb, while maintaining a high remanence and squareness.

The invention belongs to the technical field of integrated chips, and particularly relates to a bias circuit of a radio frequency power amplifier and the radio frequency power amplifier, which comprises a first transistor Q0, a second transistor Q1, a third transistor Q2, a fourth transistor Q3, a fifth transistor Q4, a sixth transistor Q5, a seventh transistor Q6 and an eighth transistor Q7, a sixth transistor Q5 is adopted as a sampling structure and an eighth transistor Q7 is adopted as active negative feedback, so that the influence of process errors and temperature change on the transistors is used for compensating the influence of temperature on the fifth transistor and the first transistor, and the transfer of a quiescent working point is greatly corrected; meanwhile, according to the scheme, an active negative feedback path can be formed at the base electrode of the power supply transistor Q1 and an output signal port, and the linearity is further improved.

The invention discloses an adjustable MMIC band-pass filter based on a tap inductance technology. The adjustable MMIC band-pass filter comprises a radio frequency input end, a radio frequency output end, a low-pass filter circuit and an adjustable band-pass filter circuit, wherein the low-pass filter circuit and the adjustable band-pass filter circuit are connected between the radio frequency input end and the radio frequency output end in series; the low-pass filter circuit comprises first to third capacitors and an inductor; the adjustable band-pass filter circuit comprises a first network, a second network, a third network, a fourth network, a fifth adjustable capacitor and a sixth adjustable capacitor; one end of the inductor is connected with the radio frequency input end, and the other end of the inductor is coupled with the first network; the first network and the second network are coupled through a fifth adjustable capacitor, the second network and the third network are coupled through a tap inductor, the third network and the fourth network are coupled through a sixth adjustable capacitor, and the fourth network is connected with a radio frequency output end. Compact magnetic coupling is achieved through the tap inductance technology, insertion loss and the chip area are remarkably reduced, and meanwhile the wide tuning range and high harmonic suppression are achieved.

A display device (10) includes a substrate (100), a first signal line (DL1) disposed on the substrate (100), and a first pixel (PU12) including a first transistor (202) having a gate electrode (GE), a source electrode (S) and a drain electrode (D), wherein the source electrode (S) is electrically connected to the first signal line (DL1) . The display device (10) includes a fan-out line (FL1) electrically connected to the first signal line (DL1), wherein the fan-out line (FL1) partially overlaps the first pixel (PU12) and is formed in a layer (CL3) different from layers (CL1, CL2)of the gate electrode (GE), the source electrode (S) and the drain electrode (D).

The utility model discloses a double-voltage heating structure and an instant heating module. The double-voltage heating structure comprises a base body and a plurality of heating resistor circuits which are sequentially arranged side by side at intervals. A first electrode, a second electrode, a third electrode and a fourth electrode are arranged on the surface of the substrate; one end of the first electrode is electrically connected with one end of one part of the heating resistor circuit in sequence; a first connecting part extends from the other end of the first electrode; one end of the second electrode is electrically connected with the other ends of all the side-by-side heating resistor circuits; a second connecting part extends from the other end of the second electrode; the third electrode is located between the first electrode and the second electrode; one end of the third electrode is electrically connected with the other ends of all the side-by-side heating resistor circuits; a third connecting part extends from the other end of the third electrode; one end of the fourth electrode is electrically connected with one end of the remaining heating resistor circuit; the other end of the fourth electrode is electrically connected with one end of the second electrode; the manufacturing cost and the area are saved, and the utilization rate of the heating resistor circuit is improved.

The utility model discloses a kind of electrically conductive structure, photovoltaic module and photovoltaic power generation system, electrically conductive structure includes electrically conductive matrix, insulating layer and first adhesive layer. Insulating layer is located at the side of electrically conductive matrix. First adhesive layer is connected at the side of insulating layer away from electrically conductive matrix. According to the electrically conductive structure of the utility model, by integrating electrically conductive matrix, insulating layer and first adhesive layer together, compared with the connection mode of traditional electrically conductive structure and electrical component (for example battery piece), the use of adhesive tape is reduced, thereby reducing the area of optical obstruction, it is favorable to promote the output power of electrical component connected with electrically conductive structure, while the mutual displacement of electrically conductive matrix, insulating layer and first adhesive layer in the process of assembly and use can be avoided, it is favorable to promote the structural stability and reliability of electrically conductive structure, promote the use safety of electrically conductive structure. In addition, the laying process of electrically conductive structure is simplified, and the mounting yield of electrically conductive structure is improved.

The utility model provides a cylindrical battery shell bottom welding mark structure and a cylindrical secondary battery. The cylindrical battery shell bottom welding mark structure comprises a shell bottom and a welding mark positioned on the shell bottom, the welding track of the shell bottom and the negative collector plate is the welding mark; the welding mark is in a vortex line shape, the center point of the welding mark is a point O, the vertex angle, away from the point O, of the outer end of the welding mark is a point A, the vertex angle, close to the point O, of the inner end of the welding mark is a point B, the area of a circle which takes the point O as the circle center and passes through the point A is S11, the area of a circle which takes the point O as the circle center and passes through the point B is S12, the area of a radiation surface of the welding mark is S10, the area of the shell bottom is S0, and S10 = S11-S12. And S10 is not less than 1.5% S0 and not more than 8.5% S0. According to the utility model, the welding print is arranged to be in the vortex line shape, so that the length of the welding print can be guaranteed, the area of the radiation surface of the welding print can be reduced, and the welding effect can be effectively improved, the safety performance of the battery can be guaranteed and the processing cost of the battery can be reduced by limiting the area of the radiation surface of the welding print.

The application discloses a cold plate device and a battery pack, comprising a cold plate body, the cold plate body is provided with a flow channel area, a sealing area and a pressure relief area, the sealing area is used for sealing the flow channel area, the flow channel area is used for containing a heat exchange medium, and the pressure relief area is used for being correspondingly arranged with an explosion-proof valve of a cylindrical battery; the pressure relief area comprises a pressure relief hole and a thinning area located outside the pressure relief hole, and a projection of an outer edge of the thinning area on a bottom surface of the cylindrical battery can surround the explosion-proof valve. The pressure relief area is composed of the pressure relief hole and the thinning area, so that the area of the pressure relief hole can be reduced, and the sealing connection strength of the edge of the flow channel area can be prevented from being affected due to the excessively large area of the pressure relief hole. The thinning area is weak in strength, when the explosion-proof valve of the cylindrical battery is opened for pressure relief, the explosion-proof valve and high-pressure gas sprayed out can easily damage the thinning area, so that the thinning area is collapsed, and it is ensured that the high-pressure gas in the cylindrical battery can be relieved through the cold plate device.

This invention belongs to the technical field of integrated circuit manufacturing, and discloses a SAR-assisted pipelined analog-to-digital converter and its control method. The analog-to-digital converter includes a two-stage SAR ADC module, and the first stage capacitor array includes C 1 1 ~C 1 M‑1 C 1 2 ~C 1 M‑1 The reference voltage is V ref C 1 1 The reference voltage is V cm =V ref / 2, an improved monotonic switching scheme using redundant capacitors can perform successive approximation comparisons to obtain an M-bit digital code. After completing the first-stage conversion, a passive residual transfer scheme is used, along with inter-stage bit transfer, to enter the second-stage conversion. This second-stage conversion employs the same improved monotonic switching scheme as the first stage, performing successive approximation comparisons to obtain an N-bit digital code. Finally, through timing alignment, an M+N-bit digital code is obtained. This design saves device area and improves conversion efficiency.

The utility model relates to the technical field of ultrasonic imaging and chip design, and relates to a circuit system and chip for realizing on-chip continuous wave Doppler ultrasound. The utility model directly connects together the host computer receiver and the host computer receiver and internal transducer array element through the CW channel; the array periphery can be multiplexed for transmitting the analog channel of the received signal in B mode; the MUX switch is arranged on the array unit inside and the array periphery circuit; the MUX switch of array unit inside is controlled to control the access of arbitrary transducer array element to the CW channel; arbitrary CW channel is connected to the host computer interface outside the chip through the MUX switch on the array periphery circuit. The utility model realizes the continuous wave Doppler ultrasound function under the premise of not increasing the number of additional cables and not increasing the additional power consumption; the flexibility of CW transmission and reception is guaranteed, the chip area is saved, the cable needed for ultrasonic probe integration is reduced, and the utility model can be widely applied to various ultrasonic imaging systems and ultrasonic chips.

The application provides a signal peak position detection device and method and an input signal extraction equipment. A lookup table memory comprises: a lookup table, the lookup table comprising: bit values of sign bits of an input signal, and a corresponding relationship of a multiplication result of the input signal and a local signal; a sign extractor is used for extracting a target bit value of a sign bit of the input signal corresponding to each sampling; a multiplexer is used for, for each sampling, looking up a target multiplication result matched with the target bit value from the lookup table of the lookup table memory according to the target bit value; and a calculation unit is used for calculating a modulus value corresponding to each sampling according to the target multiplication result obtained for each sampling, and determining a peak position of the input signal in a time period of multiple samplings according to a sampling corresponding to a maximum modulus value in all modulus values. The application can omit a multiplier and an adder required for implementing the multiplication operation in a circuit, and greatly reduces the area and overall power consumption of the circuit.

The application discloses a low-power bandgap reference current source circuit and a control method, and the circuit comprises a current mode bandgap circuit, an error amplifier input stage circuit, a threshold modulation circuit and a current mirror circuit; the current mode bandgap circuit is internally provided with an error amplifier OPAMP and a proportional resistance network; the error amplifier input stage circuit is a PMOS pair tube input stage circuit; the threshold modulation circuit is a source-liner forward bias threshold modulation circuit, which is used for forward biasing the threshold voltage of all PMOS tubes in the low-power bandgap reference current source circuit and enabling the NMOS tube connected with the error amplifier OPAMP output stage to work in a saturation region; and the current mirror circuit is a series diode compensation method current mirror circuit structure. The application is compatible with a standard CMOS process, realizes sub-1V low voltage, micro-nano ampere level low power consumption, high-precision low-noise small area effect, solves various technical pain points of a traditional scheme, and has excellent application prospects in a wearable device power management system.

The application discloses a kind of fermented feed fermented by three strains of probiotics of Bacillus YA ( Bacillus sp ), yeast Y ( Saccharomyces cerevisiae ) and capsular red bacteria R3 ( Rhodobacter capsulatus ), and preparation method and application in aquaculture thereof, and viable count is not less than 1×10 7 CFU / g.The fermented feed is replaced ordinary feed according to certain proportion, and feeding result shows that aquaculture water quality is significantly improved after adding fermented feed, and fish growth performance, digestive enzyme activity, immunity, and muscle quality are also obviously improved.Using the feed in suitable range can shorten growth cycle, reduce cost, improve aquaculture environment, reduce antibiotic use, and improve muscle quality of farmed animals, with good economic and ecological benefits, simple fermentation process, low cost, and suitable for industrial large-scale production.