767results about How to "Reduce area" patented technology

A low energy cost process for the co-production of oxygen and nitrogen employing a fuel tube extending into the first oxygen selective ion transport membrane whereby fuel is introduced adjacent to the closed end and flows cocurrently with oxygen containing gas in the annulus and an oxygen selective ion transport membrane having a separator section and a reactor section. An oxygen-containing feedstock, typically air, is compressed and then contacts the cathode side of the separator section where a portion of the oxygen contained within the feedstock is transported to the anode side of the separator section and recovered as an oxygen product gas. Substantially the remainder of the oxygen contained within the feedstock is transported from the cathode side of the reactor section to the anode side and exothermically reacted with a fuel. Following the exothermic reaction, hot nitrogen rich product gas is expanded in a turbine to generate the power necessary to compress the feedstock. Expanded nitrogen rich product gas may then be recovered from the turbine exhaust.

To provide a semiconductor memory device storing data, in which a transistor whose leakage current between a source/drain in off state is small is used as a writing transistor. In a matrix of a memory unit formed of two memory cells, in each of which a drain of a writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor, a gate of the writing transistor, and the other electrode of the capacitor in a first memory cell are connected to a first word line, and a second word line, respectively. In a second memory cell, a gate of the writing transistor, and the other electrode of the capacitor are connected to the second word line, and the first word line, respectively. Further, to increase the degree of integration, gates of the reading transistors of memory cells are disposed in a staggered configuration.

Time and frequency de-interleaving of interleaved data in an Integrated Services Digital Broadcasting Terrestrial (ISDB-T) receiver includes exactly one random access memory (RAM) buffer in the ISDB-T receiver that performs both time and frequency de-interleaving of the interleaved data and a buffer address calculation module for generating buffer address in the buffer. The system performs memory sharing of the time and frequency de-interleaver for ISDB-T receivers and reduces the memory size required for performing de-interleaving in an ISDB-T receiver and combines the frequency and time de-interleaver buffers into one RAM thereby reducing the memory size.

The present invention discloses a bidirectional PNPN silicon-controlled rectifier comprising: a p-type substrate; a N-type epitaxial layer; a P-type well and two N-type wells all formed inside the N-type epitaxial layer with the two N-type wells respectively arranged at two sides of the P-type well; a first semiconductor area, a second semiconductor area and a third semiconductor area all formed inside the P-type well and all coupled to an anode, wherein the second semiconductor area and the third semiconductor area are respectively arranged at two sides of the first semiconductor area, and wherein the first semiconductor area is of first conduction type, and the second semiconductor area and the third semiconductor area are of second conduction type; and two P-type doped areas respectively formed inside the N-type wells, wherein each P-type doped area has a fourth semiconductor area neighboring the P-type well and a fifth semiconductor area, and wherein both the fourth semiconductor area and the fifth semiconductor area are coupled to a cathode, and wherein the fourth semiconductor area is of second conduction type, and the fifth semiconductor area is of first conduction type.

The invention provides an array substrate, a fabricating method for the same and a liquid crystal display panel. The array substrate comprises a display area and a frame area enclosing the display area, and the display area comprises a plurality of data lines and a plurality of scanning lines, a plurality of pixel areas in array arrangement and a plurality of scanning connection lines, wherein the data lines and the scanning lines are orthogonal and insulated to one another and divide the display area into the pixel areas, each pixel area comprises a pixel electrode and a thin film transistor, the scanning connection lines are parallel to the data lines and used for electrically connecting the corresponding scanning lines with external driving chips. The scanning connection lines are arranged in the display area, and the scanning connection lines are used for transmitting signals by scanning a drive circuit to the corresponding scanning lines, so that the area of the scanning connection lines in a frame area is economized, and the utilization ratio of the substrate is improved.

A data communication system includes a transmitter unit and a receiver unit. The transmission unit has a transmission characteristic that is adjustable in accordance with equalization information. The transmission unit is operable to transmit a predetermined signal and the receiver unit is operable to receive the predetermined signal. The receiver unit is further operable to generate the equalization information by examining the eye opening of the received signal, and to transmit the equalization information to the transmitter unit.

An improved APB bus bridge structurally comprises an AHB bus interface and an APB bus interface and further comprises an interface sequential conversion and control module, a control FIFO (First In First Out) module and a data FIFO module, wherein the interface sequential conversion and control module comprises a state machine, a data FIFO control logic unit and a control FIFO control logic unit and a register. A control method of the improved APB bus bridge comprises the following steps: generating a ready signal by the APB bus bridge; determining that the ready signal has a high level, and autonomously sending a transmission request by an AHB bus master; receiving and judging the transmission request by the APB bus bridge, wherein if the transmission request is effective, a control signal and data of the transmission request are stored in the corresponding FIFO modules respectively and the APB bus bridge does not distinguish read and write transmissions; and through state conversion and control of the state machine of the interface sequential conversion and control module, after finishing sequential matching conversion of the two buses, quickly carrying out reliable transmission operation. The improved APB bus bridge is applicable to sequential synchronous and asynchronous AHB-to-APB bus transmission and is compatible with a memory interface.

A display device having an electrostatic capacity touch panel includes: X electrodes XP and Y electrodes YP which intersect each other via a first insulating layer; and a plurality of Z electrodes disposed in a floating state via a second insulating layer. For the second insulating layer, a material such as an elastic insulating material which changes in thickness by pressing of touch is used. The Z electrode is disposed so as to overlap both one of the X electrodes and one of the Y electrodes. A pad part of the X electrode has a largest area in the vicinity of a thin line part of the X electrode, and a smallest area in the vicinity of the thin line part of the adjacent X electrode. An area of the pad part is reduced as the pad part departs from the thin line part of the X electrode.

p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.

A high-performance optical device is provided. An optical device includes a first transmitting portion that is disposed at the center of a predetermined area in a first substrate, a light-receiving portion that receives light passing through the first transmitting portion, N light-emitting portions (N is an integer of 2 or more) that are disposed around the first transmitting portion in the predetermined area, and a control circuit that controls the light-emitting portions. The control circuit is functionally divided into N control portions, namely, first to N-th control portions. The N control portions are disposed in areas overlapping the N light-emitting portions, respectively, when viewed from above. The optical device can reduce noise light and achieve a high S/N ratio, and also the sensitivity of the optical device can be improved.

The invention provides an LED pixel arrangement structure, a printing type display device with the LED pixel arrangement structure and a preparation method of the display device, and suitable for the field of display technology. The LED pixel arrangement structure comprises multiple pixel units, each pixel unit comprises four different colors of sub pixels, namely a red sub pixel R, a green sub pixel G, a sky blue sub pixel B1 and a dark blue sub pixel B2, the sub pixels of four different colors in the same pixel unit are in 2*2 rectangular arrangement, a random vertical side of the 2*2 rectangle is used to construct a reference axis of the x-y system, the pixel unit are in mirror symmetry in the axis x and axis y directions, and the sub pixels of the same color of connected pixel units form a same-color sub pixel area in 2*2 arrangement.

A compound light-emitting diode (LED) device includes a semiconductor substrate having an active electronic circuit formed in or on the semiconductor substrate. Two or more electrically conductive circuit connection pads are formed in or on the semiconductor substrate and are electrically connected to the active electronic circuit. One or more micro-transfer printed LEDs each have at least two LED electrodes or connection pads and a fractured LED tether. An adhesive layer is disposed between the semiconductor substrate and each LED to adhere the semiconductor substrate to the LED. Two or more electrical conductors electrically connect one of the electrodes or LED connection pads to one of the circuit connection pads.

The invention relates to a capacitive triaxial acceleration transducer with a single mass block and a preparation method thereof. A mass block region and a comb structure region are formed on a substrate, wherein, the mass block region comprises a first conducting layer, a socle beam which is positioned on the first conducting layer and is in fulcrum connection with the substrate, and a first block and a second movable block which are respectively connected with the two sides of the socle beam; the movable blocks and the first conducting layer form a differential capacitor used for measuring the accelerated speed in the first direction; the comb structure region is formed on the same layer with the mass block region, which comprises a first group of comb structure which is formed on the outer side of the second movable block and is used for measuring the accelerated speed in the second direction, and a second group of comb structure which is symmetrically formed on the opposite two natural sides of any movable block and is used for measuring the accelerated speed in the third direction; and furtherer more, the gravity of a combined region formed by the mass block region and the comb structure region deviates from the socle beam; therefore, the triaxial acceleration transducer formed by adopting the single mass block can realize the function of measuring the vector acceleration.

The invention discloses an ultra-junction vertical double-diffused metal-oxide transistor which comprises an N-type doped silicon substrate, an N-type doped silicon epitaxial layer, a primitive cell area, a terminal area arranged on the periphery of the primitive cell area and a transition area which is positioned between the primitive cell area and the terminal area; the N-type doped silicon epitaxial layer is arranged on the N-type doped silicon substrate; the primitive cell area and the terminal area are arranged on the N-type doped silicon epitaxial layer; the terminal area of the transistor comprises a first ultra-junction structure and an N-type silicon doped semiconductor area, wherein the first ultra-junction structure comprises an N-type column and a P-type column; a lateral P-type column and an N-type area with high-concentration are arranged in the N-type silicon doped semiconductor area; an N-type thin layer with high-concentration is arranged on the surfaces of the first ultra-junction and the N-type silicon doped semiconductor area; and a field oxide layer is arranged on the N-type thin layer. The ultra-junction vertical double-diffused metal-oxide transistor is characterized in that: the lateral P-type column is arranged in the N-type silicon doped semiconductor area and the N-type thin layer with high-concentration is arranged on the surface of the terminal area of the transistor.

The invention provides a phase-change energy storage bedding system. The system comprises a bedding module, an energy supply module and an energy transfer module. The energy transfer module transfersenergy of the energy supply module to the bedding module; the bedding module comprises a phase-change material and a heat conducting component, wherein the heat conducting component is used for transferring the energy provided by the energy supply module to the phase-change material; the energy supply module comprises daily equipment, and the daily equipment generates waste heat; the energy transfer module comprises a heat pump system, in winter, the heat pump system is used for transferring the energy of the energy supply module or complementing waste heat, and increasing the grade of the waste heat, and the heat of the increased grade is transferred to the heat conducting component. In summer, needed cooling capacity is produced in a free cooling capacity recovery mode, an operation modeof combination with a refrigerating system and an independent operation mode of the refrigerating system. In this way, in winter, the phase-change energy storage bedding system can recover the wasteheat of the daily equipment and increase the grade of the waste heat to heat a human body; in summer, free cooling capacity can be recovered from outdoor air or the needed cooling capacity is preparedthrough a refrigerating cycle, so that the human body is cooled.

The invention discloses an embedded type touch screen and a display device. As each self-capacitance electrode is provided with a plurality of hollow areas, the area of each self-capacitance electrode can be reduced, and natural capacitance of each self-capacitance electrode is reduced; if it is assumed that the finger capacitance is unchanged in the touching process, the capacitance on each self-capacitance electrode, namely, the sum of the natural capacitance and the finger capacitance is decreased relatively, and therefore RC delay of a feedback signal on each self-capacitance electrode can be reduced; moreover, the change amount of the capacitance on each self-capacitance electrode before and after touching is carried out is increased relative to the natural capacitance of each self-capacitance electrode, relatively, the change amount of each feedback signal caused by the finger is increased, and therefore the touch sensitivity of the touch screen is improved; in addition, as the hollow areas are arranged in the self-capacitance electrodes to reduce the area of the self-capacitance electrodes, a touch blind area between every two adjacent self-capacitance electrodes and the number of the self-capacitance electrodes do not need to be increased, and it is ensured that on the basis of the narrow-border design, the touch sensitivity of the touch screen is improved.

The embodiment of the invention provides a display panel. The display panel comprises: a display area and a through hole arranged around the display area; scanning lines arranged in a first directionand a second direction; and data line arranged in the second direction and the first direction, wherein the data lines comprise at least one first data line, the first data line comprises a first linear portion and a first winding portion arranged around the through hole; and the display panel further comprises frame package glue round the through hole, and the first winding portion is coated withthe frame package glue. The first winding portion is arranged at the position where the first winding portion is overlapped with the frame package glue so as to reduce the width of the winding, reduce the area of the non-display portion round the hole and improve the screen-to-body ratio of the display panel.

A Group III nitride semiconductor light-emitting device includes an electrically conductive support; a p-electrode provided on the support; a p-type layer, an active layer, and an n-type layer, which are formed of a Group III nitride semiconductor and are sequentially provided on the p-electrode; an n-electrode which is connected to the n-type layer; a first trench extending from the surface of the p-type layer on the p-electrode's side to reach the n-type layer; an auxiliary electrode which is in contact with the surface of the n-type layer serving as the bottom of the first trench, but is not in contact with the side walls of the first trench; and an insulating film which exhibits light permeability and covers the auxiliary electrode and the bottom and side walls of the first trench.

Photoelectric conversion elements suitable for various applications and related components, and methods associated therewith, are described. A photoelectric conversion element may include a catalyst layer having at least two portions that are spaced from one another, and a current collector having a tip portion that extends toward or within the space between portions of the catalyst layer. A photoelectric conversion element may also include a semiconductor layer disposed a distance of between about 5 microns and about 20 microns away from the catalyst layer.

The invention provides an in-cell touch display panel comprising an active component array substrate, opposite substrates and a display dielectric layer. The active component array substrate comprises a plurality of active components, a plurality of pixel electrodes, a first insulating layer, a conducting layer, a plurality of second insulating layers and a plurality of common electrodes. The conducting layer comprises a plurality of connection pads and a plurality of first connecting wires. The first connecting wires extend in a first direction, are located in a display area and are connected with the corresponding connection pads. The second insulating layers are disposed on the conducting layer and comprise a plurality of contact windows. The common electrodes are disposed on the second insulating players and are arranged into a plurality of common electrode serials extending in a second direction. More than two common electrode serials are connected to so that first electrode wires with the number of N, which are arranged in order in the second direction, are formed. The Jth first connecting wire is connected to the Kth first electrode wire through the corresponding contact window.

A semiconductor memory device including a weak cell storage circuit suitable for programming therein weak cell information, and outputting the weak cell information in an initialization operation; a cell array region including a first cell region which stores the weak cell information received from the weak cell storage circuit, in the initialization operation; a refresh address generation block suitable for generating a refresh address by counting a refresh signal, and outputting a weak cell address corresponding to the weak cell information outputted from the first cell region, as the refresh address, with a predetermined cycle; and a refresh circuit suitable for performing a refresh operation for a word line corresponding to the refresh address, among a plurality of word lines.

An improved circuit wiring layout provides smooth circuit wiring in a peripheral circuit region adjacent to a memory cell region of a semiconductor memory device, and eliminates a write-speed limiting factor. Forming a metal (instead of a metal silicided polysilicon) wiring layer to be connected to a gate layer, to transmit an electrical signal to the gates of FET (e.g., MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistors formed in the peripheral circuit region; the metal wiring layer is formed (e.g., using one metal damascene process), on a layer different from a word line layer formed on the gate layer (e.g., using another metal damascene process), thereby obtaining a layout of a peripheral circuit region having a reduced area and without using a silicide process.

A multi-chip system and a boot code fetch method include a nonvolatile memory chip storing a volatile memory chip, and a boot code, and a host fetching the boot code. The boot code is transferred to the volatile memory chip before the host fetches the boot code in the nonvolatile memory chip, and the boot code is fetched in the volatile memory chip. Therefore, a bootRAM of the conventional nonvolatile memory chip may be removed, so that an area of the nonvolatile memory chip can be reduced.

The distortion correction is carried out by acquiring the calibration pattern image by an imaging device and executing calibration based on the acquired calibration pattern image. A plurality of calibration pattern images in which feature points arranged in an imaging range from which images can be picked up by the imaging device are provided at a regular interval is acquired, and a feature point group is extract from each image. The calibration is executed based on the feature point groups respectively extracted from areas with different imaging ranges.

The invention discloses a display panel which comprises color film substrates, array substrates and electrically conductive components. The array substrates are opposite to the color film substrates. The electrically conductive components comprise fixed ends and movable ends, the fixed ends are opposite to the movable ends, are positioned between the array substrates and the color film substrates and are electrically connected with the array substrates, and the movable ends extend out of spaces between the array substrates and the color film substrates and are used for binding circuit boards. The invention further discloses electronic equipment and a method for manufacturing the display panel. The display panel, the electronic equipment and the method have the advantage that the display panel is provided with narrow frames.

A generator-motor includes an alternator, electrode plates, a substrate, MOS transistors, and an MOS driver. Electrode plates are arranged on an end surface of the alternator so as to substantially form a U-shape to surround a rotation shaft of the alternator. MOS transistors are arranged on the electrode plate, while MOS transistors are arranged on the electrode plates respectively. The MOS driver is provided on the substrate arranged in a substantially U-shaped notch, and controls turn-on/off of the MOS transistors.

The invention discloses a packaging structure with an antenna and a manufacturing method thereof. The method comprises the following steps of: forming a circuit diagram and an integrated circuit (IC) chip on a substrate, wherein the IC chip is electrically connected with the circuit diagram; covering a package on the substrate to wrap the circuit diagram and the IC chip; and forming an antenna diagram on the package, wherein the antenna diagram is electrically connected with the circuit diagram by using a first through hole passing through the package. Therefore, the antenna can be formed on the package of the circuit board, and the purpose of reducing the area of a circuit board is reduced.

The invention discloses an online detection fault-tolerance system of an FPGA (Field programmable Gate Array) digital sequential circuit of an SRAM (Static Random Access Memory) type and a method. The method comprises the following steps of: respectively dividing the sequential circuit for detection and fault-tolerance into combinational logics and sequential logics; respectively carrying out triplication redundancy and majority voting to the combinational logics and the sequential logics to cover failures and obtain a redundant sequential circuit, dividing the redundant sequential circuit in the physical structure into three independent dynamic reconstruction regions and a static region and macro-processing the communication between the dynamic reconstruction regions and the static region with a bus; and respectively physically restraining the three redundant combinational logics to the three independent dynamic reconstruction regions and physically restraining the three redundant sequential logics to the static region. Compared with the prior art, the invention combines two-stage redundancy and reconfiguration technologies, not only can improve the system reliability, but also can reduce implementation resources and decrease the power consumption of a designed circuit.

A universal fixture for ultrasonic cleaning to film coated substrate is composed of sliding and fixed rectangular frames with 4 holes at 4 corners, 4 slide rods inserted in said 4 holes, several clampers, and several water-through supporting rods.

A stacked memory comprises one or more memory core chips and a fuse chip. Each of the memory core chips has a memory cell array including spare memory cells for replacing defective memory cells. The fuse chip has a fuse unit including a plurality of fuse elements whose electrical cut state corresponding to a replacement with the spare memory cells can be set. Also the fuse chip has a redundancy cell control circuit for controlling a redundancy cell operation of the defective memory cells based on state information of the fuse unit.