13 results about "Antifuse" patented technology

The present invention provides a non-volatile semiconductor memory device and a current-assisted voltage-controlled resistor that can supply an optimal voltage to each memory cell according to the state of the memory cell. [Solution] The non-volatile semiconductor memory device has a resistor element 10 and a current assist element arranged in parallel between the first voltage control line VCL1 and the second voltage control line VCL2, so that the optimal voltage can be supplied to each antifuse memory M arranged in the row direction via either the resistor element 10 or the current assist element depending on the state of the antifuse memory M.

This disclosure provides an antifuse circuit, including: an antifuse unit; a programming circuit connected to the antifuse unit, the programming circuit being used to program the antifuse unit according to a programming control signal and a programming signal; a reading unit being used to read data signals from the antifuse unit; and a verification control unit being used to control the reading unit to electrically connect to the antifuse unit according to a verification enable signal and the programming signal of the antifuse unit when verifying the programming status of the antifuse unit. The antifuse circuit, by controlling the reading unit to electrically connect to the antifuse unit according to the verification enable signal and the programming signal of the antifuse unit when verifying the programming status of the antifuse unit, achieves real-time verification of the programming status.

The embodiments of the present disclosure disclose a structure of an anti-fuse cell, an anti-fuse array and an operation method thereof, and a memory, wherein the structure of the anti-fuse cell comprises: a first anti-fuse transistor having a first end and a second end; a first selection transistor having a first end and a second end, the first end of the first selection transistor being electrically connected to the second end of the first anti-fuse transistor; and an enable signal line being electrically connected to the first end of the first anti-fuse transistor, the enable signal line being used for programming operation of the first anti-fuse transistor.

The present invention is a programming control circuit for an array of anti-fuse one-time-programmable (OTP) memory cells. During a programming operation, the programming control circuit monitors the programming current of the anti-fuse OTP memory cells and increases the programming voltage in a timely manner. When the programming control circuit confirms that the anti-fuse OTP memory cells generate sufficient programming current, the programming control circuit confirms that the programming operation is complete.

An anti-fuse device includes an anti-fuse cell and a sensing circuit. The anti-fuse cell includes a first anti-fuse and a second anti-fuse that are connected in series between a first end of the anti-fuse cell and a second end of the anti-fuse cell. The sensing circuit is coupled to the first end and the second end of the anti-fuse cell to sense a programmed state of the anti-fuse cell.

The present disclosure relates to the technical field of semiconductor, and provides a method for detecting anti-fuse, a method for fusing, and a chip. The method for detecting anti-fuse comprises: obtaining measured resistances of a to-be-detected anti-fuse at multiple different temperatures; judging a correlation between the measured resistance and the temperature of the to-be-detected anti-fuse; judging whether the to-be-detected anti-fuse is completely fused according to the correlation between the measured resistance and the temperature of the to-be-detected anti-fuse; and when the measured resistance and the temperature of the to-be-detected anti-fuse are positively correlated, judging that the to-be-detected anti-fuse is completely fused. The method for detecting anti-fuse can accurately judge whether the to-be-detected anti-fuse is completely fused.

A semiconductor device has an active region on a front face of the semiconductor. The active region includes an antifuse control cell with several first transistors. The semiconductor device has a front-facing metallization layer connected to the several first transistors. The semiconductor device has a one-time programmable circuit on a rear face. The one-time programmable circuit has a second transistor connected to a programming word line (WLP) of the antifuse control cell. The one-time programmable circuit has a third transistor connected to a read word line (WLR) of the antifuse control cell. The semiconductor device has a rear-facing metallization layer connected to the second and third transistors.

Because OTP (One Time Programmable) memory, which consists of an antifuse element or a fuse element, lacks a write control function, there is a risk of writing incorrect information due to accidental operation or ESD. [Solution] A memory device having first and second semiconductor memory circuits, each containing a memory element that can be written to only once, characterized in that information stored in the second semiconductor memory circuit is written to the memory element of the first semiconductor memory circuit.

The embodiment of the present disclosure provides a kind of anti-fuse circuit, it includes: anti-fuse unit;Burn write circuit, for the anti-fuse unit is burned according to burn write signal;Verification unit includes first input, second input and first output, the burn write signal of the anti-fuse unit is as the input signal of the first input, the data signal stored in the anti-fuse unit is as the input signal of the second input, the verification unit can verify the burn write state of the anti-fuse according to the input signal of the first input and second input, and the first output is used to output verification signal.The anti-fuse circuit provided in the embodiment of the present disclosure does not need to read out the data signal of anti-fuse unit to testing machine again to verify the burn write state of anti-fuse unit, save time, and verification accuracy is high.

The application provides a kind of antifuse memory, the reverse input end of operational amplifier is connected with the feedback end of bias voltage generation module, and the second input end voltage can be obtained according to the feedback end voltage, the second input end is electrically connected with the output end of operational amplifier, and the second input end voltage is used as the bias voltage of reading circuit;The circuit between the second power supply end and the feedback end is equivalent to the circuit between the first power supply end and the monitoring end, the circuit between the feedback end and the adjustable resistance is equivalent to the circuit between the monitoring end and the antifuse memory unit, in this way, the bias voltage generated by bias voltage generation module can effectively provide accurate bias voltage for reading module.After reading module receives bias voltage, if the breakdown resistance value of antifuse memory unit is equal to the adjustable resistance value, the critical voltage of monitoring end is equal to the reverse voltage;According to the state of level signal output by reading module, the relationship between monitoring end voltage and reverse voltage can be judged, and then whether antifuse memory unit is effectively broken down can be judged.

One-time programmable (OTP) bit-cell for an integrated circuit (IC) that includes an OTP element, such as a fuse or antifuse, coupled in electrical series with a selector that comprises a Schottky junction. The selector may comprise a metal-semiconductor-metal (MSM) material stack operable as transient voltage suppression (TVS) device that experiences electrical breakdown at a voltage below a programming voltage of the OTP element. In response to a programming voltage, the MSM stack may breakdown and pass a transient current sufficient for programming the OTP element. In response to a lower (e.g., read) voltage, the MSM stack may breakdown and pass a transient current insufficient for programming, but sufficient to sense a state of the OTP element. In response to an even lower (e.g., half-read) voltage, the MSM stack may present a very high OTP bit-cell input impedance, reducing leakage and / or sneak path currents within an array of such bit-cells.

An electrical antifuse bit cell structure includes a silicon controlled rectifier (SCR) having an anode, a cathode, and a blow gate. The blow gate is a Positive Field Effect Transistor (PFET) having a supply node for connection in series between a voltage supply and the anode of the SCR. The blow gate PFET in an on-state provides a permanent conductive path from the anode to the cathode.