81 results about "Antifuse" patented technology

A memory device includes an anti-fuse memory cell that randomly presents either a first logic state or a second logic state. The memory cell is formed on a frontside of a substrate and at least includes a first programming transistor that is formed in a first one of a plurality of metallization layers disposed over the frontside and gated by a first programming word line, and a first reading transistor that is formed in a second one of the plurality of metallization layers disposed over the frontside or along a major surface on the frontside, coupled to the first programming transistor and a first bit line in series, and gated by a first reading word line.

A method includes: forming a first transistor and a second transistor, each of the first transistor and the second transistor having a source terminal, a drain terminal, and a gate terminal; forming a word line conductor electrically connected to the gate terminal of the first transistor and the gate terminal of the second transistor; forming a program line conductor; and forming a vertically stacked dual anti-fuse element, including: forming a first metal plate, a second metal plate, and a third metal plate stacked over the first transistor and the second transistor and separated from each other by insulators; and electrically connecting the source terminal of the first transistor to the first metal plate, the source terminal of the second transistor to the third metal plate, and the program line conductor to the second metal plate.

The present invention provides a recording head that can update eigenvalues ​​while suppressing increases in memory capacity and head size. [Solution] The recording head 810 has a memory section 20 configured using a fuse element or an antifuse element. The memory section 20 has a main memory circuit M0 for storing eigenvalues ​​related to the recording head 810, and correction memory circuits M1 and M2 for storing correction values ​​for updating the eigenvalues.

A non-volatile memory device includes a substrate, a stack structure that includes a first gate layer that extends in a horizontal direction and a second gate layer that extends in the horizontal direction and is disposed apart from the first gate layer in a vertical direction, a plurality of first channel structures that penetrate in the vertical direction through a first channel region of the stack structure, a plurality of second channel structures that penetrate in the vertical direction through a second channel region of the stack structure, a first anti-fuse structure and a second anti-fuse structure that each penetrate in the vertical direction through an anti-fuse region of the stack structure, a first anti-fuse transistor that is electrically connected to the first gate layer through the first anti-fuse structure, and a second anti-fuse transistor that is electrically connected to the second gate layer through the second anti-fuse structure.

An anti-fuse circuit includes a current generator and an anti-fuse sensing unit. The current generator has at least one replica electronic element. The anti-fuse sensing unit is electrically connected to the current generator, and the anti-fuse sensing unit has at least one electronic element. The electronic element specification of the at least one electronic element of the anti-fuse sensing unit is the same as the electronic element specification of the at least one replica electronic element of the current generator. The current generator supplies current to the anti-fuse sensing unit to sense the anti-fuse. By means of the technical solution of the present application, the anti-fuse circuit can improve the accuracy of sensing the anti-fuse.

The present invention provides a non-volatile semiconductor memory device and a current-assisted voltage-controlled resistor that can supply an optimal voltage to each memory cell according to the state of the memory cell. [Solution] The non-volatile semiconductor memory device has a resistor element 10 and a current assist element arranged in parallel between the first voltage control line VCL1 and the second voltage control line VCL2, so that the optimal voltage can be supplied to each antifuse memory M arranged in the row direction via either the resistor element 10 or the current assist element depending on the state of the antifuse memory M.

A non-volatile memory device includes a substrate, a stack structure that includes a first gate layer that extends in a horizontal direction and a second gate layer that extends in the horizontal direction and is disposed apart from the first gate layer in a vertical direction, a plurality of first channel structures that penetrate in the vertical direction through a first channel region of the stack structure, a plurality of second channel structures that penetrate in the vertical direction through a second channel region of the stack structure, a first anti-fuse structure and a second anti-fuse structure that each penetrate in the vertical direction through an anti-fuse region of the stack structure, a first anti-fuse transistor that is electrically connected to the first gate layer through the first anti-fuse structure, and a second anti-fuse transistor that is electrically connected to the second gate layer through the second anti-fuse structure.

The present invention provides a semiconductor device that allows for easy determination of the remaining number of rewrites in a counter circuit and whether or not the upper limit has been reached. [Solution] The semiconductor device is configured by combining an antifuse element A and fuse elements F1 and F2, and includes a counter circuit CM1 in which a count value is set by the combination of the conduction state and non-conduction state of the fuse elements F1 and F2 and the antifuse element A. The count value set in the counter circuit CM1 is incremented by sequentially rewriting the fuse elements F1 and F2 from the conduction state to the non-conduction state and the antifuse element A from the non-conduction state. The counter circuit CM1 has an output unit 10 that outputs a signal corresponding to the combination of the conduction state and non-conduction state of the fuse elements F1 and F2 and the antifuse element A.

The invention relates to an anti-fuse memory and a programming method thereof, the anti-fuse memory comprises an anti-fuse memory array, the anti-fuse memory array comprises a plurality of anti-fuse memory cells, each anti-fuse memory cell comprises an anti-fuse transistor, and the anti-fuse memory array further comprises a bit line; and the feedback network is connected between the bit line and at least one anti-fuse storage unit, and the feedback network is used for disconnecting the bit line and the anti-fuse storage unit when detecting that the magnitude of current between the bit line and the anti-fuse storage unit connected with the bit line meets a preset condition. According to the invention, multiple bits can be programmed at the same time, and unnecessary programming current can be eliminated, so that the power consumption is reduced.

An anti-fuse memory cell, an anti-fuse memory array and a memory, the anti-fuse memory cell comprising: an anti-fuse structure having a first end and a second end; the selection transistor comprises a drain electrode and a source electrode, and one of the drain electrode and the source electrode is coupled with the first end of the anti-fuse structure; and the anode of the voltage stabilizing diode is coupled with the other one of the drain electrode and the source electrode. According to the embodiment of the invention, the voltage stabilizing diode is additionally arranged in the anti-fuse memory cell and is connected with the selection transistor in series, the voltage stabilizing diode can provide stable voltage for the selection transistor, interference caused by current fluctuation can be resisted, correspondingly, the selection transistor can provide stable current for the anti-fuse structure, and the anti-fuse memory cell is more stable in performance. Therefore, the programming reliability of the anti-fuse structure is improved.

A secure anti-fuse one-time programmable (OTP) bit cell is disclosed. In one aspect, the OTP bit cell includes: a P well including an N + region and a P + region; a first contact electrically coupled to the N + region of the P well; a second contact electrically coupled to the P + region of the P well; an insulating layer disposed over a portion of the N + region, a portion of the P well, and a portion of the P + region; a gate structure disposed over the insulating layer; and a third contact electrically coupled to the gate structure. In the unprogrammed mode, the insulating layer produces a high resistance between the third contact and the second contact, and in the programmed mode, a fracture in the insulating layer produces a low resistance between the third contact and the second contact.

The invention relates to an anti-fuse nonvolatile memory and a driving circuit thereof. The anti-fuse nonvolatile memory comprises a memory cell array, a driving circuit, a first power supply and a second power supply. The memory cell array includes a first sub-array and a second sub-array. All memory cells of the first sub-array are connected to the first anti-fuse control line and the first following control line. All memory cells of the second sub-array are connected to the second anti-fuse control line and the second following control line. A first voltage provided by the first power supply is output to the first anti-fuse control line and the second anti-fuse control line through the first anti-fuse control line driver and the second anti-fuse control line driver of the driving circuit. A second voltage provided by the second power supply is directly output to the first following control line and the second following control line.

A method of making a memory device includes forming an array of memory cells distributed along a first direction and a second direction perpendicular to the first direction, forming a first programming gate-strip extending in the second direction, and forming a plurality of first programming conducting lines extending in the first direction. Each of the memory cells includes an anti-fuse structure having a dielectric layer overlaying a semiconductor region in an active zone, and a transistor having a channel region in the active zone. The active zone extends in the first direction. Each of the plurality of first programming conducting lines is electrically connected connected to the first programming gate-strip through a corresponding resistor of a first plurality of resistors. The first programming gate-strip electrically connects to the anti-fuse structure of each of the memory cells along a column of the array of memory cells.

This disclosure provides an antifuse circuit, including: an antifuse unit; a programming circuit connected to the antifuse unit, the programming circuit being used to program the antifuse unit according to a programming control signal and a programming signal; a reading unit being used to read data signals from the antifuse unit; and a verification control unit being used to control the reading unit to electrically connect to the antifuse unit according to a verification enable signal and the programming signal of the antifuse unit when verifying the programming status of the antifuse unit. The antifuse circuit, by controlling the reading unit to electrically connect to the antifuse unit according to the verification enable signal and the programming signal of the antifuse unit when verifying the programming status of the antifuse unit, achieves real-time verification of the programming status.

The invention discloses an anti-fuse trimming circuit and an integrated circuit with the anti-fuse trimming circuit, and belongs to the field of integrated circuit design, and the anti-fuse trimming circuit comprises an anti-fuse MOS (Metal Oxide Semiconductor) tube, an inverse ratio MOS tube, a first selection MOS tube and a second selection MOS tube; one end of the anti-fuse MOS tube is connected with the high-level input end, and the other end of the anti-fuse MOS tube is connected with the trimming output end; the second current end is grounded, and the gate end is a control end; a first current end of the first selection MOS tube is connected with a trimming output end, and a second current end of the first selection MOS tube is connected with a first current end of the enabling MOS tube; a second current end of the second selection MOS tube is grounded; the gate end of the first selection MOS tube is connected with a selection signal input end, and the gate end of the second selection MOS tube is connected with an enable signal input end; or, the gate end of the second selection MOS tube is connected with the selection signal input end, and the gate end of the first selection MOS tube is connected with the enable signal input end. Compared with the prior art, the area of a chip is greatly reduced.

Memory devices, and associated systems and methods, are disclosed herein. A representative memory device comprises a substrate, an insulative layer over the substrate, and a memory array over the insulative layer. The memory device further comprises a fuse array positioned in the insulative layer and configured as a non-volatile memory that can store trimming and / or other factors. The fuse array can comprise a plurality of transistors configured as fuses and each including a source, a drain, and a gate. The transistors in a first subset of the transistors have a first resistance across one of the source, the drain, and the gate that represents a first logic state, and the transistors in a second subset of the transistors can have a second resistance across the one of the source, the drain, and the gate that is greater than the first resistance and that represents a second logic state.

The embodiment of the present application relates to the field of semiconductor circuit design, in particular to a kind of anti-fuse array structure and memory, comprising: a plurality of anti-fuse integrated structure, in bit line extension direction and word line extension direction arrangement into anti-fuse matrix, bit line extension direction and word line extension direction perpendicular to each other;Each anti-fuse integrated structure is connected with two programming wires and two word lines;In the extension direction of word line, each anti-fuse integrated structure and adjacent anti-fuse integrated structure are connected with same programming wire and word line;In the extension direction of bit line, each anti-fuse integrated structure and adjacent anti-fuse integrated structure are connected on one of programming wire.By providing a new layout mode of anti-fuse array, to realize the same capacity of storage array only needs to occupy smaller layout area, thereby increasing the spacing between anti-fuse memory cells on the basis of original layout area, guarantee the electrical isolation effect of electrical element between anti-fuse memory cells.

An antifuse-type non-volatile memory cell includes a select transistor, a following transistor and a capacitor. The first drain / source terminal of the select transistor is connected with a bit line. The gate terminal of the select transistor is connected with a word line. A first drain / source terminal of the following transistor is connected with a second drain / source terminal of the select transistor. A gate terminal of the following transistor is connected with a following line. A second drain / source terminal of the following transistor is connected with a first terminal of the capacitor. A second terminal of the capacitor is connected with an antifuse control line.

The embodiments of the present disclosure disclose a structure of an anti-fuse cell, an anti-fuse array and an operation method thereof, and a memory, wherein the structure of the anti-fuse cell comprises: a first anti-fuse transistor having a first end and a second end; a first selection transistor having a first end and a second end, the first end of the first selection transistor being electrically connected to the second end of the first anti-fuse transistor; and an enable signal line being electrically connected to the first end of the first anti-fuse transistor, the enable signal line being used for programming operation of the first anti-fuse transistor.

An antifuse one-time programmable memory bit cell comprises a metal-oxide-semiconductor (MOS) gate electrode and diffusions formed in an isolated well. The surface of the isolated well under the MOS gate electrode is the drain, the bottom portion of the isolated well is the source of a vertical junction field-effect transistor (JFET), and the diffusions are the JFET gate. The MOS gate electrode is the word line, and the diffusions are the bit line. The vertical JFET is turned on or off by a voltage applied to the JFET gate and functions as a bit cell selector device.

This application discloses a semiconductor device, a memory, a printhead, and a consumable cartridge. The semiconductor device includes a semiconductor substrate and a transistor, an antifuse element, a resistor element, a first terminal, and a second terminal disposed on the semiconductor substrate. The transistor is connected to the first terminal. The antifuse element is connected between the transistor and the second terminal via a first wiring and a third wiring. The resistor element is connected in parallel with the antifuse element between the transistor and the second terminal via a second wiring and a fourth wiring. The first and third wirings are both referred to as antifuse wirings, and the second and fourth wirings are both referred to as resistor wirings. At least one antifuse wiring is arranged in a first stacked structure, and / or, at least one resistor wiring and its corresponding antifuse wiring are arranged in a second stacked structure. This application enables a larger wiring space for the resistor wirings, thereby increasing the resistance of the resistor wirings and improving data reading accuracy.

The present invention is a programming control circuit for an array of anti-fuse one-time-programmable (OTP) memory cells. During a programming operation, the programming control circuit monitors the programming current of the anti-fuse OTP memory cells and increases the programming voltage in a timely manner. When the programming control circuit confirms that the anti-fuse OTP memory cells generate sufficient programming current, the programming control circuit confirms that the programming operation is complete.

Embodiments relate to an anti-fuse array and a memory. The anti-fuse array includes: a column of first active areas, where each of the first active areas includes a first channel region, a first source / drain region and a second source / drain region, and a first programming region; a column of second active areas, where each of the second active areas includes a second channel region, a third source / drain region and a fourth source / drain region, and a second programming region, an end portion, close to the first active areas, of the given second active area directly faces a region between end portions, close to the given second active area, of two adjacent first active areas; a first gate line; a second gate line covering each second channel region in a column of the second active areas; and a programming gate line.

The present disclosure discloses a one-time programmable (OTP) memory cell that includes an anti-fuse element and a selection circuit. The anti-fuse element includes a first terminal, a second terminal coupled to a program line, and a gate terminal. The selection circuit is coupled to a first end of the anti-fuse element, a word line and a bit line. The selection circuit controls the electrical connection between the bit line and the first end of the anti-fuse element according to the voltage of the word line. The one-time programmable memory cell is programmed by a program operation, and a channel between the first end and the second end of the anti-fuse element is compromised by the program operation.

The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes an anti-fuse unit, and the anti-fuse unit includes a selection unit and a memory cell. The semiconductor structure further includes: a substrate; a gate provided in the substrate, where in a cross section perpendicular to the substrate, the gate includes a first sidewall and a second sidewall opposite to each other; a first doped region, provided in the substrate and close to the first sidewall; a second doped region, provided in the substrate and close to the second sidewall; and an oxide layer, covering a partial surface of the gate. The gate, the first doped region and the oxide layer form the memory cell; the gate, the first doped region, the second doped region, and the oxide layer form the selection unit.

Provided is a storage device including a first antifuse element and a second antifuse element, and a supply line extending from a single power supply is branched into supply lines so that the respective supply lines are connected to the first antifuse element and the second antifuse element. A control circuit causes a voltage application to the first antifuse element and a voltage application to the second antifuse element to be alternately performed.

A semiconductor device includes a main transistor and an anti-fuse connected to one terminal of the main transistor, wherein the main transistor includes a main channel layer, a main gate electrode above the main channel layer, and a main source electrode and a main drain electrode on both sides of the main gate electrode and connected to the main channel layer, the anti-fuse includes a sub-channel layer, a sub-barrier layer above the sub-channel layer and including a material having a different energy band gap than the sub-channel layer, a sub-gate electrode above the sub-channel layer, a gate semiconductor pattern between the sub-channel layer and the sub-gate electrode, and a sub-source electrode above the sub-channel layer and on one side of the sub-gate electrode, and the main source electrode and the sub-gate electrode, or the main source electrode and the sub-source electrode are electrically connected to each other.

The application discloses an anti-fuse structure, a memory, a program operation and a read operation of the anti-fuse structure, the anti-fuse structure including: a first cell including a first MOS transistor and a data cell connected in series; a second cell including a second MOS transistor and a reference cell connected in series; the sensitive amplifier is respectively connected with the data unit and the reference unit; wherein the data unit comprises a plurality of anti-fuse storage units which are connected in parallel, and the reference unit comprises a plurality of anti-fuse storage units which are connected in parallel. The problem of increasing the breakdown voltage and improving the programming yield in the prior art is solved.