172 results about "Antifuse" patented technology

A current may be passed through a channel of an anti-fuse field-effect transistor (FET) to increase a temperature of a gate dielectric of the anti-fuse FET and change a rupture voltage of the gate dielectric of the anti-fuse FET from a first rupture voltage to a second rupture voltage. The gate dielectric may be ruptured by applying a first voltage between the gate dielectric and the channel of the anti-fuse FET, where the first voltage is between the first rupture voltage and the second rupture voltage.

A memory device includes a semiconductor substrate, an isolation structure, and an anti-fuse structure. The isolation structure is disposed in the semiconductor substrate. The anti-fuse structure is disposed in the isolation structure and includes a first electrode and a second electrode. The second electrode is disposed adjacent to the first electrode. Both of a top surface of the first electrode and a top surface of the second electrode are below a top surface of the semiconductor substrate.

This application discloses a one-time programmable memory cell, which includes one anti-fuse programmable transistor, one fuse, and two control transistors. One of a source end and a drain end of a first control transistor is connected to one of a source end and a drain end of the anti-fuse programmable transistor, and the other is connected to one of a source end and a drain end of a second control transistor and one end of the fuse. The other of the source end and the drain end of the second control transistor is connected to the ground. The one time programmable memory cell disclosed in this application can directly correct an error bit through reprogramming, can simplify circuit and layout design, requires a smaller layout area, and has higher reliability and safety.

A memory device includes an anti-fuse memory cell that randomly presents either a first logic state or a second logic state. The memory cell is formed on a frontside of a substrate and at least includes a first programming transistor that is formed in a first one of a plurality of metallization layers disposed over the frontside and gated by a first programming word line, and a first reading transistor that is formed in a second one of the plurality of metallization layers disposed over the frontside or along a major surface on the frontside, coupled to the first programming transistor and a first bit line in series, and gated by a first reading word line.

An antifuse-type one time programming memory includes a first memory cell. The first memory cell includes at least one antifuse transistor. The antifuse transistor is forksheet transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain / source structure and a second drain / source structure. A first-portion surface of the first nanowire is contacted with the isolation wall. A second-portion surface of the first nanowire is contacted with the first gate structure. The first gate structure includes a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain / source structure is electrically contacted with a first terminal of the first nanowire. The second drain / source structure is electrically contacted with a second terminal of the first nanowire.

A method includes: forming a first transistor and a second transistor, each of the first transistor and the second transistor having a source terminal, a drain terminal, and a gate terminal; forming a word line conductor electrically connected to the gate terminal of the first transistor and the gate terminal of the second transistor; forming a program line conductor; and forming a vertically stacked dual anti-fuse element, including: forming a first metal plate, a second metal plate, and a third metal plate stacked over the first transistor and the second transistor and separated from each other by insulators; and electrically connecting the source terminal of the first transistor to the first metal plate, the source terminal of the second transistor to the third metal plate, and the program line conductor to the second metal plate.

The present invention provides a recording head that can update eigenvalues ​​while suppressing increases in memory capacity and head size. [Solution] The recording head 810 has a memory section 20 configured using a fuse element or an antifuse element. The memory section 20 has a main memory circuit M0 for storing eigenvalues ​​related to the recording head 810, and correction memory circuits M1 and M2 for storing correction values ​​for updating the eigenvalues.

A memory device includes a programming gate-strip, a read gate-strip, and an array of one-bit memory cells. Each one-bit memory cell includes an anti-fuse structure, a transistor, a terminal conductor, a group of programming conducting lines, and a bit connector. The anti-fuse structure has a dielectric layer overlying a semiconductor region in an active zone at an intersection of the programming gate-strip and the active zone. The transistor has a channel region in the active zone at an intersection of the read gate-strip and the active zone. The terminal conductor overlies a terminal region of the transistor in the active zone. The group of programming conducting lines is conductively connected to the programming gate-strip through a group of one or more gate via-connectors. The bit connector is conductively connected to the terminal conductor through one or more terminal via-connectors.

An anti-fuse address decoding circuit includes: a pre-decoding circuit, configured to decode a programming address of an anti-fuse memory array and output a programming address pre-decoded signal; a level shift circuit, coupled to the pre-decoding circuit, and configured to boost the programming address pre-decoded signal and output a boosted signal; and a programming address decoding circuit, configured to receive the boosted signal, decode the boosted signal and output a programming address signal.

A non-volatile memory device includes a substrate, a stack structure that includes a first gate layer that extends in a horizontal direction and a second gate layer that extends in the horizontal direction and is disposed apart from the first gate layer in a vertical direction, a plurality of first channel structures that penetrate in the vertical direction through a first channel region of the stack structure, a plurality of second channel structures that penetrate in the vertical direction through a second channel region of the stack structure, a first anti-fuse structure and a second anti-fuse structure that each penetrate in the vertical direction through an anti-fuse region of the stack structure, a first anti-fuse transistor that is electrically connected to the first gate layer through the first anti-fuse structure, and a second anti-fuse transistor that is electrically connected to the second gate layer through the second anti-fuse structure.

An anti-fuse circuit includes a current generator and an anti-fuse sensing unit. The current generator has at least one replica electronic element. The anti-fuse sensing unit is electrically connected to the current generator, and the anti-fuse sensing unit has at least one electronic element. The electronic element specification of the at least one electronic element of the anti-fuse sensing unit is the same as the electronic element specification of the at least one replica electronic element of the current generator. The current generator supplies current to the anti-fuse sensing unit to sense the anti-fuse. By means of the technical solution of the present application, the anti-fuse circuit can improve the accuracy of sensing the anti-fuse.

A current may be passed through a channel of an anti-fuse field-effect transistor (FET) to increase a temperature of a gate dielectric of the anti-fuse FET and change a rupture voltage of the gate dielectric of the anti-fuse FET from a first rupture voltage to a second rupture voltage. The gate dielectric may be ruptured by applying a first voltage between the gate dielectric and the channel of the anti-fuse FET, where the first voltage is between the first rupture voltage and the second rupture voltage.

A semiconductor structure includes a substrate, an anti-fuse, first and second transistors, a contact structure, and a dielectric layer. The substrate includes a well region and first and second conductivity type doped regions in the well region, in which the second conductivity type doped region surrounds the first conductivity type doped region and includes a first portion and a second portion perpendicular to the first portion in a top view. The anti-fuse is in an anti-fuse region of the first conductivity type doped region. The first and second transistors are in the well region. The anti-fuse is disposed between the first and second transistors, and the anti-fuse is electrically connected to the first and second transistors. The contact structure is above the anti-fuse. The dielectric layer is between the contact structure and the anti-fuse region of the first conductivity type doped region.

The present invention provides a non-volatile semiconductor memory device and a current-assisted voltage-controlled resistor that can supply an optimal voltage to each memory cell according to the state of the memory cell. [Solution] The non-volatile semiconductor memory device has a resistor element 10 and a current assist element arranged in parallel between the first voltage control line VCL1 and the second voltage control line VCL2, so that the optimal voltage can be supplied to each antifuse memory M arranged in the row direction via either the resistor element 10 or the current assist element depending on the state of the antifuse memory M.

A non-volatile memory device includes a substrate, a stack structure that includes a first gate layer that extends in a horizontal direction and a second gate layer that extends in the horizontal direction and is disposed apart from the first gate layer in a vertical direction, a plurality of first channel structures that penetrate in the vertical direction through a first channel region of the stack structure, a plurality of second channel structures that penetrate in the vertical direction through a second channel region of the stack structure, a first anti-fuse structure and a second anti-fuse structure that each penetrate in the vertical direction through an anti-fuse region of the stack structure, a first anti-fuse transistor that is electrically connected to the first gate layer through the first anti-fuse structure, and a second anti-fuse transistor that is electrically connected to the second gate layer through the second anti-fuse structure.

The present invention provides a semiconductor device that allows for easy determination of the remaining number of rewrites in a counter circuit and whether or not the upper limit has been reached. [Solution] The semiconductor device is configured by combining an antifuse element A and fuse elements F1 and F2, and includes a counter circuit CM1 in which a count value is set by the combination of the conduction state and non-conduction state of the fuse elements F1 and F2 and the antifuse element A. The count value set in the counter circuit CM1 is incremented by sequentially rewriting the fuse elements F1 and F2 from the conduction state to the non-conduction state and the antifuse element A from the non-conduction state. The counter circuit CM1 has an output unit 10 that outputs a signal corresponding to the combination of the conduction state and non-conduction state of the fuse elements F1 and F2 and the antifuse element A.

The invention relates to an anti-fuse memory and a programming method thereof, the anti-fuse memory comprises an anti-fuse memory array, the anti-fuse memory array comprises a plurality of anti-fuse memory cells, each anti-fuse memory cell comprises an anti-fuse transistor, and the anti-fuse memory array further comprises a bit line; and the feedback network is connected between the bit line and at least one anti-fuse storage unit, and the feedback network is used for disconnecting the bit line and the anti-fuse storage unit when detecting that the magnitude of current between the bit line and the anti-fuse storage unit connected with the bit line meets a preset condition. According to the invention, multiple bits can be programmed at the same time, and unnecessary programming current can be eliminated, so that the power consumption is reduced.

A device may include a set of antifuse magnetic tunnel junctions (MTJs). A device may include a trim-enable MTJ associated with the set of antifuse MTJs, wherein each of the set of antifuse MTJs and the trim-enable MTJ has a logical state, the logical state being a first logical state or a second logical state. A device may include a circuit configured to determine the logical state of each of the set of antifuse MTJs and the trim-enable MTJ, wherein the logical state of each antifuse MTJ in the set of antifuse MTJs is read when the trim-enable MTJ has the second logical state, and wherein the logical state of every antifuse MTJ in the set of antifuse MTJs is determined to be the first logical state when the trim-enable MTJ has the first logical state.

An anti-fuse memory cell, an anti-fuse memory array and a memory, the anti-fuse memory cell comprising: an anti-fuse structure having a first end and a second end; the selection transistor comprises a drain electrode and a source electrode, and one of the drain electrode and the source electrode is coupled with the first end of the anti-fuse structure; and the anode of the voltage stabilizing diode is coupled with the other one of the drain electrode and the source electrode. According to the embodiment of the invention, the voltage stabilizing diode is additionally arranged in the anti-fuse memory cell and is connected with the selection transistor in series, the voltage stabilizing diode can provide stable voltage for the selection transistor, interference caused by current fluctuation can be resisted, correspondingly, the selection transistor can provide stable current for the anti-fuse structure, and the anti-fuse memory cell is more stable in performance. Therefore, the programming reliability of the anti-fuse structure is improved.

A secure anti-fuse one-time programmable (OTP) bit cell is disclosed. In one aspect, the OTP bit cell includes: a P well including an N + region and a P + region; a first contact electrically coupled to the N + region of the P well; a second contact electrically coupled to the P + region of the P well; an insulating layer disposed over a portion of the N + region, a portion of the P well, and a portion of the P + region; a gate structure disposed over the insulating layer; and a third contact electrically coupled to the gate structure. In the unprogrammed mode, the insulating layer produces a high resistance between the third contact and the second contact, and in the programmed mode, a fracture in the insulating layer produces a low resistance between the third contact and the second contact.

The present disclosure provides a programmable memory element. The programmable memory element includes an active region, a gate structure, and an anti-fuse storage unit. The active region is formed in a substrate and has a linear top view shape. The gate structure is arranged on the substrate and has a linear portion, which intersects with a section of the active region, and the section is away from each end of the active region. The anti-fuse storage unit uses a portion of the active region as a terminal and also includes an electrode and a dielectric layer. The electrode is arranged on the portion of the active region and is separated from the gate structure, and the dielectric layer is sandwiched between the portion of the active region and the electrode.

A memory device includes an anti-fuse cell array having a plurality of anti-fuse cells, each of the plurality of anti-fuse cells having a first transistor and a second transistor connected to the first transistor. A first terminal of the first transistor is connected to a bit line and the bit line is a buried rail formed in a substrate of the first transistor and the second transistor.

Embodiments of present invention provide an anti-fuse structure. The structure includes a first vertical metal pillar having a first bottom portion and a first top portion; a second vertical metal pillar having a second bottom portion and a second top portion; and a fuse dielectric between the first bottom portion of the first vertical metal pillar and the second bottom portion of the second vertical metal pillar, where a width of the first bottom portion of the first vertical metal pillar is wider than a width of the first top portion of the first vertical metal pillar or a width of the second bottom portion of the second vertical metal pillar is wider than a width of the second top portion of the second vertical metal pillar. A method of forming the same is also provided.

The present disclosure relates to an antifuse structure and a method for forming the same. The antifuse structure includes: a substrate; an antifuse device; a transistor device, including a first doping region, a second doping region, and a third doping region, all located within the substrate. The first doping region is electrically connected to the antifuse device, the second doping region is located on a side of the transistor device away from the antifuse device, and the third doping region is located on a side of the transistor device away from the antifuse device. The first doping region and the second doping region both include first doping ions, the third doping region includes at least the first doping ions and the second doping ions, and the doping ion concentration of the third doping region is less than the doping ion concentration of the second doping region. The present disclosure can reduce the leakage current of the antifuse structure and increase the turn-on current of the antifuse structure, thereby improving the performance of the antifuse structure.

The present invention relates to a semiconductor structure, a manufacturing method thereof, and a memory. The semiconductor structure includes: a substrate; a lower electrode layer located on a part of the substrate; an insulating dielectric layer located on the lower electrode layer, and the insulating dielectric layer exposes a part of the surface of the lower electrode layer; an upper electrode layer located on the insulating dielectric layer, and the upper electrode layer, the insulating dielectric layer, and the lower electrode layer form an antifuse capacitor. The present invention is beneficial to improving the electrical performance of the semiconductor structure.

An semiconductor device includes a programming transistor having a first source / drain (S / D) contact. The semiconductor device further includes an antifuse structure, wherein the antifuse structure comprises a conductive segment configured to form a capacitor with the first S / D contact, and the programming transistor is configured to subject the antifuse structure to a programming voltage to cause a resistive electrical path to form between the conductive segment and the first S / D contact.

The invention relates to an anti-fuse nonvolatile memory and a driving circuit thereof. The anti-fuse nonvolatile memory comprises a memory cell array, a driving circuit, a first power supply and a second power supply. The memory cell array includes a first sub-array and a second sub-array. All memory cells of the first sub-array are connected to the first anti-fuse control line and the first following control line. All memory cells of the second sub-array are connected to the second anti-fuse control line and the second following control line. A first voltage provided by the first power supply is output to the first anti-fuse control line and the second anti-fuse control line through the first anti-fuse control line driver and the second anti-fuse control line driver of the driving circuit. A second voltage provided by the second power supply is directly output to the first following control line and the second following control line.

A method of making a memory device includes forming an array of memory cells distributed along a first direction and a second direction perpendicular to the first direction, forming a first programming gate-strip extending in the second direction, and forming a plurality of first programming conducting lines extending in the first direction. Each of the memory cells includes an anti-fuse structure having a dielectric layer overlaying a semiconductor region in an active zone, and a transistor having a channel region in the active zone. The active zone extends in the first direction. Each of the plurality of first programming conducting lines is electrically connected connected to the first programming gate-strip through a corresponding resistor of a first plurality of resistors. The first programming gate-strip electrically connects to the anti-fuse structure of each of the memory cells along a column of the array of memory cells.

This disclosure provides an antifuse circuit, including: an antifuse unit; a programming circuit connected to the antifuse unit, the programming circuit being used to program the antifuse unit according to a programming control signal and a programming signal; a reading unit being used to read data signals from the antifuse unit; and a verification control unit being used to control the reading unit to electrically connect to the antifuse unit according to a verification enable signal and the programming signal of the antifuse unit when verifying the programming status of the antifuse unit. The antifuse circuit, by controlling the reading unit to electrically connect to the antifuse unit according to the verification enable signal and the programming signal of the antifuse unit when verifying the programming status of the antifuse unit, achieves real-time verification of the programming status.