11results about How to "Save extra space" patented technology

This utility model discloses a driving circuit for a ceramic chip selector, comprising: a transformer module having a transformer input terminal and a switch signal output terminal, the transformer input terminal being connected to a power supply, and a first inductor connected between the power supply and the switch signal output terminal; a negative voltage output module having a negative voltage output terminal, the negative voltage output module including a first input capacitor, a first input diode, and a second inductor, one end of the first input capacitor being connected to the switch signal output terminal, the other end of the first input capacitor being connected to the anode of the first input diode, the cathode of the first input diode being grounded, one end of the second inductor being connected to the anode of the first input diode, and the other end of the second inductor being connected to the negative voltage output terminal; and a positive voltage output module having a positive voltage output terminal connected to the switch signal output terminal. The driving circuit for the ceramic chip selector proposed in this utility model can effectively save PCB area and cost.

The utility model relates to the technical field of electronic components, and particularly discloses a touch control type knob device which comprises a rotary encoder, the rotary encoder comprises a fixed inner ring, a rotary outer ring and a circuit board, wherein the fixed inner ring is rotatably sleeved with the rotary outer ring, and the circuit board is installed on the fixed inner ring and responds to the angle change between the fixed inner ring and the rotary outer ring to generate a first electric signal. And the touch screen is fixedly arranged on the fixed inner ring, is electrically connected with the circuit board, and is used for sending a second electric signal to the circuit board after being touched and clicked. According to the touch control type knob device provided by the utility model, the overall size can be reduced on the premise of ensuring the rotating and pressing functions.

The embodiment of the present disclosure discloses an instruction fixed-length coding method, a processor, a storage medium and a program product. The method comprises the following steps: obtaining an original program, wherein the original program comprises original instructions; in a compilation stage, constructing a format protocol and a coding rule of instruction fixed-length based on a fixed coding length agreed by an architecture layer; compiling the original instructions into fixed-length instructions based on the format protocol and transmitting the fixed-length instructions into a processor; and the processor performs a coding operation on the fixed-length instructions based on the coding rule and outputs a coding result. The method can fundamentally eliminate the complex variable-length instruction coding logic by converting the variable-length instructions into a fixed-length format, simplify the processor hardware, save multiple hardware coding modules required by the variable-length instructions, reduce the chip area and power consumption, break through the rigid limitation of instruction processing throughput, adapt to parallel execution demand and improve the coding and execution efficiency.

This invention provides a ring VCO bias adaptive calibration circuit and method for suppressing MOS threshold voltage disturbances, and a ring voltage-controlled oscillator, comprising: a threshold voltage disturbance sensing module, a sensing signal processing module, and a branch current compensation transistor; the threshold voltage disturbance sensing module outputs differential voltage signals VP and VN reflecting the disturbance; the input terminals of the sensing signal processing module are respectively connected to the output terminals of a first constant current and a second constant current, and respectively receive VP and VN, for proportional subtraction amplification of VP and VN, and outputting an adaptive bias voltage; the control terminal of the branch current compensation transistor M8 is connected to VOUT, providing compensation current. This invention avoids phase noise degradation; reduces mass production costs; has a simple circuit architecture, achieves real-time adaptive calibration only through a pure analog path, and is suitable for precision frequency synthesis, RF and analog integrated circuits, and highly integrated electronic systems.

The utility model belongs to the vehicle -mounted electronic technical field, in order to solve the technical problem that current dynamic projection lamp volume is bigger, cost is higher, provides a kind of vehicle dynamic projection lamp control system, at least includes: main control module, interface module, LED drive module and power module, main control module is connected with interface module and LED drive module electricity respectively, the input of power module is connected with car body end power, and the output of power module is connected with main control module and LED drive module electricity, and LED drive module adopts the mode of MOS pipe switching and can realize 4 high-power LED control, carries out PWM light control to each LED separately, saves device cost and board area, makes dynamic projection lamp overall volume reduce.

Embodiments of the present disclosure relate to a method of calibrating a clock signal and corresponding electronic device and system. A method comprising: providing a reference clock signal having a reference period; providing a sampling clock signal having a sampling clock period that is shorter than the reference period of the reference clock signal; measuring a first sub-period as a first ratio of the first sub-period to a period of the sampling clock signal; measuring a second sub-period as a second ratio of the second sub-period to the period of the sampling clock signal; detecting a start edge of a clock signal having a clock period that is greater than the reference period; generating a reconstructed reference signal based on the first ratio, the second ratio, and the detected start edge; comparing the clock period of the clock signal to a period of the reconstructed reference signal to obtain a difference signal indicative of a difference therebetween; and providing the difference signal to user circuitry for calibrating the clock signal.

The invention discloses an ADC time domain error background calibration method and system based on digital output statistics. The system comprises a digital signal monitoring module, a gain error calibration module and a hierarchical offset error calibration module. The front end and the rear end of the ADC are connected, and digital signals are monitored in real time, so that the digital signals output by the front end stage and the rear end stage are obtained; extracting a gain error direction of a voltage-time converter (VTC) and adjusting the gain error direction by using a similarity relationship between a saturation state of a rear-end ADC and front and rear-end MSBs; constructing a hierarchical imbalance calibration loop, and carrying out decoupling calibration on the inherent imbalance of the VTC and the imbalance of each path of the TDC; on the premise of no interruption and low overhead, simultaneous, real-time and high-robustness calibration is carried out on the gain error and the multi-source offset error; belongs to the technical field of mixed signal integrated circuits.

The invention discloses a broadband radio frequency transceiving multifunctional chip covering a low frequency band and having an internal multi-module multiplexing structure, and belongs to the technical field of semiconductor radio frequency devices. A five-bit numerical control attenuator, four single-pole double-throw switches, a two-stage amplifier, a fixed attenuator, a biasing circuit and a TTL level driving circuit are integrated in the chip. Through a specific topological connection structure, hardware multiplexing of the first amplifier and the five-bit numerical control attenuator between a receiving channel and a transmitting channel is realized by using four single-pole double-throw switches, and the chip area and power consumption are remarkably reduced. The broadband coverage from a hundred MHz level low frequency to a ten GHz level high frequency is realized through a biasing circuit structure with multiple levels of inductors connected in series and RC grounded between the levels. A static working point adjusting port is led out from the chip, and power consumption and linearity can be flexibly configured through an external resistor. The invention has the advantages of high integration level, low power consumption, large bandwidth, strong universality and good index consistency, and is particularly suitable for multi-channel transmit-receive systems such as phased array radars and the like.

The application provides a memory and an electronic device. The memory device comprises: a storage array, the storage array comprising a first storage area and a second storage area, the first storage area being configured to store normal data, and the second storage area being configured to store metadata; an on-chip controller, the on-chip controller being configured to receive a first read-write command in a first mode, the first read-write command comprising a target data read-write command and a metadata read-write command appearing in sequence, the on-chip controller intercepting the metadata read-write command and outputting the target data read-write command in the first mode; wherein the storage array is configured to access the first storage area and the second storage area in parallel in response to the target data read-write command in the first mode.

This application discloses a method, apparatus, device, and storage medium for processing circuit layouts, relating to the field of electronic technology. The method includes: acquiring a circuit layout, the circuit layout including M pre-deployed circuit modules; for any one of the M circuit modules, determining a first sub-module and a second sub-module from the circuit module; and performing clock tree synthesis on the first sub-module and the second sub-module respectively. During clock tree synthesis, this method decouples the input / output registers and internal registers of the circuit modules, avoiding problems such as excessively long traces and excessive buffer insertions caused by mutual interference during clock tree synthesis due to their coupling under the same clock tree, thereby saving chip power and area.

The application is suitable for the field of chip and digital circuit design, and provides a hardware circuit, method, equipment and medium for floating point matrix multiplication, wherein the hardware circuit comprises: a floating point multiplication unit, which is used for multiplying a first standard floating point format multiplier and a second standard floating point format multiplicand, and outputs a product in a first self-defined floating point format; a floating point accumulation unit, which is used for adding the product and an accumulation input value, and outputs an accumulation sum in a second self-defined floating point format; and a format conversion unit, which is used for converting the accumulation sum in the second self-defined floating point format into a third standard floating point format and then outputting. The scheme can balance between maintaining calculation accuracy and limiting hardware overhead.