6results about How to "Save extra space" patented technology

This utility model discloses a driving circuit for a ceramic chip selector, comprising: a transformer module having a transformer input terminal and a switch signal output terminal, the transformer input terminal being connected to a power supply, and a first inductor connected between the power supply and the switch signal output terminal; a negative voltage output module having a negative voltage output terminal, the negative voltage output module including a first input capacitor, a first input diode, and a second inductor, one end of the first input capacitor being connected to the switch signal output terminal, the other end of the first input capacitor being connected to the anode of the first input diode, the cathode of the first input diode being grounded, one end of the second inductor being connected to the anode of the first input diode, and the other end of the second inductor being connected to the negative voltage output terminal; and a positive voltage output module having a positive voltage output terminal connected to the switch signal output terminal. The driving circuit for the ceramic chip selector proposed in this utility model can effectively save PCB area and cost.

The embodiment of the present disclosure discloses an instruction fixed-length coding method, a processor, a storage medium and a program product. The method comprises the following steps: obtaining an original program, wherein the original program comprises original instructions; in a compilation stage, constructing a format protocol and a coding rule of instruction fixed-length based on a fixed coding length agreed by an architecture layer; compiling the original instructions into fixed-length instructions based on the format protocol and transmitting the fixed-length instructions into a processor; and the processor performs a coding operation on the fixed-length instructions based on the coding rule and outputs a coding result. The method can fundamentally eliminate the complex variable-length instruction coding logic by converting the variable-length instructions into a fixed-length format, simplify the processor hardware, save multiple hardware coding modules required by the variable-length instructions, reduce the chip area and power consumption, break through the rigid limitation of instruction processing throughput, adapt to parallel execution demand and improve the coding and execution efficiency.

This invention provides a ring VCO bias adaptive calibration circuit and method for suppressing MOS threshold voltage disturbances, and a ring voltage-controlled oscillator, comprising: a threshold voltage disturbance sensing module, a sensing signal processing module, and a branch current compensation transistor; the threshold voltage disturbance sensing module outputs differential voltage signals VP and VN reflecting the disturbance; the input terminals of the sensing signal processing module are respectively connected to the output terminals of a first constant current and a second constant current, and respectively receive VP and VN, for proportional subtraction amplification of VP and VN, and outputting an adaptive bias voltage; the control terminal of the branch current compensation transistor M8 is connected to VOUT, providing compensation current. This invention avoids phase noise degradation; reduces mass production costs; has a simple circuit architecture, achieves real-time adaptive calibration only through a pure analog path, and is suitable for precision frequency synthesis, RF and analog integrated circuits, and highly integrated electronic systems.

The utility model belongs to the vehicle -mounted electronic technical field, in order to solve the technical problem that current dynamic projection lamp volume is bigger, cost is higher, provides a kind of vehicle dynamic projection lamp control system, at least includes: main control module, interface module, LED drive module and power module, main control module is connected with interface module and LED drive module electricity respectively, the input of power module is connected with car body end power, and the output of power module is connected with main control module and LED drive module electricity, and LED drive module adopts the mode of MOS pipe switching and can realize 4 high-power LED control, carries out PWM light control to each LED separately, saves device cost and board area, makes dynamic projection lamp overall volume reduce.

Embodiments of the present disclosure relate to a method of calibrating a clock signal and corresponding electronic device and system. A method comprising: providing a reference clock signal having a reference period; providing a sampling clock signal having a sampling clock period that is shorter than the reference period of the reference clock signal; measuring a first sub-period as a first ratio of the first sub-period to a period of the sampling clock signal; measuring a second sub-period as a second ratio of the second sub-period to the period of the sampling clock signal; detecting a start edge of a clock signal having a clock period that is greater than the reference period; generating a reconstructed reference signal based on the first ratio, the second ratio, and the detected start edge; comparing the clock period of the clock signal to a period of the reconstructed reference signal to obtain a difference signal indicative of a difference therebetween; and providing the difference signal to user circuitry for calibrating the clock signal.

The application is suitable for the field of chip and digital circuit design, and provides a hardware circuit, method, equipment and medium for floating point matrix multiplication, wherein the hardware circuit comprises: a floating point multiplication unit, which is used for multiplying a first standard floating point format multiplier and a second standard floating point format multiplicand, and outputs a product in a first self-defined floating point format; a floating point accumulation unit, which is used for adding the product and an accumulation input value, and outputs an accumulation sum in a second self-defined floating point format; and a format conversion unit, which is used for converting the accumulation sum in the second self-defined floating point format into a third standard floating point format and then outputting. The scheme can balance between maintaining calculation accuracy and limiting hardware overhead.