26results about How to "Save extra space" patented technology

The invention provides a tensor kernel operation component, and relates to the technical field of artificial intelligence chips, and the tensor kernel operation component comprises a decompression layer which is used for carrying out decompression processing on floating-point number elements in a first matrix of a preset floating-point number system to obtain first floating-point number elements in a preset bit format, or carrying out decompression processing on the first floating-point number elements in the first matrix of the preset floating-point number system to obtain second floating-point number elements in a preset bit format; the decompression module is used for decompressing floating-point number elements in a second matrix of a preset floating-point number system to obtain second floating-point number elements of a preset bit format; the calculation layer is used for multiplying and adding all first floating-point number elements corresponding to the first matrix and all second floating-point number elements corresponding to the second matrix to obtain a floating-point number in a target bit format; and the compression layer is used for receiving the floating-point number in the target bit format and carrying out compression conversion processing on the floating-point number in the target bit format to obtain a floating-point number operation result of a number system of the target floating-point number. The tensor kernel operation component provided by the invention is more in line with the matrix multiplication calculation dimension requirement of a large language model.

The invention discloses an overvoltage protection circuit of a switching power supply and the switching power supply. The switching power supply generates an output voltage according to an input voltage through periodic connection and disconnection of a main power tube. The overvoltage protection circuit comprises a voltage sampling unit which samples node voltage on a sampling node of the switching power supply to obtain node sampling voltage, and the node voltage is the sum of the product of output voltage and coefficient and input voltage; and the overvoltage control unit is used for performing overvoltage protection on the switching power supply according to the conduction duty ratio, the node sampling voltage and the characterization voltage of the overvoltage protection threshold. According to the overvoltage protection method, a proper sampling point is selected to enable the sampling voltage to be related to the output voltage and the input voltage at the same time, then the node voltage is sampled to calculate the output voltage, overvoltage protection is performed, sampling is simple, the calculated amount is small, errors are small, the overvoltage protection effect is good, an auxiliary winding is not needed, and the system cost is low.

The invention discloses a method for designing a high-yield magnetic random access memory system under an irradiation condition, and the method comprises the steps: carrying out the detection and repair of soft and hard errors based on a 2T-2M self-reference structure in combination with an error detection and correction circuit based on a Hamming code and a built-in self-test-self-repair system, inhibiting the generation of the soft and hard errors in an irradiation environment, and improving the reliability of the system. And the yield of the memory is effectively improved. The built-in self-test-self-repair system comprises a built-in self-test circuit with a fault diagnosis function and a built-in redundancy self-repair circuit, and a sequential logic unit in the system calls a sequential logic standard unit library designed by adopting a dual-modular redundancy anti-radiation reinforcement method.

The invention provides a power supply protection circuit for a high-speed digital circuit, and belongs to the technical field of electronics and communication information. Comprising a current sensor and a voltage sensor which are arranged at a power inlet, and the voltage sensor and the current sensor are both connected with a microcontroller; a circuit passing through the current sensor and the voltage sensor is connected with an intermediate-stage filter circuit, the intermediate-stage filter circuit is connected with a power supply chip, and the power supply chip is connected with a final-stage filter circuit; the current sensor is used for carrying out parameter sampling on current and voltage, the microcontroller monitors the voltage and current conditions of an inlet and subsequent stages in real time, and the power supply chip is controlled stage by stage to ensure the safety of a power supply. According to the invention, the number of used devices is reduced, the cost is reduced, overvoltage and overcurrent risks are avoided, and finally the ripple noise of the power supply end of an electric device is reduced; a special filter circuit is added according to the characteristics of the switching power supply, and ripple introduction can be effectively reduced.

The present application provides a data handling device supporting parallel processors, which can be used for data transfer between on-chip cache and off-chip memory. The device includes a control module, an arithmetic logic unit and its associated aligned cache, and a data path running in a pipeline manner consisting of a read-in DMA module, a data cache module and an output DMA module. The arithmetic logic unit used for performing calculation operations such as precision conversion is pre-placed at the data interface of the data storage unit of the processor, so that the data output from the data storage unit is first subjected to precision conversion by the arithmetic logic unit, and then transmitted to the data path, thereby minimizing the line width between the data storage module and the data handling module on the processor chip, thereby saving chip power consumption and area.

This utility model discloses a driving circuit for a ceramic chip selector, comprising: a transformer module having a transformer input terminal and a switch signal output terminal, the transformer input terminal being connected to a power supply, and a first inductor connected between the power supply and the switch signal output terminal; a negative voltage output module having a negative voltage output terminal, the negative voltage output module including a first input capacitor, a first input diode, and a second inductor, one end of the first input capacitor being connected to the switch signal output terminal, the other end of the first input capacitor being connected to the anode of the first input diode, the cathode of the first input diode being grounded, one end of the second inductor being connected to the anode of the first input diode, and the other end of the second inductor being connected to the negative voltage output terminal; and a positive voltage output module having a positive voltage output terminal connected to the switch signal output terminal. The driving circuit for the ceramic chip selector proposed in this utility model can effectively save PCB area and cost.

The utility model relates to the technical field of electronic components, and particularly discloses a touch control type knob device which comprises a rotary encoder, the rotary encoder comprises a fixed inner ring, a rotary outer ring and a circuit board, wherein the fixed inner ring is rotatably sleeved with the rotary outer ring, and the circuit board is installed on the fixed inner ring and responds to the angle change between the fixed inner ring and the rotary outer ring to generate a first electric signal. And the touch screen is fixedly arranged on the fixed inner ring, is electrically connected with the circuit board, and is used for sending a second electric signal to the circuit board after being touched and clicked. According to the touch control type knob device provided by the utility model, the overall size can be reduced on the premise of ensuring the rotating and pressing functions.

The invention discloses an acousto-optic modulator driving circuit, which comprises a local oscillation signal generator module, an analog driving modulation amplification module, a digital driving modulation amplification module and a power supply modulation module, and is characterized in that the local oscillation signal generator module is formed by connecting a crystal oscillation circuit, a low-pass filter circuit and a power divider; the analog driving modulation amplification module is formed by connecting a variable gain amplification circuit, a pre-amplification circuit, a power amplification circuit, a matching and low-pass filter circuit and a radio frequency output port; the digital driving modulation amplification module is formed by connecting a keying modulation circuit, a pre-amplification circuit, a power amplification circuit, a matching and low-pass filtering circuit and a radio frequency output port. The local oscillation signal generator module generates high-frequency sinusoidal signals through the crystal oscillation circuit and the low-pass filter circuit, local oscillation signals are provided for the analog driving modulation amplification module and the digital driving modulation amplification module at the same time through the power divider, the average power consumption is reduced, and the area and cost of a circuit board are saved.

The embodiment of the present disclosure discloses an instruction fixed-length coding method, a processor, a storage medium and a program product. The method comprises the following steps: obtaining an original program, wherein the original program comprises original instructions; in a compilation stage, constructing a format protocol and a coding rule of instruction fixed-length based on a fixed coding length agreed by an architecture layer; compiling the original instructions into fixed-length instructions based on the format protocol and transmitting the fixed-length instructions into a processor; and the processor performs a coding operation on the fixed-length instructions based on the coding rule and outputs a coding result. The method can fundamentally eliminate the complex variable-length instruction coding logic by converting the variable-length instructions into a fixed-length format, simplify the processor hardware, save multiple hardware coding modules required by the variable-length instructions, reduce the chip area and power consumption, break through the rigid limitation of instruction processing throughput, adapt to parallel execution demand and improve the coding and execution efficiency.

This invention provides a ring VCO bias adaptive calibration circuit and method for suppressing MOS threshold voltage disturbances, and a ring voltage-controlled oscillator, comprising: a threshold voltage disturbance sensing module, a sensing signal processing module, and a branch current compensation transistor; the threshold voltage disturbance sensing module outputs differential voltage signals VP and VN reflecting the disturbance; the input terminals of the sensing signal processing module are respectively connected to the output terminals of a first constant current and a second constant current, and respectively receive VP and VN, for proportional subtraction amplification of VP and VN, and outputting an adaptive bias voltage; the control terminal of the branch current compensation transistor M8 is connected to VOUT, providing compensation current. This invention avoids phase noise degradation; reduces mass production costs; has a simple circuit architecture, achieves real-time adaptive calibration only through a pure analog path, and is suitable for precision frequency synthesis, RF and analog integrated circuits, and highly integrated electronic systems.

The invention relates to the field of communication protocol systems, and provides a control structure for realizing communication protocol layer communication by hardware, which comprises a communication protocol host and a communication protocol slave connected through a communication protocol interface, and an upper computer connected with the communication protocol host through an upper computer communication interface. The protocol layer communication of the communication protocol is realized through hardware, a microcontroller does not need to be integrated in the communication protocol host and the communication protocol slave of the communication protocol system, and the area and the cost of a chip of the communication protocol system can be saved.

The invention relates to the technical field of flight carrier positioning, and discloses a target positioning method and system based on interferometer direction finding, and the method comprises the steps: carrying out the direction finding of a flight carrier at first preset time intervals in a preset positioning time period, and storing the direction finding angle information to obtain a direction finding angle vector; performing least square fitting on the direction finding angle and the time to obtain a fitting curve function reflecting the relation between the direction finding angle and the time; drawing an error equation for the direction-finding angle vector and the fitting curve function, and finding a first positioning direction-finding angle corresponding to a minimum error value which is closest to the starting time and is greater than a positioning angle threshold value in a preset positioning time period, the second positioning direction finding angle corresponds to the minimum error value which is closest to the end time and is greater than the positioning angle threshold value; and performing cross positioning according to the first direction-finding angle for positioning and the second direction-finding angle for positioning to obtain a positioning point. The positioning precision is high, and the cost is low.

The utility model belongs to the vehicle -mounted electronic technical field, in order to solve the technical problem that current dynamic projection lamp volume is bigger, cost is higher, provides a kind of vehicle dynamic projection lamp control system, at least includes: main control module, interface module, LED drive module and power module, main control module is connected with interface module and LED drive module electricity respectively, the input of power module is connected with car body end power, and the output of power module is connected with main control module and LED drive module electricity, and LED drive module adopts the mode of MOS pipe switching and can realize 4 high-power LED control, carries out PWM light control to each LED separately, saves device cost and board area, makes dynamic projection lamp overall volume reduce.

The invention provides a self-frequency-modulation filter circuit and a weak signal detection system, and relates to the technical field of filters. The self-frequency-modulation filter circuit comprises a self-frequency-modulation filter module which comprises a first transistor, a second transistor, a first resistor, a second resistor and comb teeth. The voltage-controlled oscillator is connected with the self-frequency-modulation filter module and used for outputting a second output signal with the corresponding frequency according to the amplitude of the first output signal of the self-frequency-modulation filter module; and the driving module is respectively connected with the self-frequency-modulation filter module and the voltage-controlled oscillator and is used for receiving the second output signal and adjusting the measuring range of the comb teeth according to the amplitude of the second output signal so as to adjust the frequency of the self-frequency-modulation filter module. A closed-loop control circuit is formed, the bandwidth of the filter can be automatically adjusted while the area and cost of the circuit are saved, and the design flexibility of the circuit is improved.

Embodiments of the present disclosure relate to a method of calibrating a clock signal and corresponding electronic device and system. A method comprising: providing a reference clock signal having a reference period; providing a sampling clock signal having a sampling clock period that is shorter than the reference period of the reference clock signal; measuring a first sub-period as a first ratio of the first sub-period to a period of the sampling clock signal; measuring a second sub-period as a second ratio of the second sub-period to the period of the sampling clock signal; detecting a start edge of a clock signal having a clock period that is greater than the reference period; generating a reconstructed reference signal based on the first ratio, the second ratio, and the detected start edge; comparing the clock period of the clock signal to a period of the reconstructed reference signal to obtain a difference signal indicative of a difference therebetween; and providing the difference signal to user circuitry for calibrating the clock signal.

The present application provides an ultra-low power self-bias circuit and an electronic terminal used therein, including: a startup circuit, a core circuit electrically connected to and controlled by the startup circuit; the core circuit includes: a first NMOS tube, a second NMOS tube, a resistor, and a current mirror circuit; the gate of the first NMOS tube is connected to the output end of the startup circuit and the drain of the second NMOS tube, and the source is connected to the first end of the resistor and the gate of the second NMOS tube; the second end of the resistor is grounded; the source of the second NMOS tube is connected to the second end of the resistor and grounded; wherein the drain of the first NMOS tube is connected to the current mirror circuit; the bias current output by the current mirror circuit is equivalent to the current flowing through the resistor. Compared with the traditional bandgap circuit, the self-bias circuit provided by the present application greatly simplifies the complexity of the circuit and saves the circuit layout area and power consumption, while also greatly reducing the chip cost.

The invention discloses an ADC time domain error background calibration method and system based on digital output statistics. The system comprises a digital signal monitoring module, a gain error calibration module and a hierarchical offset error calibration module. The front end and the rear end of the ADC are connected, and digital signals are monitored in real time, so that the digital signals output by the front end stage and the rear end stage are obtained; extracting a gain error direction of a voltage-time converter (VTC) and adjusting the gain error direction by using a similarity relationship between a saturation state of a rear-end ADC and front and rear-end MSBs; constructing a hierarchical imbalance calibration loop, and carrying out decoupling calibration on the inherent imbalance of the VTC and the imbalance of each path of the TDC; on the premise of no interruption and low overhead, simultaneous, real-time and high-robustness calibration is carried out on the gain error and the multi-source offset error; belongs to the technical field of mixed signal integrated circuits.

The invention provides a memory unit, a memory array, a terminal and an operation method, and the memory unit comprises a volatile in-memory calculation module and a nonvolatile in-memory calculation module. The volatile in-memory calculation module comprises a static random access structure or a dynamic random access structure; and the nonvolatile in-memory calculation module comprises a switching tube and at least one memristor, and the switching tube and the memristor are connected in series and then are connected between the two data ends of the static random access structure or between the data end of the dynamic random access structure and the reference ground. According to the memory unit, the memory array and the operation method provided by the invention, the problem that the dynamic transmission power consumption and the static standby power consumption of the existing random access memory unit are high is effectively relieved.

The invention discloses a broadband radio frequency transceiving multifunctional chip covering a low frequency band and having an internal multi-module multiplexing structure, and belongs to the technical field of semiconductor radio frequency devices. A five-bit numerical control attenuator, four single-pole double-throw switches, a two-stage amplifier, a fixed attenuator, a biasing circuit and a TTL level driving circuit are integrated in the chip. Through a specific topological connection structure, hardware multiplexing of the first amplifier and the five-bit numerical control attenuator between a receiving channel and a transmitting channel is realized by using four single-pole double-throw switches, and the chip area and power consumption are remarkably reduced. The broadband coverage from a hundred MHz level low frequency to a ten GHz level high frequency is realized through a biasing circuit structure with multiple levels of inductors connected in series and RC grounded between the levels. A static working point adjusting port is led out from the chip, and power consumption and linearity can be flexibly configured through an external resistor. The invention has the advantages of high integration level, low power consumption, large bandwidth, strong universality and good index consistency, and is particularly suitable for multi-channel transmit-receive systems such as phased array radars and the like.

The embodiment of the invention discloses a memory and an operation method thereof. The memory comprises a memory cell array and a peripheral circuit coupled with the memory cell array, the memory cell array comprises a plurality of bit lines, a plurality of word lines and a plurality of memory cells located between the plurality of bit lines and the plurality of word lines; the peripheral circuit is configured to: in response to a write command, apply a first voltage to a selected word line, apply a second voltage to a selected bit line, apply a ground voltage to an unselected word line, and apply a supply voltage to the unselected bit line, such that a target memory cell coupled to the selected word line and the selected bit line is in a conductive state, and enabling the non-target storage unit coupled with the unselected word line and / or the unselected bit line to be in a non-conducting state.

The application provides a memory and an electronic device. The memory device comprises: a storage array, the storage array comprising a first storage area and a second storage area, the first storage area being configured to store normal data, and the second storage area being configured to store metadata; an on-chip controller, the on-chip controller being configured to receive a first read-write command in a first mode, the first read-write command comprising a target data read-write command and a metadata read-write command appearing in sequence, the on-chip controller intercepting the metadata read-write command and outputting the target data read-write command in the first mode; wherein the storage array is configured to access the first storage area and the second storage area in parallel in response to the target data read-write command in the first mode.

The embodiment of the invention discloses a PFC (Power Factor Correction) control method and a power conversion system applying the same, each slave PFC control circuit is configured to share the same detection circuit, when a working mode is configured, the number of the slave PFC circuits is determined according to a detection signal obtained by the detection circuit, and when a normal working mode is configured, the number of the slave PFC circuits is determined according to a detection signal obtained by the detection circuit. The slave PFC control circuit is controlled by the driving signal of the main PFC control circuit to work; when the working mode is configured, the terminals in the normal working mode can be reused, so that the terminals and the area are saved.

The invention relates to a power management method, a power adapter and a controller thereof. The method comprises the following steps: taking power from one auxiliary winding; cyclically executing a power supply management step: detecting the voltage output by the auxiliary winding of which the power is taken currently to obtain a power supply voltage; analyzing whether the power supply voltage is within a set threshold range or not; when the power supply voltage is within a set threshold range, taking power from the auxiliary winding which is taken power at present; when the power supply voltage is greater than the upper limit value of the set threshold range, taking power from one auxiliary winding of which the number of turns is smaller than that of the auxiliary winding of which the power is taken currently in the N auxiliary windings; and when the power supply voltage is smaller than the lower limit value of the set threshold range, taking power from one auxiliary winding of which the number of turns is larger than that of the auxiliary winding of which the power is taken currently in the N auxiliary windings. According to the invention, segmented power supply is realized when the output voltage range of the power adapter is relatively wide, and a BOOST circuit does not need to be additionally arranged.

The present application provides a low-power control method, medium and low-power processor for a network message pre-classification processor, supports a scheduling strategy based on an index generated by a microengine cluster, a microengine group and a microengine arrangement order, and supports dynamic modification of the total number of microengines and the microengine scheduling strategy. Users can dynamically switch scheduling strategies according to traffic load. A fully shared storage structure is also adopted, each microengine group includes a microengine group memory, which is only accessible to the microengines within the group, and each microengine cluster is provided with a microengine cluster memory, which can be shared by all microengines in the cluster, saving more area and power consumption. When the number of microengines used is less than the total number of microengines in the microengine pool, the enable mapping table in the packet inlet scheduling module and the packet outlet scheduling module will generate an enable control signal for the microengine and the related memory according to the number of microengines currently actually used and the scheduling rules, shut down the idle microengines and memory, and reduce power consumption.

This application discloses a method, apparatus, device, and storage medium for processing circuit layouts, relating to the field of electronic technology. The method includes: acquiring a circuit layout, the circuit layout including M pre-deployed circuit modules; for any one of the M circuit modules, determining a first sub-module and a second sub-module from the circuit module; and performing clock tree synthesis on the first sub-module and the second sub-module respectively. During clock tree synthesis, this method decouples the input / output registers and internal registers of the circuit modules, avoiding problems such as excessively long traces and excessive buffer insertions caused by mutual interference during clock tree synthesis due to their coupling under the same clock tree, thereby saving chip power and area.

The application is suitable for the field of chip and digital circuit design, and provides a hardware circuit, method, equipment and medium for floating point matrix multiplication, wherein the hardware circuit comprises: a floating point multiplication unit, which is used for multiplying a first standard floating point format multiplier and a second standard floating point format multiplicand, and outputs a product in a first self-defined floating point format; a floating point accumulation unit, which is used for adding the product and an accumulation input value, and outputs an accumulation sum in a second self-defined floating point format; and a format conversion unit, which is used for converting the accumulation sum in the second self-defined floating point format into a third standard floating point format and then outputting. The scheme can balance between maintaining calculation accuracy and limiting hardware overhead.