586results about How to "Save extra space" patented technology

A data processing apparatus and method are provided for performing hazard detection in respect of a series of access requests issued by processing circuitry for handling by one or more slave devices. The series of access requests include one or more write access requests, each write access request specifying a write operation to be performed by an addressed slave device, and each issued write access request being a pending write access request until the write operation has been completed by the addressed slave device. Hazard detection circuitry comprises a pending write access history storage having at least one buffer and at least one counter for keeping a record of each pending write access request. Update circuitry is responsive to receipt of a write access request to be issued by the processing circuitry, to perform an update process to identify that write access request as a pending write access request in one of the buffers, and if the identity of another pending write access request is overwritten by that update process, to increment a count value in one of the counters. On completion of each write access request by the addressed slave device, the update circuitry performs a further update process to remove the record of that completed write access request from the pending write access history storage. Hazard checking circuitry is then responsive to at least a subset of the access requests to be issued by the processing circuitry, to reference the pending write access history storage in order to determine whether a hazard condition occurs. The manner in which the update circuitry uses a combination of buffers and counters to keep a record of each pending write access request provides improved performance with respect to known prior art techniques, without the hardware cost that would be associated with increasing the number of buffers.

Embodiments of the present invention are directed to acoustic data transmission using a spreading code. A system for acoustic data transmission includes an ingestible capsule and an acoustic receiver. The ingestible capsule includes a modulator, a spreader, and an acoustic transmitter. The modulator modulates data according to a modulation scheme. The spreader spreads the modulated data according to a spreading code. The acoustic transmitter acoustically transmits the modulated and spread data through a body of an animal. The acoustic receiver includes an acoustic transducer a de-spreader and a demodulator. The acoustic transducer receives the acoustically transmitted signal and forms an electrical signal therefrom. The de-spreader de-spreads the received signal in accordance with the spreading code. The demodulator demodulates the received and de-spread signal in accordance with the modulation scheme, wherein a phase of the spreading code is synchronized with the received signal whereby a signal-to-noise ratio of the received signal is increased.

The present invention relates to a system for landing UAV's. The system comprises a slingshot structure that includes arm based structure and an axis means installed along the arm of the structure and wherein it enables the arm to move around it in addition, the system comprises base means connecting the axis means to a platform at which the system is installable. The system also include a controlled pulling and braking means that connects between the arm of the structure and the platform upon which the system is installable and a stretchable elastic means installed in a stretched manner at a gap formed between two arms and set to connect with a landing UAV. At the landing phase, the controlled pulling and braking means of the system, essentially breaks the motion of the arm based structure that is propelled to revolve around the system's axis means, from a time that the UAV forms contact with the elastic means and with it propels the structure to move around the axis means.

A flip-chip (FC) package structure is provided. The FC package structure includes a substrate, a chip, a plurality of copper platforms, a plurality of copper bumps, a plating layer, a circuit layer and a solder mask layer. The copper bumps are disposed on the substrate. The copper platforms are stacked on the copper bumps. The plating layer covers the copper bumps and the copper platforms, for contacting with chip foot pads configured at a bottom of the chip. The FC package structure does not need to reserve a space for wire bonding, thus saving the area of the substrate. The copper platforms are stacked on the copper bumps, and are higher than the circuit pattern layer. Therefore, the chip is blocked up, and the gap between the chip and the substrate is enlarged, thus preventing the risk of configuring voids when filling the cladding material and improving the packaging yield.

Briefly, a system for synthesizing a two dimensional code and a logo and the method thereof are presented. The system for generating a synthesized two dimensional code comprises synthesizing means, for synthesizing an original two dimensional code and a visually readable logo to form the synthesized two dimensional code, with at least a part of the visually readable logo being overlapped with the original two dimensional code; identifying means, for reading and identifying the synthesized two dimensional code; and adjusting means, if the synthesized two dimensional code being identified by the identifying means has a code error rate of the synthesized two dimensional code larger than an error correction rate, the adjusting means adjusting the size of the visually readable logo and/or the location of the visually readable logo with respect to the original two dimensional code. The present invention may integrate enterprise logo(s), brand logo(s) and product logo(s) with a two dimensional code as a whole, which may save areas and achieve better effect for brand and product promotion.

Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. By applying a high voltage to an OTP element coupled to the P-terminal of a diode and switching the N-terminal of a diode to a low voltage for suitable duration of time, a current flows through the OTP element may change the resistance state. On the polysilicon diode, the spacing and doping level of a gap between the P- and N-implants can be controlled for different breakdown voltages and leakage currents. The Silicide Block Layer (SBL) can be used to block silicide formation on the top of polysilicon to prevent shorting. If the OTP element is a polysilicon electrical fuse, the fuse element can be merged with the polysilicon diode in one piece to save area.

A method and apparatus for protection against electrostatic discharge (ESD) with improved latch-up robustness featuring a silicide blocked p-type field effect transistor is disclosed. The transistor has a snapback voltage that is less than the breakdown voltage of its gate oxide. The transistor is part of an integrated circuit and coupled to an I/O pad having no n-diffusions connected directly to it. A given integrated circuit may employ one or more the transistors configured in accordance with the invention that are associated with one or more I/O pads within the integrated circuit.

The invention discloses a soft start device that can realize linear control, which comprises a working circuit, a soft start circuit and a start control circuit; the working circuit comprises a DC power source, a load capacitance, a power tube and a feedback circuit which are connected between the DC power source and the load capacitance and also a soft start circuit and a start control circuit, and the power tube is provided with a control end; the soft start circuit comprises a voltage generator, the output voltage of which is increased gradually after start, and an error amplifier, the input end of which is connected with the output end of the voltage generator; the input end of the error amplifier is connected between the output end of the power tube and the ground, while the output end of the error amplifier is connected to the control end of the power tube; when the start control circuit detects that the start begins, the soft start circuit is set to be in normal working state and a feedback circuit is set to be in off working state. The adoption of the device of the invention can avoid surge current at the moment when the power source charges the load capacitance at the instance when the circuit is electrified, can repeatedly use the existing error amplifier in the original circuit structure and save the areas and energy consumption of chips.

The invention provides a 10-bit ultra-low-power successive approximation register analog-to-digital converter based on charge redistribution. The analog-to-digital converter comprises a sampling network, a differential capacitor array, a comparator and a successive approximation control logic device; the differential capacitor array is connected with the sampling network, the comparator is connected with the differential capacitor array, and the successive approximation control logic device is connected with the comparator. The differential capacitor array includes a first capacitor array connected with a non-inverting input end of a comparator circuit and a second capacitor array connected with an inverting input end of the comparator circuit. Each of the first capacitor array and the second capacitor array consists of nine groups of capacitors which are of binary structures; bottom plates of all redundant capacitors are selectively connected with common-mode voltage or ground and the rest eight groups of capacitors are selectively connected with the common-mode voltage, power voltage or ground. An output end of the successive approximation control logic device controls switching of capacitor switches of the differential capacitor array to be connected with the voltage selectively. The first capacitor array and the second capacitor array sample input signals and input samples to the comparator, and a comparison result of the comparator is input to the successive approximation control logic device.

Vector processing engines (VPEs) having programmable data path configurations for providing multi-mode Radix-2^X butterfly vector processing circuits. Related vector processors, systems, and methods are also disclosed. The VPEs disclosed herein include a plurality of vector processing stages each having vector processing blocks that have programmable data path configurations for performing Radix-2^X butterfly vector operations to perform Fast Fourier Transform (FFT) vector processing operations efficiently. The data path configurations of the vector processing blocks can be programmed to provide different types of Radix-2^X butterfly vector operations as well as other arithmetic logic vector operations. As a result, fewer VPEs can provide desired Radix-2^X butterfly vector operations and other types arithmetic logic vector operations in a vector processor, thus saving area in the vector processor while still retaining vector processing advantages of fewer register writes and faster vector instruction execution times over scalar processing engines.

The invention relates to a band-gap reference circuit. The band-gap reference circuit comprises a reference voltage source VREF, a band-gap core circuit, a negative feedback circuit and a starting circuit, wherein gate voltage V_REG is stretched by the reference voltage source VREF so that internal voltage pre-stabilization can be achieved, an internal voltage pre-stabilizing circuit is formed, the band-gap core circuit is provided with an automatic biasing cascode amplifying circuit used for increasing a power supply rejection ratio, the negative feedback circuit provides the supply voltage VDD, processed through voltage stabilization, for the band-gap core circuit, and the starting circuit stretches the reference voltage source VREF when work begins so that the automatic biasing cascode amplifying circuit can work normally. According to the band-gap reference circuit, due to the facts that the supply voltage VDD processed through voltage stabilization is provided for the band-gap core circuit through the negative feedback circuit, and the automatic biasing cascode amplifying circuit is adopted inside for increasing the power supply rejection ratio, area and power consumption are saved.

The invention discloses a circuit board testing system, which comprises a test tank, a material taking and putting mechanism and a control system, wherein the control system comprises a PC (personal computer) processor and a PLC (Programmable Logic Controller) control system. A box-type test machine comprises a box body, a drawer-type fixture, a fixture driving component and a test device, wherein one side of the box body is opened; the drawer-type fixture is arranged in the box body in an insertion mode from the opened side of the box body; the fixture driving component is connected with the drawer-type fixture and is used for driving the drawer-type fixture to pop out or retract back to the opened side of the box body; and the test device is arranged in the box body and is communicated with a circuit board to be tested. According to the circuit board testing system, the automation of the circuit board testing system can be realized.

A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is preferably a material that minimizes stresses on the crystalline body, such as an oxide. The body may be doped, and may also include a silicide layer on the upper surface. This fuse structure may be successfully programmed over a wide range of programming voltages and time.

A semiconductor package that includes at least two semiconductor devices that are coupled to one another through a conductive clip.

The invention discloses a capacitance mismatch calibrating circuit and calibrating method applied to a single-end SAR ADC (Successive Approximation Analog-to-Digital Converter). By using the method, error caused by capacitance mismatch of the SAR ADC can be calibrated. According to the method, only two pairs of redundant capacitance need to be inserted in an analog domain for compensation of capacitance mismatch in a digital domain. A binary capacitance DAC (Digital-to-Analog Converter) containing two pairs of redundant dot capacitance includes a segmentation binary capacitance DAC and redundant capacitance Cjr+, Cjr- inserted to the lowest bit of aN MSB segment of a segmentation capacitance, and redundant capacitance Cqr+, Cqr- inserted to an LSB segment. A redundant bit calculation module adds the inserted redundant bits to other normal bits and obtains N-bit valid output. A capacitance mismatch calibrating module performs compensation to capacitance mismatch on the output result. Compared with the traditional SAR ADC structure, only two pairs of redundant capacitance are added. The calculation of mismatch compensation is performed in the digital domain, so that the layout size and analog circuit complexity is reduced.

The invention discloses a high-speed low-power-consumption dynamic comparator, comprising a pre-amplification circuit and a regeneration latch circuit; the pre-amplification circuit comprises a clock output end, a first differential signal input end, a second differential signal input end, an output node FN and an output node FP; the pre-amplification circuit is connected with a direct current power, the output node FN synthesizes the output voltage VDD of the direct current power and a first differential input signal to output the first differential input signal, and the output node FP synthesizes the output voltage VDD of the direct current power and a second differential input signal to output the second differential input signal; the regeneration latch circuit is connected with the output node FN and the output node FP of the pre-amplification circuit, and can be used for latching the first differential input signal and the second differential input signal and outputting a first output signal and a second output signal. The dynamic comparator provided by the invention can quickly achieve low power consumption dynamic latching function under the high speed application.

Logic circuits that support the addition of three binary numbers using hardwired adders are described. In one embodiment, this is accomplished by using a 3:2 compressor (i.e., a Carry Save Adder method), using hardwired adders to add the sums and carrys produced by the 3:2 compression, and sharing carrys data calculated in one logic element (“LE”) with the following LE. In such an embodiment, with the exception of the first and last LEs in a logic array block (“LAB”), each LE in effect lends one look-up table (“LUT”) to the LE below (i.e., the following LE) and borrows one LUT from the LE above (i.e., the previous LE). The LUT being lent or borrowed is one that implements the carry function in the 3:2 compressor model. In another aspect, an embodiment of the present invention provides LEs that include selectors to select signals corresponding to the addition of three binary numbers mode.

The present invention provides a lateral diffused metal-oxide-semiconductor device including a first doped region, a second doped region, a third doped region, a gate structure, and a contact metal. The first doped region and the third doped region have a first conductive type, and the second doped region has a second conductive type. The second doped region, which has a racetrack-shaped layout, is disposed in the first doped region, and has a long axis. The third doped region is disposed in the second doped region. The gate structure is disposed on the first doped region and the second doped region at a side of the third doped region. The contact metal is disposed on the first doped region at a side of the second doped region extending out along the long axis, and is in contact with the first doped region.