715 results about "Test structure" patented technology

The invention belongs to the technical field of performance testing, and particularly discloses an intelligent testing system and method for the impedance performance of an HDI circuit board, and the method comprises the steps: immediately starting an interlayer collection module after the lamination of each line layer, carrying out the electrical precise alignment through a POFV test structure, and collecting the in-situ impedance data; the diagnosis prediction module analyzes and processes the data, generates an impedance deviation parameter set, calculates an impedance performance standard coefficient fused with a layer influence factor, and analyzes and outputs a trend result through a time sequence; the impedance state judgment module carries out abnormity judgment based on a preset rule according to the standard coefficient and the trend result; when the judgment result is abnormal, an adjustment triggering marking module is started; and finally, a test report output module generates a test report containing the impedance performance score and the impedance performance distribution of the whole board. According to the invention, layer-by-layer, real-time and closed-loop intelligent test and regulation of impedance performance are realized, and product quality and production efficiency are effectively improved.

The invention relates to the technical field of semiconductor testing, in particular to a radio frequency testing bonding pad and a radio frequency testing structure. The radio frequency test pad comprises a substrate; the connection supporting layer is located on the substrate, and the connection supporting layer comprises a metal layer; the connection ports are located on the connection supporting layer, and the connection ports comprise a grounding port and a signal port; the grounding port is conductively connected through the metal layer; the signal port and the metal layer are not conductive. The signal port and the metal layer are arranged to be non-conductive, so that potential difference between the signal port and a structure below is avoided, parasitic capacitance is inhibited, and the accuracy of radio frequency testing is further improved.

The invention discloses a combined load synchronous application testing device. The technical problems that in the prior art, the load applying mode is single, and the combined load cannot be synchronously applied are solved. The device comprises a connecting mechanism and a load applying mechanism, wherein the load applying mechanism comprises a torsional load applying structure, a load transmitting structure and a multi-linkage testing structure. The load transmission structure comprises a special-shaped stress plate and a torsional load transmission assembly, and the torsional load transmission assembly comprises a connecting chuck and a torque plug-in. By controlling the rotation of the torsion load transmission assembly, a pure torsion load applying mode or a conversion mode of converting torsion motion into radial load can be selectively realized, and multi-directional load detection is realized. The invention further provides a combined load synchronous applying function, the single driving source synchronously activates the torsion load path and the radial load path by adjusting the geometric positions of the torque plug-in and the load adjusting plate on the connecting chuck, and synchronous applying of the torsion load and the radial load is achieved.

The invention relates to an airflow sensor testing structure and a packaging method and packaging structure thereof, each chip unit of an airflow sensor wafer is composed of a substrate (1), a vibrating diaphragm (2) and a back plate which are stacked, the substrate (1) is provided with a back cavity (42) penetrating in the thickness direction of the substrate (1), a slot (10) is formed in the bottom of the substrate (1), and the vibrating diaphragm (2) is arranged in the slot (10). The open groove (10) penetrates through the substrate (1) and the back cavity (42), and the open groove (10) is used for establishing a continuous air flow path in a space outside the back cavity (42) and the air flow sensor. During packaging, the airflow sensor chip is fixed on the packaging substrate through silica gel, a packaging shell is installed outside the airflow sensor chip, the open groove (10) is filled with the silica gel, and blocking and sealing of the open groove (10) are achieved. According to the invention, the requirement of each tube core on the test wafer can be met, the production cost is not increased, and the risk of wafer fragmentation can be effectively avoided.

The invention discloses a selector unit for dynamic switching of a standard unit, a ring oscillator and a test structure. Wherein the selector unit is connected in parallel with standard units with different threshold voltages, driving capabilities and logic functions, and is matched with the first switch control circuit, so that flexible switching of the differentiated standard units is realized, and the static architecture limitation of a traditional test circuit is broken through; according to the ring oscillator, a selector unit is embedded into a closed oscillation loop of a standard unit chain, a time sequence path of multiple unit combinations is formed through dynamic configuration, and the delay superposition effect between mixing units in an actual circuit is effectively simulated; the test structure is based on the configurable characteristic of the ring oscillator, combines a pin sharing mechanism of the first control signal multiplexing module, realizes parallel test of multiple unit combinations in a single chip, and eliminates multi-chip separate test requirements, so that a high-efficiency and high-coverage standard unit delay detection system is realized under the constraint of hardware resources, and the test efficiency is improved. And a verification basis is provided for deviation analysis of the process simulation model.

The invention belongs to the field of terminal equipment production, and particularly relates to test equipment and a terminal equipment production line. The testing equipment comprises a base, a first conveying line, a second conveying line, a testing structure and a material moving structure, the second conveying line and the first conveying line are arranged in a spaced mode, the testing structure is used for detecting materials, a feeding station and a first discharging station are arranged on the two opposite sides of the base in the first direction respectively, and the first conveying line receives the materials at the feeding station; the first conveying line is used for conveying materials to the testing structure and receiving the tested materials from the testing structure, the material moving structure is used for transferring the unqualified materials from the first conveying line to the second conveying line, the first conveying line discharges the qualified materials to a first discharging station, and the testing structure comprises a testing unit. The multiple testing units are arranged at intervals in the first direction, and all the testing units detect materials in sequence and are used for detecting different parameters of the materials respectively. According to the invention, the test efficiency and the test consistency can be improved.

A method for non-contact modal analysis uses an optical sensing device such as a video camera. Unlike traditional modal analysis, requiring accelerometers or force sensors to measure the modal characteristics of a structure and animate the motion of a wireframe model of the test structure, the inventive system mathematically modifies the original video recordings by filtering, amplifying, and modifying the playback rate or applying modal shape mask or vectors to produce modified video to show motion at each modal frequency. This provides animated mode shapes with higher spatial and temporal resolution that possible with the traditional approach of using wireframe model animations.

The invention provides a test structure and a test method thereof, which are applied to the technical field of semiconductors. In the invention, a first tested element and a second tested element are arranged in a mutually separated manner along a first direction, each pad group comprises a first sub-pad and a second sub-pad which are arranged in a mutually separated manner, electric connecting wires comprise a first electric connecting wire and a second electric connecting wire, and the sizes of the first sub-pad and the second sub-pad are set to be the same. The resistance values of the first electric connecting wire and the second electric connecting wire are the same, so that when the same probe is used for testing the first tested element and the second tested element, the contact resistances between the first sub-bonding pad and the second sub-bonding pad which are the same in size and the probe are the same; the resistance values of the first electric connecting line and the second electric connecting line with the same resistance value can be offset during difference operation, so that the influence of the contact resistance and the resistance of the electric connecting lines in the transistor element on the measurement accuracy of the on-resistance of the transistor element is avoided, namely, the purpose of reducing the measurement error is achieved.

The application relates to the technical field of hydrogen energy transportation and material performance testing, and relates to a test structure for hydrogen permeation testing under a high-pressure gaseous hydrogen environment, a mounting method and application thereof. The test structure comprises a sample body and an insulating sealing assembly, and the sample body is in a double-stage disc structure. The uppermost edge of the first sealing insulating assembly is flush with the upper end surface of the cylindrical platform, and the sample body is matched with the inner side of the first sealing insulating assembly for installation. The second sealing insulating assembly is in an open-upward shape, and the first sealing insulating assembly is matched with the second sealing insulating assembly for installation. The test surface of the sample body of the test structure is kept consistent with the flow field of the gas main stream, and when the test structure is used for testing, the permeation behavior of the hydrogen flow to the material surface can be truly reflected. All clamping and conducting structures are arranged on the outer part of the pipe wall of the test pipeline or the left part of the sample body, so that flow field disturbance is avoided in the main path of the gas flow.

The invention discloses a reduced scale model pile body test structure which comprises a test box, a model pile and a laser scanner, a test soil body is laid in the test box, the model pile is vertically inserted into the test soil body, a reaction wall is installed on one side of the test box, a jack is installed on the reaction wall, and a thrust plate is installed at the front end of the jack; a target is installed on the model pile, and the laser scanner is located above one side of the target. According to the hollow nylon pipe model pile, it is guaranteed that lateral mechanical behaviors are similar, and the material cost and the machining difficulty are greatly reduced; the nylon pipe can also be used as an inclinometer pipe, so that the sensor is convenient to arrange; meanwhile, a grooving pipe inertia moment correction formula is introduced to accurately calculate the actual inertia moment of the grooved pipe, and similar errors are reduced; meanwhile, a strain gauge and a target are matched to comprehensively monitor the model pile from internal deformation, surface strain to top displacement; the surface of the model pile is roughened, so that the surface roughness of the model pile is equivalent to that of a concrete pile, slurry is injected into a pile-soil gap, and the simulation authenticity of the interface friction characteristic is improved.

The invention discloses a semiconductor device parameter testing method and structure, and belongs to the field of semiconductor testing. The testing method comprises the steps that a testing structure is provided, the testing structure comprises a two-dimensional electron gas channel and a multi-end testing pattern, testing branches are arranged at the positions, close to the two ends, in the two-dimensional electron gas channel, and the two ends of the two-dimensional electron gas channel and the testing branches are connected with the testing ends of the multi-end testing pattern in a one-to-one correspondence mode; respectively connecting the test ends connected with the two ends of the two-dimensional electron gas channel with a bias voltage and the ground, and measuring the channel current and the voltage of the test ends connected with the test branches; and calculating one or more of the source end contact resistance, the drain end contact resistance, the channel square resistance and the current surface density of the two-dimensional electron gas channel according to the size parameters of the two-dimensional electron gas channel and the measured voltage and channel current. The method is more accurate in test result, richer in data dimension and high in test flexibility.

The invention discloses a channel mobility testing method and a channel mobility testing structure. The test method comprises the following steps: providing the semiconductor devices, and determining the resistance between the source electrode and the drain electrode of each semiconductor device by applying test voltage to the source electrodes, the drain electrodes and the grid electrodes of at least two semiconductor devices; wherein the test voltages applied to the source electrodes of different semiconductor devices are the same, the test voltages applied to the drain electrodes of different semiconductor devices are the same, and the test voltages applied to the grid electrodes of at least two different semiconductor devices are different; measuring the resistance between the source electrode and the drain electrode of each semiconductor device; and determining the channel mobility of the semiconductor device according to the resistance between the source electrode and the drain electrode of each semiconductor device and the test voltage applied to the grid electrode of each semiconductor device. According to the invention, the measurement of the channel field effect mobility is realized, the measurement mode is simple, and the measurement efficiency is high.

The invention discloses a test structure, a manufacturing method and a test method of resistance of a metal silicide layer, the test structure comprises a substrate, an epitaxial layer and the metal silicide layer, the epitaxial layer is arranged on the substrate, and the metal silicide layer is arranged on the epitaxial layer. According to the invention, the interference of ion implantation is structurally eliminated, and the real resistance characteristic of the metal silicide layer is ensured to be obtained, so that the real states of key process parameters such as the thickness and square resistance of the metal silicide layer, the sizes of a polycrystalline silicon gate and a silicon active region and the like and the uniformity of the key process parameters in a wafer can be accurately reflected; a reliable basis is provided for process monitoring and optimization, and the performance consistency and the manufacturing yield of the device are improved.

The utility model discloses a gel pillow elasticity testing device, which comprises a test board, a pressing test structure and two groups of stress detectors, a test board is arranged on the two groups of stress detectors, limiting mechanisms for limiting a gel pillow are arranged at the front end and the rear end of the top of the test board, and two groups of brackets are arranged on the outer walls of the two sides of the test board. A top plate is connected to the four supports, an adjusting part for adjusting the front-back position of the downward-pressing testing structure is arranged on the left side of the upper surface of the top plate and comprises a U-shaped moving box, the opening end of the U-shaped moving box right faces the top of the top plate, the U-shaped moving box is slidably connected with the top plate, and a connecting rod is installed at the top of the U-shaped moving box. According to the gel pillow elasticity testing device, the adjusting part can adjust the front-back position of the pressure applying instrument on the pressing testing structure, elasticity testing can be conducted on different positions of the irregular face of the gel pillow, the accuracy of the elasticity testing of the gel pillow is improved, the gel pillow can be limited through the limiting mechanism, and the gel pillow is prevented from deviating in the pressing testing process.

The invention discloses a channel mobility testing method, a channel mobility testing structure and a manufacturing method of the channel mobility testing structure. The channel mobility test method comprises the following steps: applying test voltage to source electrodes, drain electrodes and grid electrode structures of at least two different semiconductor devices, and determining resistance between the source electrode and the drain electrode of each semiconductor device; wherein the channel widths of at least part of the semiconductor devices in the at least two different semiconductor devices are different; the channel width is the width of the well region between the JFET region and the first region in the direction from the first region to the JFET region; measuring the resistance between the source electrode and the drain electrode of each semiconductor device; and determining the channel mobility of each semiconductor device according to the resistance between the source electrode and the drain electrode of each semiconductor device and the channel width of each semiconductor device. According to the embodiment of the invention, the measurement of the channel field effect mobility can be realized, the measurement mode is simple, and the measurement efficiency is high.

The application relates to a high-precision addressable ring oscillator test chip, method, device and medium, which comprises an addressing module, an output module and a plurality of ring oscillator test modules; the ring oscillator test module comprises a signal transmission module, a multifunctional test module and a plurality of ring oscillator test structures; the addressing module is used for selecting a ring oscillator test structure from the ring oscillator test structures of the plurality of ring oscillator test modules to perform a communication test; the multifunctional test module can switch the voltage compensation mode or the small-current test mode of the ring oscillator test structure based on a received control signal; when the characteristic parameters of the ring oscillator are measured, the voltage compensation mode can utilize voltage drop compensation to reduce the influence of the resistance voltage drop introduced in the test path, effectively improving the measurement precision, and the small-current test mode can effectively measure the static power supply current of the ring oscillator.

A semiconductor structure includes a back-end-of-line region including a first level of metal interconnects and a second level of metal interconnects separated by at least one interlayer dielectric layer, and a laser debonding test structure disposed in the back-end-of-line region. The laser debonding test structure includes a testable metal plate layer disposed within the at least one interlayer dielectric layer between the first level of metal interconnects and the second level of metal interconnects, a set of test pads, and a set of vias, at least a subset of the set of vias extending from at least one test pad in the set of test pads to the testable metal plate layer disposed within the at least one interlayer dielectric layer between the first level of metal interconnects and the second level of metal interconnects.

The utility model discloses a device for testing the compression resistance of an aluminum shell of a capacitor, which belongs to the technical field of compression resistance testing of the aluminum shell of the capacitor, and comprises a machine base, the two sets of semi-permeable protective cylinders are fixedly connected to the machine base, the upper ends of the two sets of semi-permeable protective cylinders extend to the truss, and the bottoms of the semi-permeable protective cylinders communicate with the exterior of the machine base through waste liquid pipes; two groups of clamping mechanisms; according to the utility model, the capacitor aluminum shell to be tested is placed in the corresponding semi-permeable protective cylinder, the electric cylinder drives the clamping mechanism to clamp and position the capacitor aluminum shell, the high-pressure liquid pressurized by the gas-liquid booster pump in the pressurizing pipe is injected into the capacitor aluminum shell to be tested, and the pressure of the pressure gauge and the liquid leakage condition of the capacitor aluminum shell are observed. The two groups of test structures are designed independently, so that the other group of structure is in a test state while one group of structure clamps the capacitor aluminum shell to be tested, and the test continuity is ensured.

A semiconductor test structure includes a substrate, a plurality of gate structures on the substrate, a plurality of thin-film resistive layers, each of the thin-film resistive layers being respectively over one of the plurality of gate structures, and a plurality of gate structures on the substrate, each of the plurality of thin-film resistive layers being respectively over the other one of the plurality of gate structures, each of the plurality of thin-film resistive layers being respectively over the other one of the plurality of gate structures. The plurality of thin film resistor layers are arranged in a dielectric layer, the test circuit layer is arranged on the dielectric layer and is in a square waveform pattern from a top view, and the two contact pads are respectively connected with two ends of the test circuit layer.

The invention belongs to the technical field of semiconductor packaging, and provides an online monitoring method and system for thermal cycle failure of TSV copper salient points, and the method comprises the steps: synchronously collecting resistance data and acoustic emission signals of a test structure containing the TSV copper salient points, and writing the resistance data and acoustic emission signals into a data cache region; calculating a resistance change rate relative to an initial value based on the resistance data in the data cache region, and generating a primary trigger event when the resistance change rate exceeds a real-time judgment threshold value; in response to the primary trigger event, estimating physical coordinates of the abnormal activity; scanning the region of interest taking the physical coordinates as the center to obtain local deformation data, and fusing the physical coordinates, the local deformation data and the resistance change rate to generate a failure diagnosis conclusion; and based on the failure diagnosis conclusion, carrying out backtracking analysis on historical data before the primary trigger event occurs in the data cache region, and adaptively adjusting a real-time judgment threshold, so that real-time monitoring and intelligent diagnosis of the TSV copper bump thermal cycle failure are realized.

A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.

The utility model relates to an FPC integrated automatic test equipment, including transmission band support, loading transmission band, FPC loading plate, front side test structure, overturn structure, reverse side test structure, the loading transmission band is connected in the transmission band support, a plurality of groups of FPC loading plates are arranged on the loading transmission band at equal intervals, the overturn structure is arranged on the front side test structure, the reverse side test structure is arranged on the reverse side test structure, and the reverse side test structure is arranged on the reverse side test structure. The front testing structure is fixed on the conveying belt support, the overturning structure is fixed on the conveying belt support, and the back testing structure is fixed at the top end of the overturning structure. According to the utility model, the arrangement of the FPC detection structure is optimized, the traditional FPC detection mode is changed, the detection equipment with the overturning function is designed, and the overturning structure is simple, convenient to maintain and use and suitable for popularization and use.

The invention provides a test screening method and system for enhancing electrical interference resistance of a chip, and belongs to the technical field of integrated circuit testing, and the method comprises the steps: building a topological network interference model which comprises a topological connection relation among a chip power pin, a grounding pin and a signal pin, the interference source parameters are set according to the rated voltage range and the interference distance of the chip; constructing an interference path to form three groups of test structures; obtaining current distribution parameters, including determining an initial current value, calculating a voltage drop value and determining a test current value; executing an interference simulation test; when the simulation result meets a preset condition, dynamically adjusting the distance between the test structures in the topological network interference model to form an optimized test model; and performing chip batch screening according to the optimized test model, constructing an accurate interference model according to a topology network theory, optimizing current distribution parameters, dynamically adjusting a test structure, and realizing high-precision test and efficient screening of the anti-electrical interference capability of the chip.

The application provides a simple gate oxide integrity testing device, which comprises a test sample and a test structure; the test sample comprises a substrate, a dielectric layer (gate oxide layer) on the substrate, a gate replacement layer used for replacing a gate layer or being located above the gate layer, so that the test sample forms a three-layer structure comprising the substrate-dielectric layer-gate replacement layer, and the gate oxide integrity of the dielectric layer is tested by combining a thermal desorption technology; the test structure is used for accommodating the test sample, providing a test temperature, and recording released elements; the application also provides a simple gate oxide integrity testing method, which has the technical effects of low cost, simple operation, and rapid feedback of test results, and does not need to prepare a transistor device, adopts the gate replacement layer arranged on the substrate-dielectric layer (gate oxide layer) to combine the thermal desorption technology, and directly tests the stacked layer material contained in a MOS stacked layer structure.

A test structure and test method are disclosed. The test structure includes: a substrate; a first electrode located on the substrate, the first electrode serving as a first test terminal or electrically connected to a first test terminal; a second electrode located on the substrate to the side of the first electrode, the second electrode serving as a second test terminal or electrically connected to a second test terminal; and a first dielectric layer located between the first electrode and the second electrode. The test structure of this invention can be used to obtain the values ​​of electrical parameters between the first test terminal and the second test terminal, thereby obtaining the quality status of the first dielectric layer based on the values ​​of these electrical parameters. This facilitates quality monitoring of the first dielectric layer between the first electrode and the second electrode, and correspondingly, it also helps to obtain the quality status of the semiconductor structure, thereby facilitating improvements to the semiconductor manufacturing process.

The application provides a test rack for semiconductor package testing, which comprises a test base, a placement plate arranged on the top of the test base, a plurality of test slots for placing semiconductor to be tested arranged on the top of the placement plate, and a plurality of first ventilation slots arranged on one side of the placement plate; a test structure is arranged on the top of the test base, and the test structure comprises a detection device and a detection needle for detecting the semiconductor to be tested; a plurality of test benches are arranged in the plurality of test slots respectively, and each test bench comprises a bearing seat, a cooling base arranged at the bottom of the bearing seat, an adsorption air duct formed between the bearing seat and the cooling base, a plurality of adsorption holes arranged on the top of the bearing seat, and a plurality of bearing columns arranged in the plurality of adsorption holes and located at adsorption positions or ejection positions, so that negative pressure adsorption and bottom heat dissipation are realized; test boxes with cooling air ducts are arranged on both sides of the cooling base, and the test boxes are internally provided with slidable semiconductor test pins; during testing, the semiconductor test pins are pressed down to enter the cooling air ducts to realize heat dissipation of contact parts, and the test stability is improved.

This invention discloses an emergency start test method for Fuxing high-speed trains, comprising the following steps: confirming before the test that the overhead contact line has been de-energized and the train is in a battery disconnected state; preparing the connection fixtures for the test; confirming that the auxiliary air compressor, pantograph, and vacuum circuit breaker are functioning normally; using testing software to confirm that the converter is functioning normally; and restoring the test structure to its original state. This invention enables the completion of an emergency start test of the train under conditions of no power to the overhead contact line and no high voltage supply to the train, avoiding the risk of high voltage grounding, improving work efficiency, fundamentally eliminating the risk of overhead contact line grounding and overcurrent melting caused by EGS misoperation, and improving work safety.

The utility model discloses sealing performance test equipment for valve production, which comprises a base, a control case is fixedly mounted on the right side of the outer surface of the upper end of the base, a test board is fixedly mounted on the left side of the outer surface of the upper end of the base, and a lifting test structure is fixedly mounted on the upper portion of the test board. An auxiliary feeding structure is arranged at the front end of the testing table, the auxiliary feeding structure comprises a lifting seat, a fixing plate, a guide column, a connecting block, a hydraulic rod, a first supporting frame, a supporting roller, a connecting shaft, a guide groove, a mounting groove and a second supporting frame, the fixing plate is fixedly mounted on the outer surface of one side of the base, and the lifting seat is located on the upper portion of the fixing plate. According to the sealing performance testing equipment for valve production, through the arrangement of the auxiliary feeding structure, workers can be conveniently assisted to feed valves, physical exhaustion of the workers is reduced, and safety during feeding is improved.

The utility model relates to a test structure and a semiconductor structure, a test pad and a test lead are connected with a metal layer and a metal plug to form at least one test circuit, and when open circuit defect detection is carried out on the metal layer or the metal plug, the test circuit formed by the metal layer or the metal plug is detected. Whether the open-circuit defect exists in the metal layer or the metal plug can be determined according to the test result, the open-circuit defect of the metal layer or the metal plug can be detected on line in the manufacturing process of the semiconductor chip, and meanwhile the defect position can be located according to the test result. The detection efficiency is improved, the detection cost is reduced, and the detection rate and the detection accuracy are improved.

This invention provides a test structure and its test method. The test structure includes a first electrode structure, a dielectric layer, and a second electrode structure stacked sequentially. The first electrode structure includes a first insulating layer and a first electrode layer embedded in the first insulating layer. The dielectric layer includes a first portion and a second portion surrounding the outside of the first portion. The second electrode structure includes a second electrode layer. The first electrode layer and the second electrode layer are arranged opposite each other. The first portion is located between the first electrode layer and the second electrode layer. On the side of the first electrode layer, the first insulating layer covers the second portion. A plurality of release holes are formed in the first insulating layer. All release holes are spaced around the outside of the first portion. The test structure can automatically measure and obtain the side-cut distance of the sacrificial layer before and after the sacrificial layer release cavity structure process by a testing machine, thereby improving the measurement accuracy and testing efficiency of the side-cut distance and saving testing time and labor costs.