1331 results about "Test structure" patented technology

The invention relates to the technical field of pipe bracket testing, in particular to a thermal insulation pipe bracket overall strength displacement overload testing device and method.The thermal insulation pipe bracket overall strength displacement overload testing device comprises a bearing base and further comprises a pipe bracket base arranged on the upper side of the bearing base, a connecting pipe bracket is installed at the upper end of the pipe bracket base, a clamping plate is clamped to the upper side of the bearing base, and a rotating shaft is arranged on the clamping plate in a penetrating mode; the bottom end of the rotating shaft is clamped and connected with a connecting gear, and an annular groove is formed in the edge of the upper side of the bearing base. According to the invention, the axial and radial strength of the pipe bracket can be tested in the displacement overload test process, the use limitation is low, the automation degree is high, the test efficiency of the heat insulation pipe bracket is obviously improved, the situation that the pipe bracket is broken to injure people due to broken objects in the displacement overload test process of the pipe bracket can be avoided, and the test efficiency is improved. The displacement overload test structure has a good safety protection function, is high in use safety, and also realizes a step-by-step disassembly function of the displacement overload test structure, so that barrier-free maintenance of the test structure is facilitated.

The invention relates to the technical field of rock mass testing, in particular to a tunnel water-rich fault fracture zone area loading simulation test device and method.The tunnel water-rich fault fracture zone area loading simulation test device comprises a test box, and a partition plate is arranged in the test box; the partition plate divides the test box into a first area and a second area, and the second area is filled with a rock-soil sample; a lateral loading structure; a vertical loading structure; the simulated fault test structure comprises a mounting frame fixedly connected to the partition plate, a driving structure and a simulated fault unit, one end of the driving structure is hinged to the mounting frame, and the other end of the driving structure is connected with the simulated fault unit; the fault simulation unit is hinged to the mounting frame and used for simulating an adjustable fault, and the technical problems that an existing test device cannot dynamically adjust the fault fracture width and the dip angle according to the load effect and cannot perform real-time coupling simulation on a hydrological seepage field are solved.

The invention belongs to the technical field of performance testing, and particularly discloses an intelligent testing system and method for the impedance performance of an HDI circuit board, and the method comprises the steps: immediately starting an interlayer collection module after the lamination of each line layer, carrying out the electrical precise alignment through a POFV test structure, and collecting the in-situ impedance data; the diagnosis prediction module analyzes and processes the data, generates an impedance deviation parameter set, calculates an impedance performance standard coefficient fused with a layer influence factor, and analyzes and outputs a trend result through a time sequence; the impedance state judgment module carries out abnormity judgment based on a preset rule according to the standard coefficient and the trend result; when the judgment result is abnormal, an adjustment triggering marking module is started; and finally, a test report output module generates a test report containing the impedance performance score and the impedance performance distribution of the whole board. According to the invention, layer-by-layer, real-time and closed-loop intelligent test and regulation of impedance performance are realized, and product quality and production efficiency are effectively improved.

The invention discloses a detection method for representing interface roughness of an interconnection structure by using low-frequency noise. According to the method, constant low current is applied to a to-be-tested structure, output current of the to-be-tested structure is measured, and then random current fluctuation generated by interaction of electrons and interconnection structure interfaces, defects and phonons is obtained; fourier transform is carried out on random current fluctuation to obtain frequency domain parameters of the current; calculating the power spectrum density of random current fluctuation according to the frequency domain parameter of the current; wherein the PSD is proportional to the f, and then fitting is carried out to obtain a slope k; and evaluating the interface roughness of the interconnection structure by using the slope k. According to the method, the experiment can be rapidly completed under the condition that the sample is not damaged, and the reusability of the sample is improved. In addition, the low-frequency noise characterization method does not need direct contact or imaging, is suitable for testing packaged chips, and can measure the overall roughness of long interconnection line segments at the same time.

The invention relates to the technical field of semiconductor testing, in particular to a radio frequency testing bonding pad and a radio frequency testing structure. The radio frequency test pad comprises a substrate; the connection supporting layer is located on the substrate, and the connection supporting layer comprises a metal layer; the connection ports are located on the connection supporting layer, and the connection ports comprise a grounding port and a signal port; the grounding port is conductively connected through the metal layer; the signal port and the metal layer are not conductive. The signal port and the metal layer are arranged to be non-conductive, so that potential difference between the signal port and a structure below is avoided, parasitic capacitance is inhibited, and the accuracy of radio frequency testing is further improved.

The utility model provides a flat plate type transfer ironing machine test structure for simulating white dots of a roller type transfer ironing machine, which comprises a flat plate type transfer ironing machine, the flat plate type transfer ironing machine comprises a bottom plate and a heating plate, transfer printing paper and a printing stock are arranged between the heating plate and the bottom plate, and a breathable carrier is arranged on one surface of the transfer printing paper, which is not contacted with the printing stock. The number of white dots after transfer printing of the flat plate type transfer ironing machine is increased; compared with the prior art, the air permeability of the periphery of the transfer printing paper is changed, so that the transfer printing effect on the flat plate type transfer ironing machine can be close to that of a roller type transfer ironing machine, and white spots which can appear on the roller type transfer ironing machine but cannot appear on the flat plate type transfer ironing machine can be transferred by the flat plate type transfer ironing machine; transfer paper manufacturers can adjust the process in time and improve the transfer paper.

The invention discloses a semiconductor test structure and a test method thereof, and belongs to the field of semiconductors. The test structure comprises at least two metal layers arranged on a substrate, the metal layers at least comprise a lower metal layer and an upper metal layer, the lower metal layer is arranged close to the substrate and at least comprises a test area, a test area, a contrast area and a reference area, the test area is arranged between the test area and the contrast area, and the reference area is arranged between the test area and the contrast area. The reference area is arranged on one side of the test area, the inspection area and the contrast area, and the upper metal layer is arranged on the test area, the contrast area and the reference area; the metal plug is arranged between the upper metal layer and the lower metal layer; the first bonding pad is arranged on the upper metal layer on the reference region; the second bonding pad is arranged on the upper metal layer on the test area; and a third pad disposed on the upper metal layer on the contrast region. According to the semiconductor test structure and the test method thereof provided by the invention, the position of an electric leakage defect in the semiconductor structure can be accurately positioned.

The invention discloses electronic detonator spot welding defect detection equipment which comprises a bottom bearing plate, a telescopic fixing structure is arranged at the upper end of the bottom bearing plate, a circulating feeding structure is arranged in the telescopic fixing structure, and a testing structure is arranged at the upper end of the telescopic fixing structure. The telescopic fixing structure comprises side supporting plates symmetrically and fixedly arranged on the top face of the bottom bearing plate. According to the electronic detonator spot welding defect detection equipment provided by the invention, the telescopic fixing structure is arranged, and two groups of transverse electric push rods which are symmetrically arranged drive clamping plates at the upper ends to get close to each other, so that electronic detonator control plates with different sizes on the surface of the top plate can be fixed; and meanwhile, a longitudinal electric push rod is matched to drive a test meter and a test needle head on the top to descend to be in contact with a welding spot on the surface of the control panel, so that whether the welding spot has pseudo soldering or not can be detected, compared with an existing detection device, the detection efficiency of the control panel can be effectively improved, and meanwhile higher adaptability is achieved for control panels of different sizes.

The invention discloses a shaft current test structure and method for a motor EMC (Electro Magnetic Compatibility) on-load test system, which are based on a shaft current test structure with a test unit, test shaft current on a test shaft by using a current probe and obtain shaft current data through an EMI (Electro Magnetic Interference) receiver and a computer; the method is simple, convenient and rapid to operate and high in test efficiency, an existing motor EMC on-load test system does not need to be greatly changed, a current probe is adopted to test the shaft current, non-invasive measurement is adopted, and interference to normal operation of the system is reduced to the maximum extent; according to the invention, the problems that the current shaft current test method only focuses on the shaft current test of the motor itself, the comprehensiveness and reliability are poor, and the shaft current test requirement of the motor EMC on-load test system is difficult to meet can be effectively solved; the influence of the shaft current on the motor EMC on-load test can be explored, and the correlation degree and the action mechanism between the shaft current and the electromagnetic compatibility can be deeply analyzed and evaluated.

The invention discloses a mechanical and ground stress combined loading device based on an underground structural member and a loading method thereof, and relates to the technical field of explosion tests. The dynamic response problem of an existing underground structure under the coupling action of soil stress and explosive load is solved. The device comprises an explosive load applying system and a surrounding stress applying system. The explosion load applying system comprises a lifting mechanism, a guide rail, a drop hammer and a test model; the confining stress applying system applies horizontal confining pressure and vertical confining pressure to the test model; the lifting mechanism drives the drop hammer to realize lifting at different heights; the drop hammer applies a vertical uniformly-distributed explosion-like load to the test model; an enclosure structure is arranged at the top of the test model, and sandy soil is arranged in the enclosure structure; a cover plate is arranged at the top of the enclosure structure, a cushion layer is arranged on the cover plate, and a buffer is arranged on the cushion layer; strain gauges are arranged on the surface of the bottom of the test model; and pressure sensors are arranged in the sand dispersion layer and on the inner surface of the test structure model. The method is suitable for underground structure anti-explosion overall effect model test research.

The invention provides a semiconductor test structure and a test method thereof. The semiconductor test structure is arranged on a scribing channel of a wafer, and comprises a transistor which comprises a substrate, a source electrode, a drain electrode and a grid electrode; the electric fuse comprises a first end and a second end; wherein the source electrode is electrically connected to the first bonding pad through a first metal wire, the second end of the electric fuse is electrically connected to the second bonding pad through a second metal wire, the drain electrode, the substrate and the first end of the electric fuse are electrically connected to the third bonding pad through corresponding third metal wires, and the grid electrode is electrically connected to the fourth bonding pad through a fourth metal wire. Voltage is applied to the first bonding pad, the second bonding pad, the third bonding pad and the fourth bonding pad by adopting a preset rule so as to test the resistance of the electric fuse and the performance of the transistor. According to the technical scheme, the resistance of the electric fuse and the performance of the transistor can be simultaneously monitored in the line in the wafer manufacturing process, the process is rapidly adjusted, and the flexibility of the process is improved.

The embodiment of the invention provides a semiconductor test structure and a manufacturing method thereof, and the semiconductor test structure comprises a test array region which comprises test active regions arranged in an array. The plurality of test conductive wire groups are arranged along the first direction, each test conductive wire group comprises two test conductive wires which are adjacently arranged and a connecting part which is connected with the first ends of the two test conductive wires, each test conductive wire extends and penetrates through the test array area along a second direction, and the second direction is perpendicular to the first direction. And the at least one electric connection structure and the two external connection structures are located on the second ends of the test conductive wires in the plurality of test conductive wire groups, and the first ends and the second ends of the test conductive wires are opposite to each other. The at least one electric connection structure is electrically connected with the adjacent test conductive wires in the adjacent test conductive wire groups in the plurality of test conductive wire groups, and the two external connection structures are electrically connected with the two outermost test conductive wires in all the test conductive wires in the plurality of test conductive wire groups respectively.

The invention discloses a combined load synchronous application testing device. The technical problems that in the prior art, the load applying mode is single, and the combined load cannot be synchronously applied are solved. The device comprises a connecting mechanism and a load applying mechanism, wherein the load applying mechanism comprises a torsional load applying structure, a load transmitting structure and a multi-linkage testing structure. The load transmission structure comprises a special-shaped stress plate and a torsional load transmission assembly, and the torsional load transmission assembly comprises a connecting chuck and a torque plug-in. By controlling the rotation of the torsion load transmission assembly, a pure torsion load applying mode or a conversion mode of converting torsion motion into radial load can be selectively realized, and multi-directional load detection is realized. The invention further provides a combined load synchronous applying function, the single driving source synchronously activates the torsion load path and the radial load path by adjusting the geometric positions of the torque plug-in and the load adjusting plate on the connecting chuck, and synchronous applying of the torsion load and the radial load is achieved.

The invention provides a semiconductor device, a cutting method thereof and a semiconductor chip, relates to the technical field of semiconductor chips, and aims to solve the technical problem that the packaging yield of the semiconductor chip is low. The semiconductor device comprises a substrate, a plurality of semiconductor units and a plurality of test structures, wherein the plurality of semiconductor units and the plurality of test structures are located on one side of the substrate. The plurality of semiconductor units are distributed in an array, and at least part of the plurality of test structures is located between two adjacent semiconductor units. In the two adjacent semiconductor units and the test structure between the two adjacent semiconductor units, the distance between one semiconductor unit and the test structure is smaller than the distance between the other semiconductor unit and the test structure. The semiconductor chip obtained by cutting the semiconductor device is applied to a three-dimensional memory so as to realize data reading and writing operation.

The invention relates to the technical field of aero-engine tests, in particular to an aero-engine turbine blade cooling effect test optical test structure which comprises optical glass, an outer casing and an optical channel pipe. The optical glass is located on the light-in side of the optical channel pipe, and the light-out side of the optical channel pipe faces the target blade. The outer casing is arranged on the outer side of the optical channel pipe in a sleeving mode, and a cooling channel is formed between the inner wall of the outer casing and the outer wall of the optical channel pipe so as to cool the optical channel pipe; a gas film ring is connected between the optical glass base and the light inlet side of the optical channel pipe in a sealed mode and located on the light outlet side of the optical glass. The optical glass base is provided with the cooling gas inlet, and the gas film ring is provided with the gas jet hole, so that the cooling gas performs jet sweeping on the light emitting surface of the optical glass and enters the optical channel pipe to cool the optical channel pipe, thereby improving the accuracy of the cooling effect test result of the turbine blade.

The invention is suitable for the technical field of solar cells, and provides a back contact solar cell, a cell assembly and a photovoltaic system. The first fine grids and the second fine grids are arranged on the back surface of the silicon substrate; the at least one group of first bonding pads are arranged on the back surface of the silicon substrate, and the first bonding pads are electrically connected with the first fine grids; the at least one group of second bonding pads are arranged on the back surface of the silicon substrate and are electrically connected with the second fine grids; the first test structure comprises two third bonding pads which are arranged at intervals in the first direction, and the third bonding pads are electrically connected with the first fine grids; the third bonding pad and the first bonding pad are the same in size; the second testing structure comprises two fourth bonding pads which are adjacently arranged in the first direction, the fourth bonding pads are electrically connected with the second fine grids, and the fourth bonding pads and the second bonding pads are the same in size. According to the back contact solar cell provided by the invention, the carrier collection effect of the fine grid can be improved, and the printing cost of the back contact solar cell can be reduced.

The invention discloses a semiconductor test structure and a test method thereof. According to the invention, the P-type well regions and the N-type well regions which are alternately distributed are formed in the active region, and the S-shaped active region metal silicide strips serving as S-shaped test structures are formed on the surface of the active region; the two ends of the snakelike active region metal silicide strip are located above the well regions of different conduction types respectively, so that the snakelike active region metal silicide strip covers the surfaces of the PN junctions which are connected in series; through the snakelike test structure, the square resistance of the snakelike active region metal silicide strip can be accurately measured, whether electric leakage exists in the substrate or not is detected, and whether continuity of the snakelike active region metal silicide strip is abnormal or not and whether bridging exists or not is detected. Furthermore, a cross comb-shaped test structure used for measuring the breakdown voltage of the metal silicide layer of the active region to judge whether the isolation between the active regions meets the requirement is formed in the region where the snake-shaped test structure is located, so that the comprehensiveness of the test structure can be improved, and the test area of a test pattern in a chip is saved; the area utilization rate is effectively improved.

The invention relates to the technical field of hydrogen energy conveying and material performance testing, in particular to a testing structure for hydrogen permeation testing in a high-pressure gas-phase hydrogen environment and an installation method and application of the testing structure. The testing structure comprises a sample body and an insulation sealing assembly, and the sample body is of a double-step disc structure; the uppermost edge of the first sealing insulation assembly is flush with the upper end face of the cylindrical platform, the sample body is installed on the inner side of the first sealing insulation assembly in a matched mode, the second sealing insulation assembly is in a shape with an upward opening, and the first sealing insulation assembly is installed in the second sealing insulation assembly in a matched mode. The test surface of the sample body of the test structure and the gas main flow keep a consistent flow velocity field, and when the test structure is used for testing, the permeation behavior of the hydrogen flow on the material surface can be truly reflected; all the clamping and conducting structures are arranged outside the pipe wall of the test pipeline or at the left part of the sample body, so that flow field disturbance is prevented from being introduced into a main airflow path.

The invention relates to a locomotive articulation device testing device and method, and belongs to the technical field of locomotive articulation devices, and the device comprises a testing structure platform which is used for installing an articulation device so as to test the articulation device; the hydraulic driving unit is used for driving the test structure platform to simulate the operation condition of the locomotive to rotate; and the electric control operation table is used for testing logic control and collecting and processing test data so as to generate a test result. By adopting the locomotive articulator testing device, the damping performance of a trackless locomotive articulator damping control system under various operation conditions can be more accurately tested, and the stability of the performance of the articulator in the actual operation process of a trackless rubber-tyred vehicle is ensured.

The invention relates to a three-dimensional sensing, storing and computing integrated structure and a manufacturing method and a testing structure thereof, belongs to the technical field of semiconductors, and solves the problem that the existing three-dimensional integration method faces the shortage of resource allocation of a rewiring layer. The manufacturing method of the three-dimensional sensing, storing and computing integrated structure comprises the following steps: forming a fan-out packaged processor, a memory and an image sensor through a subsequent process; mounting the fan-out type packaged processor on a substrate in a surface mounting manner; bonding the memory to the upper part of the processor of the fan-out type package; and inverting the image sensor, bonding the image sensor above the memory, and routing the image sensor from the memory to the substrate. According to the manufacturing method of the three-dimensional sensing, storing and computing integrated structure, a manufacturing method of a three-dimensional testability design structure is provided, and joint testing among an image sensor, a memory and a processor is achieved.

The invention discloses a mismatch test structure and a forming method, a test method and a modeling method thereof, and the forming method comprises the steps: providing a to-be-tested device which comprises a substrate and a semiconductor device layer, and forming an array comprising a plurality of repeated device units in the semiconductor device layer, and selecting MOS transistors of the same type from the adjacent device unit groups as a to-be-tested mismatch module, wherein each MOS transistor in the to-be-tested mismatch module is provided with an adjacent MOS transistor which is commonly connected with the source end of the MOS transistor when the device works normally and an adjacent MOS transistor which is not commonly connected with the source end of the MOS transistor when the device works normally. MOS transistors of the same type are selected from adjacent device unit groups to serve as a to-be-tested mismatch module, each MOS transistor is provided with an adjacent transistor which is connected with a source end in common mode and is not provided with a source end in common mode, and the mismatch characteristics of the source end of each MOS transistor in a common connection state and a non-common connection state are tested at the same time.

The invention provides semiconductor device thermal resistance measuring equipment, which is applied to the technical field of electrical variable measurement and comprises a case, a workbench fixed at the top of the case, a constant-temperature base arranged in the middle of the workbench, a rack arranged on one side of the workbench and erected above the constant-temperature base, a thermal resistance detector matched with the rack, and a temperature sensor arranged on the thermal resistance detector. The top of the rack is provided with a pressing mechanism which can press and abut against the semiconductor device to be tested towards the upper end face of the constant-temperature base. The middle part of the upper end surface of the constant-temperature base is provided with a flexible heat-conducting contact pad used for self-adapting to the shape of a semiconductor device to be tested, and the flexible heat-conducting contact pad is internally provided with a temperature control assembly; and an environment simulation mechanism is matched on the pressing mechanism. The thermal resistance testing device has a high-adaptability and high-precision thermal resistance testing structure, can adapt to semiconductor devices in various shapes for testing, can simulate the actual application environment of the semiconductor devices, can provide reliable data support for thermal management design of the semiconductor devices, and is good in overall use effect.

The invention relates to an airflow sensor testing structure and a packaging method and packaging structure thereof, each chip unit of an airflow sensor wafer is composed of a substrate (1), a vibrating diaphragm (2) and a back plate which are stacked, the substrate (1) is provided with a back cavity (42) penetrating in the thickness direction of the substrate (1), a slot (10) is formed in the bottom of the substrate (1), and the vibrating diaphragm (2) is arranged in the slot (10). The open groove (10) penetrates through the substrate (1) and the back cavity (42), and the open groove (10) is used for establishing a continuous air flow path in a space outside the back cavity (42) and the air flow sensor. During packaging, the airflow sensor chip is fixed on the packaging substrate through silica gel, a packaging shell is installed outside the airflow sensor chip, the open groove (10) is filled with the silica gel, and blocking and sealing of the open groove (10) are achieved. According to the invention, the requirement of each tube core on the test wafer can be met, the production cost is not increased, and the risk of wafer fragmentation can be effectively avoided.

The invention discloses a pipeline integrated attitude control rocket engine thrust test structure and a working method thereof, and belongs to the technical field of sensing measurement and control. The testing structure is composed of a front fixed frame, a rear fixed frame, a rear movable frame, a middle-layer movable frame, a front movable frame, a straight connecting beam, a front-end inclined connecting beam, a propellant supply pipeline, a rear-end inclined connecting beam, a sensitive beam, a thin film sensor and a supporting thin beam. The thrust generated by rocket eruption enables the engine and the adapter frame to displace, then a series of structures from the front movable frame to the rear movable frame are driven to move step by step in the horizontal direction, strain function film layers of the four film sensors on the sensitive beam are deformed, and finally a differential Wheatstone bridge is formed by the circuit board for testing. According to the invention, the film sensor and the propellant supply pipeline are integrated on the test structure, and the S-shaped propellant supply pipeline, the circular truncated cone type movable frame structure and the layered overall structure are designed, so that the sensitivity of the test sensor is remarkably improved while the high rigidity of the test device is ensured.

The invention discloses a selector unit for dynamic switching of a standard unit, a ring oscillator and a test structure. Wherein the selector unit is connected in parallel with standard units with different threshold voltages, driving capabilities and logic functions, and is matched with the first switch control circuit, so that flexible switching of the differentiated standard units is realized, and the static architecture limitation of a traditional test circuit is broken through; according to the ring oscillator, a selector unit is embedded into a closed oscillation loop of a standard unit chain, a time sequence path of multiple unit combinations is formed through dynamic configuration, and the delay superposition effect between mixing units in an actual circuit is effectively simulated; the test structure is based on the configurable characteristic of the ring oscillator, combines a pin sharing mechanism of the first control signal multiplexing module, realizes parallel test of multiple unit combinations in a single chip, and eliminates multi-chip separate test requirements, so that a high-efficiency and high-coverage standard unit delay detection system is realized under the constraint of hardware resources, and the test efficiency is improved. And a verification basis is provided for deviation analysis of the process simulation model.

The utility model relates to a test structure and a semiconductor structure. The test structure comprises a plurality of test units arranged in a two-dimensional array and at least one row of liner units, and each liner unit comprises a plurality of liners arranged at intervals; in the row direction of the two-dimensional array, the test units and the pads are alternately arranged, and at least two adjacent rows of test units share the same row of pad units; the test structure is arranged in a cutting channel of a wafer, and the line direction is parallel to the extending direction of the cutting channel. The semiconductor structure comprises an exposure area, a first cutting channel arranged around the exposure area, a second cutting channel arranged in a residual area around the exposure area and the test structure, the extension direction of the first cutting channel is parallel to a short axis direction, and the extension direction of the second cutting channel is parallel to a long axis direction. And the long axis direction and the short axis direction are respectively the length direction and the width direction of the exposure area. According to the invention, the effective usable area of the wafer is improved on the premise of ensuring the effectiveness of the acceptance test of the wafer.

The invention discloses a through hole test structure, a test method and an integrated circuit, and belongs to the technical field of semiconductors, the through hole test structure at least comprises a bottom metal layer, a top metal layer and a middle metal layer; the through hole layer is connected with the two metal layers, the through hole layer comprises a first type of connecting structure and a second type of connecting structure, the first type of connecting structure comprises a first number of through holes, the second type of connecting structure comprises a second number of through holes, and the second number is greater than the first number; wherein the bottom through hole layer or the top through hole layer comprises at least one first type of connecting structure, and at least one first type of connecting structure is additionally arranged at any position of the current through hole layer except the position of the first type of connecting structure of the upper layer in the lamination direction of the through hole layers. Through the through hole test structure, the test method and the integrated circuit provided by the invention, the accuracy of abnormal detection of the through hole can be improved.

The invention relates to the technical field of bidirectional force application test structures, and provides a bidirectional force application test structure, which comprises a DOCK pushing driving assembly, a key striking driving assembly and an LDCM key card insertion module, and is characterized in that the LDCM key card insertion module comprises a module mounting seat, and the module mounting seat is provided with a needle mold assembly used for abutting a plug-in card and a plug-in card mounting seat used for fixing the plug-in card; the plug-in card installation seat is provided with an LDCM plug-in card, a plug-in card positioning groove, an upper overturning block used for pressing an upper button of the button type plug-in card and a lower overturning assembly used for pressing a lower button of the button type plug-in card, and the lower overturning assembly is located on the side, opposite to the upper overturning block, of the plug-in card positioning groove and is in linkage with the upper overturning block. The LDCM plug-in card is installed in the plug-in card positioning groove and is provided with an upper button and a lower button. And the press key driving assembly drives the upper overturning block to overturn or reset.

The invention relates to the field of integrated circuit testing, provides an SRAM (Static Random Access Memory) fault testing structure, and particularly relates to an IEEE (Institute of Electrical and Electronic Engineers) 1687 standard and an SRAM self- According to the method, a common fault model of an SRAM (Static Random Access Memory) is analyzed, improvement is performed on the basis of a March C-algorithm, and a March C-pro algorithm capable of covering most common faults of the SRAM is derived; a modularized SRAM self-test structure is designed based on a March C-pro algorithm, so that the design cost caused by built-in self-test of a memory and possible additional interface requirements are avoided; a multi-layer network structure based on the IEEE 1687 standard is designed, access to an embedded instrument is achieved, an SRAM self-test module is connected, and an SRAM test in the SOC is achieved.

The invention belongs to the field of terminal equipment production, and particularly relates to test equipment and a terminal equipment production line. The testing equipment comprises a base, a first conveying line, a second conveying line, a testing structure and a material moving structure, the second conveying line and the first conveying line are arranged in a spaced mode, the testing structure is used for detecting materials, a feeding station and a first discharging station are arranged on the two opposite sides of the base in the first direction respectively, and the first conveying line receives the materials at the feeding station; the first conveying line is used for conveying materials to the testing structure and receiving the tested materials from the testing structure, the material moving structure is used for transferring the unqualified materials from the first conveying line to the second conveying line, the first conveying line discharges the qualified materials to a first discharging station, and the testing structure comprises a testing unit. The multiple testing units are arranged at intervals in the first direction, and all the testing units detect materials in sequence and are used for detecting different parameters of the materials respectively. According to the invention, the test efficiency and the test consistency can be improved.