Patents
Literature
Patsnap Copilot is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Patsnap Copilot

2931 results about "Test structure" patented technology

Structural testing is the type of testing carried out to test the structure of code. It is also known as White Box testing or Glass Box testing. This type of testing requires knowledge of the code, so, it is mostly done by the developers.

Dual probe test structures for semiconductor integrated circuits

Disclosed is a semiconductor die having an upper layer and a lower layer. The die includes a lower test structure formed in the lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end, wherein the first end is coupled to a predetermined voltage level. The die also has an insulating layer formed over the lower metal layer and an upper test structure formed in the upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure, and the upper metal layer being formed over the insulating layer. The die further includes at least one probe pad coupled with the upper test structure. Preferably, the first end of the lower test structure is coupled to a nominal ground potential. In another implementation, the upper test structure is a voltage contrast element. In another embodiment, a semiconductor die having a scanning area is disclosed. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The die includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The first plurality of test structures or the second plurality of test structures has a probe pad coupled to at least one test structure.
Owner:KLA TENCOR TECH CORP

Apparatus and methods for determining and localization of failures in test structures using voltage contrast

Disclosed is test structure that can be fabricated with minimal photolithography masking steps and in which defects may be localized to specific layers. Mechanisms for fabricating such test structures are also provided. In one embodiment, a semiconductor test structure suitable for a voltage contrast inspection is provided. The test structure includes one or more test layers corresponding to one or more product layers selected from a plurality of product layers of an integrated circuit (IC) product structure. The number of the selected one or more test layers is less than a total number of the plurality of product layers of the product structure, and the test layers include at least a first portion that is designed to have a first potential during the voltage contrast inspection and a second portion that is designed to have a second potential during the voltage contrast inspection. The first potential differs from the second potential. The selected one or more test layers which correspond to product layers are selected from the plurality of product layers such that defects found in the test layers of the test structure during the voltage contrast inspection represent a prediction of defects in the corresponding product structure.
Owner:KLA TENCOR TECH CORP

Device architecture and process for improved vertical memory arrays

An array process diagnosis test structure for an integrated circuit including a transistor array composed of vertical FET memory cell access transistors, which are formed into the depth of a substrate in the form of active webs which run parallel in the lateral direction of the circuit is disclosed. Memory cell storage capacitors in the array test structure are formed in deep trenches on the end faces of those sections of the active webs which form the vertical FET transistors. Word lines are arranged along the webs and along parallel intersecting bit lines of the array, outside of which, and on two mutually opposite edges, are located a first and second word line comb. The wordline combs are offset and connected alternately to different word lines. In addition, a first and a second bit line comb are formed on the two other opposing edges of the transistor array mutually offset and each connected to different bit lines. The test structure provides a convenient means to carry out reliability investigations on the gate oxide of the vertical FET transistors and on the capacitor dielectric in the deep trenches, capacitance measurements between the word lines, and between the word lines and other circuit layers, as well as capacitance measurements between the bit lines and between the bit lines and other circuit layers, and thus facilitates diagnosis of possible fault sources arising during the production process.
Owner:POLARIS INNOVATIONS

Voltage contrast test structure

A method for electrically testing a semiconductor wafer during integrated-circuit fabrication process, the method including: (i) providing a scanning charged-particle microscope (SCPM), having a defined scanning plane and operative, while in any one mechanical state, to scan a surface in the scanning plane within a two-dimensional scanning window, which has a given maximum size; (ii) providing in association with any layer of the wafer, it being a test layer, one or more test structures, each test structure including normally conductive areas within a normally non-conductive background in one or more layers, which include said test layer, the conductive areas formed as one or more patterns; the patterns in said test layer include one or more clusters of mutually isolated pads; each pad is conductively connected with a corresponding distinct point on the patterns and all the pads in any one cluster are sized and arranged so that at least a significant portion of each pad falls within a common window whose size does not exceed said maximum size of said scanning window; (iii) with said test layer forming the top surface of the wafer, placing the wafer on the SCPM and adjusting the mechanical state of the SCPM so that at least a significant portion of each pad in any one of said clusters is within said scanning window; (iv) causing the SCPM, while in said mechanical state, to scan all of the pads of said one cluster and thereby to provide information about the electrical state of the respective test structure.
Owner:APPL MATERIALS ISRAEL LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products