1077 results about "Test structure" patented technology

The invention relates to the technical field of pipe bracket testing, in particular to a thermal insulation pipe bracket overall strength displacement overload testing device and method.The thermal insulation pipe bracket overall strength displacement overload testing device comprises a bearing base and further comprises a pipe bracket base arranged on the upper side of the bearing base, a connecting pipe bracket is installed at the upper end of the pipe bracket base, a clamping plate is clamped to the upper side of the bearing base, and a rotating shaft is arranged on the clamping plate in a penetrating mode; the bottom end of the rotating shaft is clamped and connected with a connecting gear, and an annular groove is formed in the edge of the upper side of the bearing base. According to the invention, the axial and radial strength of the pipe bracket can be tested in the displacement overload test process, the use limitation is low, the automation degree is high, the test efficiency of the heat insulation pipe bracket is obviously improved, the situation that the pipe bracket is broken to injure people due to broken objects in the displacement overload test process of the pipe bracket can be avoided, and the test efficiency is improved. The displacement overload test structure has a good safety protection function, is high in use safety, and also realizes a step-by-step disassembly function of the displacement overload test structure, so that barrier-free maintenance of the test structure is facilitated.

The invention relates to the technical field of rock mass testing, in particular to a tunnel water-rich fault fracture zone area loading simulation test device and method.The tunnel water-rich fault fracture zone area loading simulation test device comprises a test box, and a partition plate is arranged in the test box; the partition plate divides the test box into a first area and a second area, and the second area is filled with a rock-soil sample; a lateral loading structure; a vertical loading structure; the simulated fault test structure comprises a mounting frame fixedly connected to the partition plate, a driving structure and a simulated fault unit, one end of the driving structure is hinged to the mounting frame, and the other end of the driving structure is connected with the simulated fault unit; the fault simulation unit is hinged to the mounting frame and used for simulating an adjustable fault, and the technical problems that an existing test device cannot dynamically adjust the fault fracture width and the dip angle according to the load effect and cannot perform real-time coupling simulation on a hydrological seepage field are solved.

The invention belongs to the technical field of performance testing, and particularly discloses an intelligent testing system and method for the impedance performance of an HDI circuit board, and the method comprises the steps: immediately starting an interlayer collection module after the lamination of each line layer, carrying out the electrical precise alignment through a POFV test structure, and collecting the in-situ impedance data; the diagnosis prediction module analyzes and processes the data, generates an impedance deviation parameter set, calculates an impedance performance standard coefficient fused with a layer influence factor, and analyzes and outputs a trend result through a time sequence; the impedance state judgment module carries out abnormity judgment based on a preset rule according to the standard coefficient and the trend result; when the judgment result is abnormal, an adjustment triggering marking module is started; and finally, a test report output module generates a test report containing the impedance performance score and the impedance performance distribution of the whole board. According to the invention, layer-by-layer, real-time and closed-loop intelligent test and regulation of impedance performance are realized, and product quality and production efficiency are effectively improved.

The invention relates to the technical field of semiconductor testing, in particular to a radio frequency testing bonding pad and a radio frequency testing structure. The radio frequency test pad comprises a substrate; the connection supporting layer is located on the substrate, and the connection supporting layer comprises a metal layer; the connection ports are located on the connection supporting layer, and the connection ports comprise a grounding port and a signal port; the grounding port is conductively connected through the metal layer; the signal port and the metal layer are not conductive. The signal port and the metal layer are arranged to be non-conductive, so that potential difference between the signal port and a structure below is avoided, parasitic capacitance is inhibited, and the accuracy of radio frequency testing is further improved.

The invention discloses a semiconductor test structure and a test method thereof, and belongs to the field of semiconductors. The test structure comprises at least two metal layers arranged on a substrate, the metal layers at least comprise a lower metal layer and an upper metal layer, the lower metal layer is arranged close to the substrate and at least comprises a test area, a test area, a contrast area and a reference area, the test area is arranged between the test area and the contrast area, and the reference area is arranged between the test area and the contrast area. The reference area is arranged on one side of the test area, the inspection area and the contrast area, and the upper metal layer is arranged on the test area, the contrast area and the reference area; the metal plug is arranged between the upper metal layer and the lower metal layer; the first bonding pad is arranged on the upper metal layer on the reference region; the second bonding pad is arranged on the upper metal layer on the test area; and a third pad disposed on the upper metal layer on the contrast region. According to the semiconductor test structure and the test method thereof provided by the invention, the position of an electric leakage defect in the semiconductor structure can be accurately positioned.

The invention discloses electronic detonator spot welding defect detection equipment which comprises a bottom bearing plate, a telescopic fixing structure is arranged at the upper end of the bottom bearing plate, a circulating feeding structure is arranged in the telescopic fixing structure, and a testing structure is arranged at the upper end of the telescopic fixing structure. The telescopic fixing structure comprises side supporting plates symmetrically and fixedly arranged on the top face of the bottom bearing plate. According to the electronic detonator spot welding defect detection equipment provided by the invention, the telescopic fixing structure is arranged, and two groups of transverse electric push rods which are symmetrically arranged drive clamping plates at the upper ends to get close to each other, so that electronic detonator control plates with different sizes on the surface of the top plate can be fixed; and meanwhile, a longitudinal electric push rod is matched to drive a test meter and a test needle head on the top to descend to be in contact with a welding spot on the surface of the control panel, so that whether the welding spot has pseudo soldering or not can be detected, compared with an existing detection device, the detection efficiency of the control panel can be effectively improved, and meanwhile higher adaptability is achieved for control panels of different sizes.

The embodiment of the invention provides a semiconductor test structure and a manufacturing method thereof, and the semiconductor test structure comprises a test array region which comprises test active regions arranged in an array. The plurality of test conductive wire groups are arranged along the first direction, each test conductive wire group comprises two test conductive wires which are adjacently arranged and a connecting part which is connected with the first ends of the two test conductive wires, each test conductive wire extends and penetrates through the test array area along a second direction, and the second direction is perpendicular to the first direction. And the at least one electric connection structure and the two external connection structures are located on the second ends of the test conductive wires in the plurality of test conductive wire groups, and the first ends and the second ends of the test conductive wires are opposite to each other. The at least one electric connection structure is electrically connected with the adjacent test conductive wires in the adjacent test conductive wire groups in the plurality of test conductive wire groups, and the two external connection structures are electrically connected with the two outermost test conductive wires in all the test conductive wires in the plurality of test conductive wire groups respectively.

The invention discloses a combined load synchronous application testing device. The technical problems that in the prior art, the load applying mode is single, and the combined load cannot be synchronously applied are solved. The device comprises a connecting mechanism and a load applying mechanism, wherein the load applying mechanism comprises a torsional load applying structure, a load transmitting structure and a multi-linkage testing structure. The load transmission structure comprises a special-shaped stress plate and a torsional load transmission assembly, and the torsional load transmission assembly comprises a connecting chuck and a torque plug-in. By controlling the rotation of the torsion load transmission assembly, a pure torsion load applying mode or a conversion mode of converting torsion motion into radial load can be selectively realized, and multi-directional load detection is realized. The invention further provides a combined load synchronous applying function, the single driving source synchronously activates the torsion load path and the radial load path by adjusting the geometric positions of the torque plug-in and the load adjusting plate on the connecting chuck, and synchronous applying of the torsion load and the radial load is achieved.

The invention provides a semiconductor device, a cutting method thereof and a semiconductor chip, relates to the technical field of semiconductor chips, and aims to solve the technical problem that the packaging yield of the semiconductor chip is low. The semiconductor device comprises a substrate, a plurality of semiconductor units and a plurality of test structures, wherein the plurality of semiconductor units and the plurality of test structures are located on one side of the substrate. The plurality of semiconductor units are distributed in an array, and at least part of the plurality of test structures is located between two adjacent semiconductor units. In the two adjacent semiconductor units and the test structure between the two adjacent semiconductor units, the distance between one semiconductor unit and the test structure is smaller than the distance between the other semiconductor unit and the test structure. The semiconductor chip obtained by cutting the semiconductor device is applied to a three-dimensional memory so as to realize data reading and writing operation.

The invention relates to the technical field of aero-engine tests, in particular to an aero-engine turbine blade cooling effect test optical test structure which comprises optical glass, an outer casing and an optical channel pipe. The optical glass is located on the light-in side of the optical channel pipe, and the light-out side of the optical channel pipe faces the target blade. The outer casing is arranged on the outer side of the optical channel pipe in a sleeving mode, and a cooling channel is formed between the inner wall of the outer casing and the outer wall of the optical channel pipe so as to cool the optical channel pipe; a gas film ring is connected between the optical glass base and the light inlet side of the optical channel pipe in a sealed mode and located on the light outlet side of the optical glass. The optical glass base is provided with the cooling gas inlet, and the gas film ring is provided with the gas jet hole, so that the cooling gas performs jet sweeping on the light emitting surface of the optical glass and enters the optical channel pipe to cool the optical channel pipe, thereby improving the accuracy of the cooling effect test result of the turbine blade.

The invention is suitable for the technical field of solar cells, and provides a back contact solar cell, a cell assembly and a photovoltaic system. The first fine grids and the second fine grids are arranged on the back surface of the silicon substrate; the at least one group of first bonding pads are arranged on the back surface of the silicon substrate, and the first bonding pads are electrically connected with the first fine grids; the at least one group of second bonding pads are arranged on the back surface of the silicon substrate and are electrically connected with the second fine grids; the first test structure comprises two third bonding pads which are arranged at intervals in the first direction, and the third bonding pads are electrically connected with the first fine grids; the third bonding pad and the first bonding pad are the same in size; the second testing structure comprises two fourth bonding pads which are adjacently arranged in the first direction, the fourth bonding pads are electrically connected with the second fine grids, and the fourth bonding pads and the second bonding pads are the same in size. According to the back contact solar cell provided by the invention, the carrier collection effect of the fine grid can be improved, and the printing cost of the back contact solar cell can be reduced.

The invention relates to the technical field of hydrogen energy conveying and material performance testing, in particular to a testing structure for hydrogen permeation testing in a high-pressure gas-phase hydrogen environment and an installation method and application of the testing structure. The testing structure comprises a sample body and an insulation sealing assembly, and the sample body is of a double-step disc structure; the uppermost edge of the first sealing insulation assembly is flush with the upper end face of the cylindrical platform, the sample body is installed on the inner side of the first sealing insulation assembly in a matched mode, the second sealing insulation assembly is in a shape with an upward opening, and the first sealing insulation assembly is installed in the second sealing insulation assembly in a matched mode. The test surface of the sample body of the test structure and the gas main flow keep a consistent flow velocity field, and when the test structure is used for testing, the permeation behavior of the hydrogen flow on the material surface can be truly reflected; all the clamping and conducting structures are arranged outside the pipe wall of the test pipeline or at the left part of the sample body, so that flow field disturbance is prevented from being introduced into a main airflow path.

The invention relates to a three-dimensional sensing, storing and computing integrated structure and a manufacturing method and a testing structure thereof, belongs to the technical field of semiconductors, and solves the problem that the existing three-dimensional integration method faces the shortage of resource allocation of a rewiring layer. The manufacturing method of the three-dimensional sensing, storing and computing integrated structure comprises the following steps: forming a fan-out packaged processor, a memory and an image sensor through a subsequent process; mounting the fan-out type packaged processor on a substrate in a surface mounting manner; bonding the memory to the upper part of the processor of the fan-out type package; and inverting the image sensor, bonding the image sensor above the memory, and routing the image sensor from the memory to the substrate. According to the manufacturing method of the three-dimensional sensing, storing and computing integrated structure, a manufacturing method of a three-dimensional testability design structure is provided, and joint testing among an image sensor, a memory and a processor is achieved.

The invention provides semiconductor device thermal resistance measuring equipment, which is applied to the technical field of electrical variable measurement and comprises a case, a workbench fixed at the top of the case, a constant-temperature base arranged in the middle of the workbench, a rack arranged on one side of the workbench and erected above the constant-temperature base, a thermal resistance detector matched with the rack, and a temperature sensor arranged on the thermal resistance detector. The top of the rack is provided with a pressing mechanism which can press and abut against the semiconductor device to be tested towards the upper end face of the constant-temperature base. The middle part of the upper end surface of the constant-temperature base is provided with a flexible heat-conducting contact pad used for self-adapting to the shape of a semiconductor device to be tested, and the flexible heat-conducting contact pad is internally provided with a temperature control assembly; and an environment simulation mechanism is matched on the pressing mechanism. The thermal resistance testing device has a high-adaptability and high-precision thermal resistance testing structure, can adapt to semiconductor devices in various shapes for testing, can simulate the actual application environment of the semiconductor devices, can provide reliable data support for thermal management design of the semiconductor devices, and is good in overall use effect.

The invention relates to an airflow sensor testing structure and a packaging method and packaging structure thereof, each chip unit of an airflow sensor wafer is composed of a substrate (1), a vibrating diaphragm (2) and a back plate which are stacked, the substrate (1) is provided with a back cavity (42) penetrating in the thickness direction of the substrate (1), a slot (10) is formed in the bottom of the substrate (1), and the vibrating diaphragm (2) is arranged in the slot (10). The open groove (10) penetrates through the substrate (1) and the back cavity (42), and the open groove (10) is used for establishing a continuous air flow path in a space outside the back cavity (42) and the air flow sensor. During packaging, the airflow sensor chip is fixed on the packaging substrate through silica gel, a packaging shell is installed outside the airflow sensor chip, the open groove (10) is filled with the silica gel, and blocking and sealing of the open groove (10) are achieved. According to the invention, the requirement of each tube core on the test wafer can be met, the production cost is not increased, and the risk of wafer fragmentation can be effectively avoided.

The invention discloses a selector unit for dynamic switching of a standard unit, a ring oscillator and a test structure. Wherein the selector unit is connected in parallel with standard units with different threshold voltages, driving capabilities and logic functions, and is matched with the first switch control circuit, so that flexible switching of the differentiated standard units is realized, and the static architecture limitation of a traditional test circuit is broken through; according to the ring oscillator, a selector unit is embedded into a closed oscillation loop of a standard unit chain, a time sequence path of multiple unit combinations is formed through dynamic configuration, and the delay superposition effect between mixing units in an actual circuit is effectively simulated; the test structure is based on the configurable characteristic of the ring oscillator, combines a pin sharing mechanism of the first control signal multiplexing module, realizes parallel test of multiple unit combinations in a single chip, and eliminates multi-chip separate test requirements, so that a high-efficiency and high-coverage standard unit delay detection system is realized under the constraint of hardware resources, and the test efficiency is improved. And a verification basis is provided for deviation analysis of the process simulation model.

The utility model relates to a test structure and a semiconductor structure. The test structure comprises a plurality of test units arranged in a two-dimensional array and at least one row of liner units, and each liner unit comprises a plurality of liners arranged at intervals; in the row direction of the two-dimensional array, the test units and the pads are alternately arranged, and at least two adjacent rows of test units share the same row of pad units; the test structure is arranged in a cutting channel of a wafer, and the line direction is parallel to the extending direction of the cutting channel. The semiconductor structure comprises an exposure area, a first cutting channel arranged around the exposure area, a second cutting channel arranged in a residual area around the exposure area and the test structure, the extension direction of the first cutting channel is parallel to a short axis direction, and the extension direction of the second cutting channel is parallel to a long axis direction. And the long axis direction and the short axis direction are respectively the length direction and the width direction of the exposure area. According to the invention, the effective usable area of the wafer is improved on the premise of ensuring the effectiveness of the acceptance test of the wafer.

The invention relates to the field of integrated circuit testing, provides an SRAM (Static Random Access Memory) fault testing structure, and particularly relates to an IEEE (Institute of Electrical and Electronic Engineers) 1687 standard and an SRAM self- According to the method, a common fault model of an SRAM (Static Random Access Memory) is analyzed, improvement is performed on the basis of a March C-algorithm, and a March C-pro algorithm capable of covering most common faults of the SRAM is derived; a modularized SRAM self-test structure is designed based on a March C-pro algorithm, so that the design cost caused by built-in self-test of a memory and possible additional interface requirements are avoided; a multi-layer network structure based on the IEEE 1687 standard is designed, access to an embedded instrument is achieved, an SRAM self-test module is connected, and an SRAM test in the SOC is achieved.

The invention belongs to the field of terminal equipment production, and particularly relates to test equipment and a terminal equipment production line. The testing equipment comprises a base, a first conveying line, a second conveying line, a testing structure and a material moving structure, the second conveying line and the first conveying line are arranged in a spaced mode, the testing structure is used for detecting materials, a feeding station and a first discharging station are arranged on the two opposite sides of the base in the first direction respectively, and the first conveying line receives the materials at the feeding station; the first conveying line is used for conveying materials to the testing structure and receiving the tested materials from the testing structure, the material moving structure is used for transferring the unqualified materials from the first conveying line to the second conveying line, the first conveying line discharges the qualified materials to a first discharging station, and the testing structure comprises a testing unit. The multiple testing units are arranged at intervals in the first direction, and all the testing units detect materials in sequence and are used for detecting different parameters of the materials respectively. According to the invention, the test efficiency and the test consistency can be improved.

The invention provides a launching mechanism and an inclined water entry impact test system. The launching mechanism comprises a launching device, a test structure body and a launching frame, the launching frame comprises an erecting frame, a baffle and a sliding frame, the baffle is arranged at one end of the erecting frame, an opening is formed in the other end of the erecting frame, the launching device is installed on the sliding frame, the sliding frame is arranged on the erecting frame in a sliding mode, and the test structure body is arranged on the sliding frame. The end, away from the launching port, of the launching device is connected with the baffle through a first energy absorber, one end of the sliding frame is connected with the erecting frame through a second energy absorber, and the other end of the sliding frame is connected with the erecting frame through a third energy absorber. The launching mechanism generates recoil resistance through the first energy absorber, the second energy absorber and the third energy absorber. Ejection power is provided for the test structural body through the multiple phase change pipes, high-speed water entry of the test structural body can be achieved, appropriate damping parameters are matched for different load test structural bodies, and recoil in the launching process is buffered and eliminated.

A method for non-contact modal analysis uses an optical sensing device such as a video camera. Unlike traditional modal analysis, requiring accelerometers or force sensors to measure the modal characteristics of a structure and animate the motion of a wireframe model of the test structure, the inventive system mathematically modifies the original video recordings by filtering, amplifying, and modifying the playback rate or applying modal shape mask or vectors to produce modified video to show motion at each modal frequency. This provides animated mode shapes with higher spatial and temporal resolution that possible with the traditional approach of using wireframe model animations.

The utility model relates to the field of PCB detection, in particular to a withstand voltage detection device for a PCB. Comprising a detection table, and a calibration plate of an L-shaped structure is arranged at one corner of a detection area; the annular outer edge of the detection area is also provided with a fastener; the fastening piece comprises a mounting plate, a fastening plate and a fastening rod; a testing structure is arranged on the back plate and comprises a rotating motor, a rotating shaft, a guide rod, a mounting seat and a testing needle; the rotating motor is mounted on the back plate through a bracket; an output shaft of the rotating motor is connected with the rotating shaft; the guide rod is arranged on the back plate and is parallel to the rotating shaft; the mounting seat penetrates through the rotating shaft and is in threaded connection with the rotating shaft; meanwhile, the mounting seat also penetrates through the guide rod, and the mounting seat and the guide rod are in sliding connection; the test needles are installed on the installation seat and used for carrying out electrified withstand voltage test operation on the aluminum substrate, and the distance between the two test needles is adjustable. The device is simple in operation, facilitates the fixation of the PCB, can be suitable for the withstand voltage detection of various PCBs with various specifications, and is more practical.

The invention relates to the technical field of semiconductor manufacturing, and discloses a laser chip oxidation aperture testing method which comprises the following steps: providing a laser wafer which comprises a plurality of testing structures with different oxidation aperture design values, each test structure comprises an oxidation aperture simulation chip and a monitoring test chip which have the same oxidation aperture design value; obtaining an oxidation aperture measurement value of the oxidation aperture simulation chip in each test structure and a monitoring voltage value for monitoring the test chip, and obtaining the oxidation aperture measurement value and the monitoring voltage value of the test structure; according to the oxidation aperture measurement values and the monitoring voltage values of the plurality of test structures, obtaining an oxidation aperture measurement value-monitoring voltage value relation curve; and acquiring a chip voltage value of the laser chip, and determining the oxidation aperture of the laser chip according to the oxidation aperture measurement value-monitoring voltage value relation curve. According to the invention, the oxidation aperture of each laser chip can be accurately tested, so that the oxidation aperture can be incorporated into the shipment judgment standard of each laser chip.

The present invention provides a thin plate residual stress testing device and a thin plate residual stress testing method. The thin plate residual stress testing device includes: a clamping support assembly, a cutting assembly, and a laser testing assembly. The clamping support assembly includes at least one clamping test structure, which includes a test bench, a first clamping portion, a second clamping portion, and a bottom support portion. The test bench has a test cavity inside, and the test bench also has a test inlet connected to the test cavity. At least a portion of the first clamping portion, the second clamping portion, and the bottom support portion are respectively disposed within the test cavity. The thin plate to be tested enters the test cavity from the test inlet along its length, and the bottom support portion is used to support the bottom of the thin plate to be tested. The cutting assembly is used to cut grooves of varying depths on the thin plate to be tested. The present invention solves the problems of low testing efficiency, complex structure, and high equipment cost in thin plate residual stress testing devices in the prior art, and can achieve fully automated testing.

The invention provides a test structure and a test method thereof, which are applied to the technical field of semiconductors. In the invention, a first tested element and a second tested element are arranged in a mutually separated manner along a first direction, each pad group comprises a first sub-pad and a second sub-pad which are arranged in a mutually separated manner, electric connecting wires comprise a first electric connecting wire and a second electric connecting wire, and the sizes of the first sub-pad and the second sub-pad are set to be the same. The resistance values of the first electric connecting wire and the second electric connecting wire are the same, so that when the same probe is used for testing the first tested element and the second tested element, the contact resistances between the first sub-bonding pad and the second sub-bonding pad which are the same in size and the probe are the same; the resistance values of the first electric connecting line and the second electric connecting line with the same resistance value can be offset during difference operation, so that the influence of the contact resistance and the resistance of the electric connecting lines in the transistor element on the measurement accuracy of the on-resistance of the transistor element is avoided, namely, the purpose of reducing the measurement error is achieved.

The application relates to the technical field of hydrogen energy transportation and material performance testing, and relates to a test structure for hydrogen permeation testing under a high-pressure gaseous hydrogen environment, a mounting method and application thereof. The test structure comprises a sample body and an insulating sealing assembly, and the sample body is in a double-stage disc structure. The uppermost edge of the first sealing insulating assembly is flush with the upper end surface of the cylindrical platform, and the sample body is matched with the inner side of the first sealing insulating assembly for installation. The second sealing insulating assembly is in an open-upward shape, and the first sealing insulating assembly is matched with the second sealing insulating assembly for installation. The test surface of the sample body of the test structure is kept consistent with the flow field of the gas main stream, and when the test structure is used for testing, the permeation behavior of the hydrogen flow to the material surface can be truly reflected. All clamping and conducting structures are arranged on the outer part of the pipe wall of the test pipeline or the left part of the sample body, so that flow field disturbance is avoided in the main path of the gas flow.

The invention discloses a reduced scale model pile body test structure which comprises a test box, a model pile and a laser scanner, a test soil body is laid in the test box, the model pile is vertically inserted into the test soil body, a reaction wall is installed on one side of the test box, a jack is installed on the reaction wall, and a thrust plate is installed at the front end of the jack; a target is installed on the model pile, and the laser scanner is located above one side of the target. According to the hollow nylon pipe model pile, it is guaranteed that lateral mechanical behaviors are similar, and the material cost and the machining difficulty are greatly reduced; the nylon pipe can also be used as an inclinometer pipe, so that the sensor is convenient to arrange; meanwhile, a grooving pipe inertia moment correction formula is introduced to accurately calculate the actual inertia moment of the grooved pipe, and similar errors are reduced; meanwhile, a strain gauge and a target are matched to comprehensively monitor the model pile from internal deformation, surface strain to top displacement; the surface of the model pile is roughened, so that the surface roughness of the model pile is equivalent to that of a concrete pile, slurry is injected into a pile-soil gap, and the simulation authenticity of the interface friction characteristic is improved.

The invention discloses a semiconductor device parameter testing method and structure, and belongs to the field of semiconductor testing. The testing method comprises the steps that a testing structure is provided, the testing structure comprises a two-dimensional electron gas channel and a multi-end testing pattern, testing branches are arranged at the positions, close to the two ends, in the two-dimensional electron gas channel, and the two ends of the two-dimensional electron gas channel and the testing branches are connected with the testing ends of the multi-end testing pattern in a one-to-one correspondence mode; respectively connecting the test ends connected with the two ends of the two-dimensional electron gas channel with a bias voltage and the ground, and measuring the channel current and the voltage of the test ends connected with the test branches; and calculating one or more of the source end contact resistance, the drain end contact resistance, the channel square resistance and the current surface density of the two-dimensional electron gas channel according to the size parameters of the two-dimensional electron gas channel and the measured voltage and channel current. The method is more accurate in test result, richer in data dimension and high in test flexibility.

The utility model provides an electrical property test structure for measuring overlay precision of a metal layer and a through hole. The electrical property test structure comprises a first test structure and a second test structure, each of the first test structure and the second test structure comprises a first metal layer, a second metal layer, a through hole and a test bonding pad; the second metal layer / first metal layer in the first test structure / second test structure is comb-shaped and comprises a plurality of second metal comb teeth / first metal comb teeth; a plurality of through holes are formed in the second metal comb teeth / the first metal comb teeth at intervals; the first metal layer / the second metal layer at least comprises a plurality of first metal strips / second metal strips which are arranged at intervals, and the through holes are formed between the adjacent first metal strips / second metal strips; and the distance between at least two through holes at different positions in the second metal comb teeth and the first metal strip / second metal strip close to the first metal strip / second metal strip is set according to a preset rule. According to the scheme, the problem of how to accurately and comprehensively measure alignment deviation of the through hole, the upper-layer metal wire and the lower-layer metal wire is solved.

The invention discloses a channel mobility testing method and a channel mobility testing structure. The test method comprises the following steps: providing the semiconductor devices, and determining the resistance between the source electrode and the drain electrode of each semiconductor device by applying test voltage to the source electrodes, the drain electrodes and the grid electrodes of at least two semiconductor devices; wherein the test voltages applied to the source electrodes of different semiconductor devices are the same, the test voltages applied to the drain electrodes of different semiconductor devices are the same, and the test voltages applied to the grid electrodes of at least two different semiconductor devices are different; measuring the resistance between the source electrode and the drain electrode of each semiconductor device; and determining the channel mobility of the semiconductor device according to the resistance between the source electrode and the drain electrode of each semiconductor device and the test voltage applied to the grid electrode of each semiconductor device. According to the invention, the measurement of the channel field effect mobility is realized, the measurement mode is simple, and the measurement efficiency is high.