130 results about "Test structure" patented technology

The application relates to a high-precision addressable ring oscillator test chip, method, device and medium, which comprises an addressing module, an output module and a plurality of ring oscillator test modules; the ring oscillator test module comprises a signal transmission module, a multifunctional test module and a plurality of ring oscillator test structures; the addressing module is used for selecting a ring oscillator test structure from the ring oscillator test structures of the plurality of ring oscillator test modules to perform a communication test; the multifunctional test module can switch the voltage compensation mode or the small-current test mode of the ring oscillator test structure based on a received control signal; when the characteristic parameters of the ring oscillator are measured, the voltage compensation mode can utilize voltage drop compensation to reduce the influence of the resistance voltage drop introduced in the test path, effectively improving the measurement precision, and the small-current test mode can effectively measure the static power supply current of the ring oscillator.

A semiconductor structure includes a back-end-of-line region including a first level of metal interconnects and a second level of metal interconnects separated by at least one interlayer dielectric layer, and a laser debonding test structure disposed in the back-end-of-line region. The laser debonding test structure includes a testable metal plate layer disposed within the at least one interlayer dielectric layer between the first level of metal interconnects and the second level of metal interconnects, a set of test pads, and a set of vias, at least a subset of the set of vias extending from at least one test pad in the set of test pads to the testable metal plate layer disposed within the at least one interlayer dielectric layer between the first level of metal interconnects and the second level of metal interconnects.

The application provides a simple gate oxide integrity testing device, which comprises a test sample and a test structure; the test sample comprises a substrate, a dielectric layer (gate oxide layer) on the substrate, a gate replacement layer used for replacing a gate layer or being located above the gate layer, so that the test sample forms a three-layer structure comprising the substrate-dielectric layer-gate replacement layer, and the gate oxide integrity of the dielectric layer is tested by combining a thermal desorption technology; the test structure is used for accommodating the test sample, providing a test temperature, and recording released elements; the application also provides a simple gate oxide integrity testing method, which has the technical effects of low cost, simple operation, and rapid feedback of test results, and does not need to prepare a transistor device, adopts the gate replacement layer arranged on the substrate-dielectric layer (gate oxide layer) to combine the thermal desorption technology, and directly tests the stacked layer material contained in a MOS stacked layer structure.

A test structure and test method are disclosed. The test structure includes: a substrate; a first electrode located on the substrate, the first electrode serving as a first test terminal or electrically connected to a first test terminal; a second electrode located on the substrate to the side of the first electrode, the second electrode serving as a second test terminal or electrically connected to a second test terminal; and a first dielectric layer located between the first electrode and the second electrode. The test structure of this invention can be used to obtain the values ​​of electrical parameters between the first test terminal and the second test terminal, thereby obtaining the quality status of the first dielectric layer based on the values ​​of these electrical parameters. This facilitates quality monitoring of the first dielectric layer between the first electrode and the second electrode, and correspondingly, it also helps to obtain the quality status of the semiconductor structure, thereby facilitating improvements to the semiconductor manufacturing process.

The application provides a test rack for semiconductor package testing, which comprises a test base, a placement plate arranged on the top of the test base, a plurality of test slots for placing semiconductor to be tested arranged on the top of the placement plate, and a plurality of first ventilation slots arranged on one side of the placement plate; a test structure is arranged on the top of the test base, and the test structure comprises a detection device and a detection needle for detecting the semiconductor to be tested; a plurality of test benches are arranged in the plurality of test slots respectively, and each test bench comprises a bearing seat, a cooling base arranged at the bottom of the bearing seat, an adsorption air duct formed between the bearing seat and the cooling base, a plurality of adsorption holes arranged on the top of the bearing seat, and a plurality of bearing columns arranged in the plurality of adsorption holes and located at adsorption positions or ejection positions, so that negative pressure adsorption and bottom heat dissipation are realized; test boxes with cooling air ducts are arranged on both sides of the cooling base, and the test boxes are internally provided with slidable semiconductor test pins; during testing, the semiconductor test pins are pressed down to enter the cooling air ducts to realize heat dissipation of contact parts, and the test stability is improved.

A test structure and a test method, the structure comprising: a substrate, the substrate comprising a chip area and a sealing area surrounding the chip area; a dielectric layer located above the substrate; one or more to-be-tested interconnection layer structures located in the dielectric layer above the substrate of the sealing area and exposing the chip area, the to-be-tested interconnection layer structure comprising one or more to-be-tested interconnection layers arranged in a longitudinal stack, the to-be-tested interconnection layer comprising a first metal layer and a second metal layer located above the first metal layer, and an interconnection via located between the first metal layer and the second metal layer, and the first metal layer and the second metal layer are electrically connected with the interconnection via. The number of interconnection vias at the wafer level is monitored, the number of tested interconnection vias is greatly increased, and the reliability of the test structure is improved.

The application provides a semiconductor test structure and a breakpoint failure positioning method. The semiconductor test structure comprises a first metal layer, a plurality of first sub-metal blocks arranged in a matrix along an X direction and a Y direction; a second metal layer, a plurality of second sub-metal blocks arranged in the X direction and the Y direction and arranged above the first sub-metal blocks in a staggered manner, the first sub-metal block and the second sub-metal block adjacent to the first sub-metal block in the staggered manner are connected in a head-to-tail manner through a conductive via to form a plurality of interconnected parallel and head-to-tail chain structures; and a dummy metal filling layer, a plurality of identification marks located at the periphery of the chain structure. Obviously, the semiconductor test structure provided by the application is that a plurality of identification marks are newly formed in the X direction and the Y direction in the dummy metal filling layer formed at the periphery of at least two asymmetric sides of the existing test structure for breakpoint failure analysis through filling or etching.

The present application provides a continuous scanning laser Doppler vibration test method for the outer surface of a thin-walled casing. Firstly, the continuous scanning vibration test is performed on the outer surface of the thin-walled casing, and the vibration time-domain signals of the outer surface of the thin-walled casing are collected. Then, the vibration displacement amplitude of the outer surface of the thin-walled casing is obtained by processing the tested time-domain signals through a band-pass filter and a Hilbert transform. Next, the laser continuous scanning path point coordinate model of the variable cross-section outer surface of the thin-walled casing is established, and the laser continuous scanning path point coordinates of the outer surface of the thin-walled casing at the missing hole are deleted by comparing with the coordinate model of the UG of the thin-walled casing. The vibration displacement amplitude based on the laser continuous scanning path point coordinates is obtained. The continuous scanning modal shape of the planar expansion of the outer surface of the thin-walled casing is obtained. Finally, the three-dimensional continuous scanning modal shape of the outer surface of the thin-walled casing is obtained through a coordinate conversion formula. Compared with the traditional test method for the outer surface of a thin-walled cylinder, the test efficiency is greatly improved, and the range of the test structure is expanded.

A test structure and a test method, the test structure comprising: a metal plate; a to-be-tested interconnection via electrically connected with the metal plate; a first interconnection via located at a side of the to-be-tested interconnection via and electrically connected with the metal plate; a first current signal loading end electrically connected with a top of the to-be-tested interconnection via; a first voltage signal loading end electrically connected with the top of the to-be-tested interconnection via and separated from the first current signal loading end; a second current signal loading end electrically connected with the first interconnection via; and a second voltage signal loading end electrically connected with the first interconnection via and separated from the second current signal loading end. The precision of obtaining the resistance value of the to-be-tested interconnection via to the metal plate is improved.

The application discloses a method for quickly testing a plurality of FPGA implementation decoders, comprising: a host computer generates a data packet and sends, receives a decoding result of a lower computer, processes a block error rate and a bit error rate; the lower computer uses a state machine to control the whole test system; a read-write control block controls writing of to-be-decoded data into two RAMs and reading of a decoding result into a FIFO; a decoding control block controls starting, reading, ending and resetting of the decoder. The method follows the idea that when one RAM is storing data, the decoder reads data in the other RAM, and compared with a test structure following the idea of series connection of generating data, sending, decoding and receiving processing, the running time can be shortened.

This invention discloses a test structure that facilitates TEM sample preparation, comprising: a front metal layer including a front target metal line extending along a first direction; and a rear metal layer formed above the front metal layer, including two left pseudo-rear metal lines and two right pseudo-rear metal lines extending along a second direction, and a rear target metal line. The two left pseudo-rear metal lines are located to the left of the rear target metal line, with the first left pseudo-rear metal line located between the rear target metal line and the second left pseudo-rear metal line. The two right pseudo-rear metal lines are located to the right of the rear target metal line, with the first right pseudo-rear metal line located between the rear target metal line and the second right pseudo-rear metal line. This invention breaks the second left and right pseudo-rear metal lines above the front target metal line by a pattern spacing dimension, which reduces the difficulty of TEM sample preparation and assists in precise positioning during TEM sample preparation, thereby improving the success rate, analysis efficiency, and analysis cost of TEM sample preparation.

The utility model discloses a kind of axial flow type regulating valve sealing test structures, belong to sealing test technical field, its technical scheme main points include water tank and regulating valve body, the surface of the water tank is fixedly connected with portal frame, the inside of the portal frame is provided with adjusting assembly, the adjusting assembly includes lifting plate, the bottom of the lifting plate is provided with auxiliary test assembly, by setting auxiliary test assembly, closed plate can be automatically clamped regulating valve body both ends under the drive of adjusting assembly, right side closed plate is connected with air compressor through gas pipe, compressed air can be filled into valve cavity quickly, without manual connection gas source and seal, greatly improve test efficiency, while reducing the failure rate and labor intensity of manual operation, by setting adjusting assembly, adjusting assembly can quickly, accurately adjust the spacing between two closed plates, so that the regulating valve body of different specifications can be adapted, test efficiency is significantly improved, and then improve versatility.

The application provides an internal short circuit boundary testing assembly of an electric core, a testing device and a testing method thereof, and belongs to the field of battery fault detection. The internal short circuit boundary testing assembly of the electric core comprises a positive electrode to-be-tested structure, a negative electrode to-be-tested structure, a first diaphragm and a second diaphragm. The first diaphragm is located between the positive electrode to-be-tested structure and the negative electrode to-be-tested structure, and the first diaphragm is provided with a through hole corresponding to the positive electrode to-be-tested structure and the negative electrode to-be-tested structure. The second diaphragm covers the through hole. Through the internal short circuit boundary testing assembly of the electric core, a relatively accurate internal short circuit boundary of the electric core can be obtained, so that the advantages and disadvantages of the safety of the electric core can be judged more accurately.

The present application relates to the technical field of semiconductor, and particularly relates to an electromigration test structure, including 13 structures of I-V lead hole through layer type, single-side lead voltage test pad and current source hole through layer type, cross layer type for double-side lead voltage test pad. The I-V lead hole through layer type is a structure, which comprises four structural elements, namely, a metallization test line, other metal interconnection lines, a hole interconnection structure and a large-area metallization test pad. The structure comprises two metal layers, wherein the metallization test line is located on the first layer, and the current source, the voltage lead and the other metal interconnection lines are connected to the second layer through the hole interconnection, forming a cross layer structure. The present application provides an electromigration test structure for evaluating the electromigration reliability problem caused in the semiconductor device manufacturing process.

The present disclosure provides a memory integrated circuit and a manufacturing method thereof. The memory integrated circuit includes a plurality of memory arrays located in a plurality of chip regions of a semiconductor chip and a plurality of test structures located in a scribe lane region of the semiconductor chip. The plurality of memory arrays and the plurality of test structures each include a plurality of word lines and a plurality of insulating structures extending in a same direction. The plurality of insulating structures in each memory array are configured to define a plurality of capacitor contact structures. The plurality of insulating structures in each memory array are arranged at a first pitch, and the plurality of insulating structures in each test structure are arranged at a second pitch greater than the first pitch.

The utility model discloses a kind of mobile phone camera sealing test structure, specifically related to mobile phone camera production detection technical field, including test frame, the top of test frame is fixedly arranged with fixed seat, the top of test frame is fixedly arranged with support frame, the inside of test frame is provided with positioning mechanism, positioning mechanism includes multiple first electric telescopic link fixedly arranged in the inside of test frame, the output of first electric telescopic link is fixedly arranged with movable plate, the surface of test frame is provided with multiple guide slots, the surface of movable plate is provided with sliding slot, T-shaped internal thread block is slidably arranged in the inside of sliding slot, one side of movable plate is fixedly installed with small stepper motor, the output of small stepper motor is fixedly arranged with screw rod. The utility model is fixed accurately to mobile phone camera by the positioning mechanism of multidirectional adjustment, adapt to different specifications products, and ensure the air tightness of test environment, improve detection result accuracy.

The application discloses a test structure and a test method, and belongs to the technical field of semiconductors. The test structure is used for testing a process margin limit of a conductive layer, and the process margin limit of the conductive layer includes: a maximum number of conductive lines that can be arranged by the conductive layer, a maximum line width and / or a maximum spacing between adjacent conductive lines; the test structure includes a plurality of test units, and each test unit includes: a conductive layer including at least one conductive line, the conductive line extending along a first direction; a voltage test port structure and a current test port structure, which are arranged at the same side of the thickness direction of the conductive layer along the first direction and are electrically connected with a target conductive line in the at least one conductive line, respectively; and wherein the number of conductive lines, the line width and / or the spacing between adjacent conductive lines in the plurality of test units are different. The application can detect the process margin limit of the conductive layer, has high detection efficiency and low detection cost.

The utility model relates to PCB board test technical field, concretely relates to a kind of PCB board function test device, including bottom plate, still including test mechanism, test mechanism is located above bottom plate, test mechanism includes feeding structure, test structure, feeding structure includes the carousel rotation setting in bottom plate upper end, three moving grooves are set in carousel, moving groove inside is equipped with top plate, circuit board is placed in top plate upper side, and top plate is equipped with the clamping structure for clamping fixed circuit board in the side away from carousel center. Advantageous effect: through clamping structure clamping fixed circuit board, then using test structure to test the function of circuit board, after testing, drive carousel clockwise rotation, make circuit board rotate to carousel's unloading position, and then drive top plate to move upwards and lift circuit board upwards, make circuit board upper end higher than moving groove top end, and then facilitate to take circuit board, avoid to cause damage to circuit board, reduce the time of taking, improve the efficiency of test.

The application provides a test structure and a test method of a parasitic capacitance. The test structure comprises a first test structure, a second test structure and a third test structure. The first test structure, the second test structure and the third test structure each comprise a gate structure on a substrate, a source-drain structure in the substrate and a contact hole structure. The gate structure is electrically connected to a first test pad and forms a first parasitic capacitance with the substrate. The source-drain structure forms a second parasitic capacitance with the gate structure. The contact hole structure is electrically connected to a second test pad and forms a third parasitic capacitance with the gate structure. The first test structure is used for testing the sum of the first parasitic capacitance and the second parasitic capacitance. The second test structure is used for testing the second parasitic capacitance. The third test structure is used for testing the second parasitic capacitance. The test structure and the test method of the technical solution of the application can test a single parasitic capacitance.

The application provides an electromigration test assembly and a manufacturing method and an electromigration reliability test method thereof, and relates to the technical field of semiconductors, and is used for solving the problem of low measurement accuracy. The electromigration test assembly comprises a packaging body, a structure to be tested, two first connecting lines and two second connecting lines. The packaging body is provided with at least four connecting pieces which are spaced apart, and the at least four connecting pieces comprise two first connecting pieces and two second connecting pieces, the two first connecting pieces are used for measuring a test current, and the two second connecting pieces are used for obtaining a test voltage. The structure to be tested is arranged on the surface of the packaging body and is provided with at least two pads which are spaced apart from each other, wherein the two pads are two lead-out ends. The two first connecting lines are connected to the two lead-out ends and the two first connecting pieces respectively, and the two second connecting lines are connected to the two first connecting pieces and the two second connecting pieces respectively. The electromigration test assembly separates the voltage end and the current end, thereby improving the accuracy and stability of measurement.

The application discloses a wafer-level system test structure, which controls TAPs of dies in a wafer through a TAP controller to form a two-dimensional test network, wherein each die comprises a first, a second and a third test access port (TAP). The first TAP is communicatively connected with the third TAP in the upper-level die in the Y direction to form a Y-direction test chain, the second TAP is communicatively connected with the third TAP in the lower-level die in the X direction to form an X-direction test chain, and the third TAP can be configured to be communicatively connected with the first TAP in the Y direction or the second TAP in the X direction according to requirements, thereby forming a complete test chain. The two-dimensional grid deployment enables effective functional test of the dies themselves when production defects occur in the test structure itself, thereby improving yield. In addition, the Y-direction or X-direction test chain can be flexibly selected according to test targets, thereby improving test efficiency and reducing test cost.

The application relates to a semiconductor testing structure and a semiconductor testing method. The semiconductor testing structure comprises a testing gate, a plurality of contact structures, a first testing lead-out structure and a second testing lead-out structure. The plurality of contact structures are arranged as columns along a first direction parallel to a substrate; the contact structures and the testing gate have a first interval in a second direction parallel to the substrate; the second direction intersects the first direction; one end of the testing gate is electrically connected to the first testing lead-out structure; and the second testing lead-out structure extends along the first direction and is electrically connected to the same column of contact structures. The application can effectively monitor dielectric breakdown and is conducive to device miniaturization.

The utility model provides a kind of test structure for monitoring gate metal connection layer open circuit, including at least one test unit, wherein, the test unit includes the metal connection line of several gates and several active regions that are arranged in turn, and at least one gate metal connection line across adjacent the gate and the active region metal connection line;Along predetermined extension direction, adjacent the gate, the active region metal connection line is formed in order by the gate metal connection line ladder series connection one snakelike test chain between, and the both ends of the snakelike test chain are respectively connected by the gate metal connection line of head and tail end. By the utility model, the connection stability of gate metal connection layer M0GT can be effectively monitored.

The application discloses a test structure for drain end interference reliability of a storage unit and a test method thereof. The test structure is arranged in a cutting path of a wafer on which a storage chip is arranged. The test structure comprises at least two back-to-back storage units, i.e., a cycle storage unit and an interference storage unit. The cycle storage unit and the interference storage unit are each provided with a control gate, a floating gate, a tunneling dielectric layer and a blocking dielectric layer. The blocking dielectric layer is arranged between the control gate and the floating gate, the floating gate is arranged between the tunneling dielectric layer and the blocking dielectric layer, and the tunneling dielectric layer is arranged on the surface of a wafer substrate. The two drain ends of the cycle storage unit and the interference storage unit share one drain lead-out end. The source end / gate of the cycle storage unit and the source end / gate of the interference storage unit are respectively led out. During the test, the source end of the cycle storage unit is grounded, and the source end of the interference storage unit is applied with a test voltage. The application realizes efficient and accurate evaluation of the drain end interference problem of the NorFlash.

A test structure and a method for forming the same, wherein the structure comprises: a plurality of first electrode layers on a second region, the plurality of first electrode layers are electrically connected with a first lead, each first electrode layer comprises a plurality of first metal lines and a plurality of second metal lines connected with each other, the first metal lines are parallel to a first direction, the second metal lines are parallel to a second direction, and one second metal line is connected with one first metal line at both ends; and a plurality of second electrode layers on the second region, the plurality of second electrode layers and the plurality of first electrode layers are separated from each other, each second electrode layer comprises a plurality of third metal lines and a plurality of fourth metal lines connected with each other, the third metal lines are parallel to the first direction, the fourth metal lines are parallel to the second direction, and one fourth metal line is connected with one third metal line at both ends, so that the time-dependent breakdown performance of the dielectric layer in the first direction and the second direction can be monitored simultaneously.

This invention provides a rocket jet test structure, including a support rod, a connector, a projectile body, a balance, a high-pressure pipe, a tail section, a gas chamber, a nozzle I, a nozzle II, a nozzle seat, and a support rod. One end of the support rod is connected to an external gas source pipeline, and the other end is connected to the balance, the support rod, and the high-pressure pipe, introducing the external gas source into the high-pressure pipe. The connector is sleeved on the outside of the support rod, with both ends fixedly connected to an external wind tunnel test mechanism and the support rod, respectively. The projectile body, tail section, and nozzle seat simulate the shape of a rocket shell. One end of the projectile body mates with the conical surface of the balance, and the other end is connected to the tail section. The other end of the tail section is sealed by the nozzle seat, on which a nozzle II that does not participate in the jet is installed. The high-pressure pipe, the gas chamber, and the support rod are located within the cavity formed by the projectile body, tail section, and nozzle seat. The high-pressure pipe is connected to the gas chamber, and the support rod is fixedly connected to the gas chamber. The nozzle I that participates in the jet is fixed at the end of the gas chamber. The support rod, the high-pressure pipe, the gas chamber, and the nozzle I form a complete gas path. The gas introduced from the support rod flows through the pipeline and is ejected from the nozzle I.

The application belongs to the technical field of semiconductor device modeling and EDA, and discloses a method for extracting parameters of a compact model of an anti-radiation SiGe HBT based on a physical mechanism. The method prepares a test structure array containing different geometric sizes and doping, obtains direct current / alternating current characteristics through multi-dose point irradiation of a 60Co gamma ray, establishes a logarithmic-linear or saturation exponential degradation equation based on an irradiation damage mechanism, embeds a standard MEXTRAM / HICUM model in the form of a Verilog-A subcircuit, adds a dose input pin, extracts degradation coefficients to construct a total dose-key parameter degradation mapping library, and integrates the library with an EDA tool to realize irradiation environment simulation. The application shortens the anti-radiation circuit design cycle from 6 months to 2 weeks, and the model-measured error is less than 5% after 1 Mrad irradiation, so the application is suitable for the design of anti-radiation integrated circuits such as spaceborne phased arrays and space communication.

Embodiments of the present application provide a semiconductor test structure and a manufacturing method thereof. The manufacturing method comprises: providing a substrate; the substrate comprises a first region and a second region; the first region and the second region have a first overlapping region; on the substrate, a first test structure located in the first overlapping region is formed; the first test structure comprises a first conductive line, a second conductive line and a first conductive channel connecting the first conductive line and the second conductive line; the first conductive line and the second conductive line are formed in a photomask bonding manner and comprise a first part and a second part partially overlapping with the first part; the first test structure is subjected to continuity detection and / or disconnection detection to obtain a detection result; the detection result indicates that a lithography deviation and a bonding deviation belong to a preset deviation range.

The application provides a test structure and a test method of a semiconductor device, and relates to the technical field of semiconductors. The application constructs a via test structure for testing a target via in a semiconductor structure in a scribe groove of the semiconductor device. In the via test structure, a to-be-tested via and the target via are formed by the same process, so that the to-be-tested via can reflect the process parameters of the target via. In the via test structure, the application utilizes the feature that the target via is exposed relative to the dielectric layer when penetrating the dielectric layer, constructs two capacitors on the two sides of the exposed end of the to-be-tested via relative to the dielectric layer, and thus the distance between the to-be-tested via and the capacitors can be reflected by measuring the capacitance value of the capacitors and the to-be-tested via, so as to quantitatively determine the offset of the to-be-tested via. In addition, the via test structure can form a hierarchical structure to measure the offset of the via between different levels in the semiconductor device.

The application provides a via resistance test structure and a method for testing via resistance. The test structure comprises N vias, N+1 layers of metal lines connected by the vias between adjacent two layers of the metal lines, and N+3 test pads, wherein two test pads are respectively connected to the first ends of two layers of the metal lines in the length direction, and the rest of the test pads are respectively connected to the second ends of the metal lines in the length direction, or the first ends of the metal lines in the width direction, or the second ends of the metal lines in the width direction. N is an integer greater than or equal to 2. The N+3 test pads are used to measure the resistance of the N vias, thereby saving the number of test pads, further saving the wafer area and reducing the cost.