115 results about "Output compare" patented technology

A calibration circuit includes a replica transconductance stage that is a replica of a transconductance amplifier in a serializer / deserializer (SerDes) interface and a replica transimpedance stage that is a replica of a transimpedance amplifier in the SerDes interface. The replica transimpedance stage has an input coupled to its output. A comparison circuit is configured to generate a difference signal representative of a difference between voltage levels of an input signal received at an input of the replica transconductance stage and an output signal representative of voltage level at the output of the replica transimpedance stage. Replica feedback resistors are configured to couple an output of the replica transimpedance stage to the input of the replica transconductance stage. The difference signal can be used to select resistance values provided by the replica feedback resistors and by corresponding gain control resistors in the transimpedance amplifier in the SerDes interface.

The invention discloses a single-pin trimming circuit, which relates to the technical field of analog circuit design and comprises a comparator module, a first input end of the comparator module is connected to a single pin, a second input end of the comparator module is connected to a reference voltage, and the comparator module is used for comparing an input voltage of the single pin with the reference voltage and outputting a comparison signal; the input end of the time sequence decoding module is connected to the output end of the comparator module, and the time sequence decoding module is configured as follows: a, the logic state of a trimming position is judged according to the duration time of the pulse in the comparison signal; and b, addressing different trimming positions according to the number of pulses in the comparison signal, and further generating a multi-position trimming control signal through a series of pulse signals input by the single pin. Accurate control of a multi-bit fuse trimming circuit in a chip is realized by using single-pin resources.

The invention discloses a three-dimensional stacked chip and a test method. The three-dimensional stacked chip comprises at least two wafers to be tested; the at least two to-be-tested wafers comprise a first to-be-tested wafer and a second to-be-tested wafer, and the first to-be-tested wafer and the second to-be-tested wafer are stacked and connected through a connecting layer; the first to-be-tested wafer is provided with a first test circuit, and the second to-be-tested wafer is provided with a second test circuit and a comparison circuit. The first test circuit is used for writing test data into the first wafer to be tested; the second test circuit is used for copying the test data to the second wafer to be tested through the connecting layer; and the comparison circuit is used for comparing the copied test data with to-be-compared data in the second to-be-tested wafer and outputting comparison information for judging whether the connection layer is abnormal or not. The test of the connection layer can be realized, and the test coverage rate and the simultaneous test number are improved.

The present application relates to the technical field of power supply for boards. Provided are a power supply system, a computing board and a server. The system comprises: a USB-C connector, which is used for acquiring a power supply signal from a PD power adapter; a first transmission circuit, which is used for routing the power supply signal to a power supply input end of a computing board when the first transmission circuit is gated on; a second transmission circuit, which is used for performing power conversion on the power supply signal when the second transmission circuit is gated on and then routing the power supply signal to the power supply input end of the computing board; a power testing circuit, which is used for comparing the power of the power supply signal with a preset power and outputting the comparison result; and a driving circuit, which is used for separately generating, on the basis of the comparison result outputted by the power testing circuit, a driving signal for a first gating end and a second gating end, so as to gate on the first transmission circuit or the second transmission circuit. The solution of the present application has good universality and is applicable to computing boards having a relatively large power change range, and can effectively avoid the occurrence of power loss phenomena, and thus greatly improves the power supply stability and reliability for the boards.

The utility model relates to the technical field of cold isostatic pressing equipment, in particular to a cold isostatic pressing equipment control system based on a programmable logic controller (PLC), which comprises the PLC. The PLC controller comprises a PID control module, an analog quantity module and a digital quantity module. A digital quantity module is arranged, and a control signal is generated according to an input switching value signal to drive a control valve set to operate cold isostatic pressing equipment connection; a PID (Proportion Integration Differentiation) control module is arranged to generate a comparison signal according to a set pressure signal and a pressure signal acquired from a pressure sensor; an analog quantity module is arranged and used for outputting a comparison signal to a booster station main pump set, the opening and closing degree of a proportional valve of the booster station main pump set is adjusted, and pressure increasing and releasing operation of an auxiliary machine and a main machine of cold isostatic pressing equipment execution equipment is completed.

The application provides a comparator and a decision feedback equalization circuit, comprising a first input circuit, which is used for generating a first differential signal according to an input signal and a first reference signal under the control of a control signal; a first positive feedback circuit, which is used for accelerating the difference between the first differential signal; a second input circuit, which is used for generating a second differential signal according to the input signal and a second reference signal under the control of the control signal; wherein the first reference signal is greater than the second reference signal; a second positive feedback circuit, which is used for accelerating the difference between the second differential signal; and an output circuit, which is connected with the output end of the first input circuit and is used for amplifying and latching the voltage signal of the output end of the first input circuit or the voltage signal of the output end of the second input circuit in a regeneration stage to output a comparison result. The response rate of the comparator in the application is high, the power consumption is small, the working voltage is low and the inter-symbol interference can be eliminated.

The robot controller includes a communicator, a storage, and a processor. An input signal is input to the communicator. The storage stores the control software. The processor creates the command signal including the command value for operating the robot based on the input signal and the control software. The processor reads out the past input signal and the past command signal from the storage or from external source. After updating the control software, the processor creates a confirmation command signal based on the past input signal and the control software. The processor compares the past command signal with the confirmation command signal and outputs the comparison result.

The invention belongs to the technical field of integrated circuits, and particularly relates to a burning circuit with a configurable port mapping function and a burning method thereof. Comprising a mapen signal generating circuit which is used for detecting and counting rising edges of clock signals CLKPmap input by a clock mapping IO port, when a counting value reaches a preset fixed threshold value, data signals DATAPmap input by a data mapping IO port serve as to-be-matched data, the to-be-matched data are compared with reference data bit by bit, and when the counting value reaches the preset fixed threshold value, the to-be-matched data are obtained; a comparison result signal mapen is output to enable the port configuration circuit; the port configuration circuit is used for selecting a mapping pair port or a default pair port as a burning port under the enabling of the comparison result signal mapen; according to the method, the default port and the mapping port are selected, so that the layout flexibility of the PCB is improved, the wiring complexity is reduced, and meanwhile, the adaptability of a packaging form is improved.

Provided are a malicious attack protection circuit, a system-on-chip including the same, and an operating method thereof. The malicious attack protection circuit includes a reference interrupt generator to output a reference interrupt signal every reference interrupt period, a variable clock manager for outputting an operating clock signal to a logic circuit outside the malicious attack protection circuit and a variable clock signal having a variable period, a variable interrupt generator to output an interrupt signal every variable interrupt period based on the variable clock signal, a comparison circuit to compare the reference interrupt signal with the interrupt signal and output a comparison result signal, and a controller that interrupts the output of the operating clock signal input to the logic circuit, according to the comparison result signal.

The application discloses a reconfigurable strong PUF circuit and method with strong nonlinear response, an STT-MRAM storage unit array is used for storing data information "0" or "1", an odd array access transistor is used for accessing the STT-MRAM storage unit of an odd bit, and an even array access transistor is used for accessing the STT-MRAM storage unit of an even bit; an odd array excitation selection transistor is used for controlling the write signal of the STT-MRAM storage unit of the odd bit, and an even array excitation selection transistor is used for controlling the write signal of the STT-MRAM storage unit of the even bit; an array selection circuit ASC selects an odd row STT-MRAM storage unit and an even row STT-MRAM storage unit from the STT-MRAM storage unit array, inputs the resistance comparison into a sensing amplifier circuit SA, and outputs a comparison result. The application makes the PUF response have strong nonlinearity, thereby significantly improving the security, and improving the performance of the PUF in speed, power consumption, area and the like.

The invention relates to the technical field of integrated circuits, and discloses a reference current configuration circuit for a nonvolatile memory, which comprises a current reference circuit for generating a reference current, the value of which is configurable; the storage array comprises a plurality of storage units; the comparator is connected with the current reference circuit and the storage array; the comparator is used for comparing the reference current with the unit current to output a comparison result; wherein the unit current is the current of a selected memory unit in a first typical region or a second typical region in the memory array; the digital logic control circuit is connected with the current reference circuit and the comparator and is used for obtaining extreme value current corresponding to the first typical region and the second typical region based on a comparison result of the comparator; and the value of the reference current is configured according to the extreme value current. According to the circuit, the stable yield of mass production of the nonvolatile memory can be ensured, and meanwhile, the time overhead and human input for manually configuring and reading current parameters are avoided. The invention further discloses the nonvolatile memory.

The present invention discloses a two-dimensional AMR sensor switch chip signal architecture and detection method. In the signal circuit architecture, the clock signal output terminal of the fast clock circuit is connected to the clock signal input terminal of the first combinational logic operation module and the clock signal input terminal of the second combinational logic operation module, and the clock signal output terminal of the slow clock circuit is connected to the clock signal input terminal of the first combinational logic operation module; the first combinational logic operation module outputs an X-direction sampling signal, a Y-direction sampling signal, and a detection enable signal, and the second combinational logic operation module outputs a comparator enable signal, a chopping signal, and an XY-direction switching signal. Chopping offset cancellation technology is used to improve detection accuracy, and time-division multiplexing technology is used to share a processing signal chain, achieving low-power two-dimensional signal acquisition and detection in the X and Y directions, and flexible switching of directions according to actual needs.

The invention provides a source driver, a display driving device, and a display device including the display driving device. A display driving apparatus according to one or more example embodiments includes a source driver configured to output a data signal obtained by amplifying an input signal to a source line in a first period, and receive a detection signal from the source line in a second period different from the first period, and outputs a comparison result signal based on a comparison between the detection signal and the input signal; and a driving controller configured to determine a characteristic of the source line based on a timing at which a level of the comparison result signal transitions in the second period.

The present application discloses a CAN bus transceiver bus common-mode voltage detection circuit, which relates to the technical field of integrated circuits. The circuit includes: a sampling module, a comparison module and a logic module; the comparison module is connected to the sampling module and the logic module respectively, and the sampling module is connected to the output circuit of the CAN bus transceiver; the sampling module is used to collect the driving current of the CAN bus transceiver output circuit and send the driving current to the comparison module; the comparison module is used to compare the driving current with a preset reference current and output the comparison result to the logic module; the comparison result includes: the signal state of a high-side current comparison signal and a reverse-side current comparison signal; the logic module is used to determine that the bus common-mode voltage of the CAN bus transceiver is not within a preset normal range when the signal state of the high-side current comparison signal or the reverse-side current comparison signal in the comparison result is a high level, so as to facilitate fault diagnosis and maintenance.

The present invention discloses a high-precision voltage-mode relaxation oscillator, comprising: a reference current source; a bandgap reference voltage source; a three-terminal input and dual-output comparator, wherein the three-terminal input includes a positive terminal input connected to a reference voltage V REF and two negative terminal inputs respectively connected to the positive terminals of capacitors C1 and C2. The comparison results of the two negative terminal inputs with the positive terminal input are respectively the two output signals of the comparator. Two capacitors C1 and C2, whose negative terminals are both grounded, and whose positive terminals are respectively connected to the two negative terminal inputs of the comparator; a digital control circuit, which consists of a latch formed by two NOR gates and two inverters. The comparator adopted by the voltage-mode relaxation oscillator has a dual-output structure, and there is no need to additionally adopt a D flip-flop for sampling and frequency division. The control logic only adopts a latch formed by two NOR gates and two inverters, which improves the output frequency of the voltage-mode relaxation oscillator, reduces the power consumption and layout area of the circuit.

A kind of digital audio removes the stable earphone amplifier of jitter, including correction module, correction module is set between input interface and amplification module, for correcting the deviation of clock jitter.It is also provided with storage module, energy analysis module, detection module and amplification control module;Storage module obtains digital audio file from player, and is stored in storage module;Energy analysis module extracts the waveform vibration curve of audio file to be played or being played from storage module, and carries out analysis, extracts waveform feature and sends to detection module;Detection module extracts waveform data from the signal output by amplification module, and extracts the features of waveform data;Detection module compares the waveform features sent by energy analysis module with the waveform features actually played by amplification module, and outputs comparison result, solves the volume variation and instability caused by correction module.

The utility model relates to a heating system dry burning protection circuit which comprises a power switch S1, a detection circuit, a comparison circuit, a comparator, successive approximation logic and a digital circuit, one end of the detection circuit is connected with a power supply, the other end of the detection circuit is connected with a heating wire, and the detection circuit is provided with a first constant current source and a detection switch S2 and generates a first voltage signal VE; the comparison circuit comprises a detection resistor and an adjustable constant current source to generate a second voltage signal VS, the positive and negative input ends of a comparator respectively receive the first voltage signal VE and the second voltage signal VS and output a comparison result to successive approximation logic, and the successive approximation logic can adjust the current of the adjustable constant current source and output a heating wire resistance value digital code DXlt; n-1: 0gt; the digital circuit is based on the digital code DXlt; n-1: 0gt; whether the heating wire is dry-burnt or not is judged according to the relative change, an expensive and complex microcontroller (MCU) is prevented from being used, and effective monitoring and intelligent protection of the state of the heating wire are achieved through low-cost hardware.

The present invention relates to the field of integrated circuit technology, and in particular to a low-ripple, fast-response digital LDO circuit and control method. The circuit comprises: a clock-controlled comparator for real-time monitoring of the deviation between the feedback voltage VFB and the reference voltage VREF and outputting a comparison signal; a partial stability detection circuit comprising a counter and a sequence detector, both of which are digitally designed; the counter, based on the continuity of the comparison signal, emits a Cnt signal for detecting the continuity of the output signal; the sequence detector, based on the output mode of the output signal, emits a mode signal for evaluating whether the output signal has reached a preset target stable state; and a shift control circuit, based on the Cnt and mode signals provided by the partial stability detection circuit, dynamically controls and adjusts a PMOS switch array to achieve voltage regulation. The present invention can solve the ripple problem of traditional digital LDOs, ensuring fast response while improving the accuracy of the output voltage. It avoids the use of window comparators and multiple reference voltages, and eliminates errors caused by offsets between multiple comparators.

The invention discloses a current calibration device and method. The device comprises a comparison module, a logic control module and a calibration current module, the comparison module is connected with the digital-to-analog converter and the logic control module; the calibration current module is connected with the digital-to-analog converter and the logic control module; the logic control module generates an initial control code output to the calibration current module, so that the calibration current module generates an initial calibration current output to the digital-to-analog converter according to the initial control code; the digital-to-analog converter outputs a current to be calibrated to the comparison module according to the initial calibration current, the comparison module compares the current to be calibrated with a reference current and outputs a comparison result to the logic control module, and the logic control module generates a target control code output to the calibration current module by adopting a successive approximation method according to the comparison result; the target control code is used for current calibration of the digital-to-analog converter. According to the invention, the mismatch error can be reduced without increasing the size of the main current source unit in the digital-to-analog converter.

The embodiment of the invention discloses a clock signal frequency detection circuit. The circuit comprises a first edge pulse generator, a first latch, a switch module, a time length comparison module and a second edge pulse generator. The first edge pulse generator is used for generating a first clock edge pulse signal according to the edge of a to-be-tested clock signal; the first latch is used for receiving a first clock edge pulse signal and generating a first control signal according to the first clock edge pulse signal; the switch module is switched on or switched off according to the first control signal; the time length comparison module is used for comparing the period of the first clock edge pulse signal with reference time and outputting a comparison result; the second edge pulse generator is used for generating a second clock edge pulse signal according to the edge of the comparison result. According to the technical scheme provided by the embodiment of the invention, the time length comparison module is opened at the edge of the to-be-detected clock signal and closed after comparison, so that low-power-consumption clock signal frequency detection is realized.

An ADC system may include an ADC, a comparator, a voltage source, a comparator output polarity control circuit and a comparator output counter. An analog input signal may be input to a first input of the comparator, and an output of the voltage source may be input to a second input of the comparator. The comparator may generate an output to the comparator output polarity control circuit, and the comparator output counter may count clock cycles while the comparator output is asserted and may assert a monitor output based on the comparator output counter value. The monitor output may be an interrupt, an alarm or other system alerts and may control system operation.

The present application provides a comparator, comprising: an input circuit having an output terminal for generating a differential signal based on an input signal and a reference signal during a sampling phase; a positive feedback circuit connected to the output terminal of the input circuit for accelerating the difference between the differential signals; and an output circuit connected to the output terminal of the input circuit for amplifying and latching the voltage signal at the output terminal of the input circuit during a regeneration phase to output a comparison result. This solution uses a positive feedback circuit to accelerate the difference between the differential signals. When the reference signal is of an inappropriate size, the sampling phase can be shortened, thereby improving the response rate of the comparator and reducing the power consumption of the comparator.

The application discloses a chip design verification system and method, an electronic device and a storage medium, and relates to the technical field of integrated circuit design. Since the excitation descriptor chain table generated by the dynamic scheduler according to the target test scene can directly present whether it contains a transparent attribute, if the transparent attribute exists, the descriptor chain table is directly transmitted to the output comparator through a bypass channel, bypassing the complex calculation link of the reference model; if not, the traditional path is taken to process the reference model. The application provides a differentiated path selection mechanism, changes the data flow direction of the verification platform, and under the condition that the excitation descriptor chain table contains the transparent attribute, the comparison between the excitation descriptor chain table and the to-be-verified execution result can be performed in advance without waiting for the reference model operation, thereby improving the verification efficiency of the to-be-tested design.

The present invention discloses a multi-bit read decision circuit, a memory, and a multi-bit binary data reading method. The multi-bit read decision circuit includes: a multiplexing module for performing gating control on a memory column; a voltage clamping module electrically connected to the multiplexing module, the voltage clamping module for reading a first current signal from a memory array, converting the first current signal into a first converted voltage signal for output; a multi-bit parallel comparison module electrically connected to the voltage clamping module, the multi-bit parallel comparison module for receiving the first converted voltage signal and converting the first converted voltage signal into multiple copied current signals according to a specific copy ratio relationship, comparing the multiple copied current signals with multiple reference current signals, and outputting a comparison result; and a biasing module electrically connected to both the voltage clamping module and the multi-bit parallel comparison module, the biasing module for providing the first clamping voltage signal to the voltage clamping module. The present invention avoids the generation of complex reference currents.

The invention discloses a low-power-consumption tag detection system for a wireless communication chip, and the system comprises a state control module which is provided with a low-frequency timer, and is used for controlling the chip to be switched among three state stages of dormancy, preparation and detection through reading a configuration value of a chip register; the input end of the adaptive ADC acquisition module is connected with the antenna end of the chip and the reference current source, and the adaptive ADC acquisition module is used for comparing the antenna voltage with the reference voltage and outputting a comparison pulse signal; and the input end of the digital logic control module is connected with the output end of the adaptive ADC acquisition module, and the digital logic control module is used for comparing the pulse signals, performing shaping, counting and logic judgment, outputting a quantized value, comparing the quantized value with a preset voltage threshold interval, outputting a label approach judgment result, and judging whether the dormancy stage is interrupted or not based on the label approach judgment result. According to the invention, the environmental noise and the real tag signal can be effectively distinguished, the false triggering rate is obviously reduced, and low-power-consumption operation of the chip is realized.

The invention provides a gene data lookup table coding method and device based on in-memory calculation. The method comprises the following steps: splitting three-dimensional lookup table data, and sequentially storing the split three-dimensional lookup table data into a plurality of SRAM (Static Random Access Memory) arrays; the method comprises the following steps: acquiring an input sequence of gene data with the length of L, and arranging the input sequence into L-2 triads (addr1, addr2, sym) according to the position of a symbol in the input sequence; determining a target array from the plurality of SRAM arrays according to addr1 in the triads, transmitting N triads to the target array of the triads at a time, and determining a to-be-searched data row from all data rows of the target array according to addr2 in the triads; three dimensions of the lookup table respectively correspond to three dimensions of an addr1 one-dimensional array, an addr2 one-dimensional array and a sym one-dimensional array; the target array completes comparison between all symbols of a data row to be searched and sym in the triple in a single period through a single-period byte search operation, and outputs a comparison result vector; and recording positions representing that the comparison results are the same in the comparison result vector to an output buffer area of the target array, and replacing symbols sym of the input sequence with the positions.

The invention provides an EFUSE programming reading circuit which is characterized in that a comparison voltage output module is used for outputting a comparison voltage, a first end and a second end of a programming control unit in each fuse module are respectively coupled to a first end and a second end of a fuse, and a third end of the programming control unit is grounded. When a programming control signal and a programming power supply control signal are represented to be forbidden, the voltage of the second end of the fuse wire is pulled down to a low level, so that a first comparison unit can carry out comparison conveniently; when the two signals are represented as enabling signals, the voltage of the second end of the fuse wire is pulled up to a preset voltage, and the second end and the third end of the programming control unit are controlled to be conducted so as to fuse the fuse wire; the first comparison unit provides a first current for the fuse wire, compares the voltage value of the first end of the fuse wire with the magnitude of the comparison voltage when the read control signal is enabled, and outputs a comparison result signal. According to the invention, enough programming current is provided only when the fuse needs to be fused, so that the problem of wrong programming is avoided, and long-term reliable reading of the EFUSE is guaranteed.

This application provides a numerical statistics method and a numerical statistics system for executing the method. The numerical statistics system transmits the statistical data to be collected to a first arithmetic unit, which includes multiple arithmetic circuits and an addition circuit. The multiple comparison circuits simultaneously receive the statistical data and output comparison results. The comparison results are transmitted to the multiple addition circuits, which output sum data. The sum data is transmitted to a second arithmetic unit for accumulation, and the accumulation result is stored in a memory, completing the statistical analysis.

The application discloses a logic acceleration circuit and method of high-speed capacitive SAR ADC. The logic acceleration circuit comprises a two-way selector, a latch, a comparator and an adaptive asynchronous clock generator. The two-way selector is used for selecting the output latch result and the comparator result and is connected to the switch of the control capacitor array analog-digital converter (CDAC). The latch is used for latching the comparator result and is connected to the two-way selector. The comparator is used for comparing the output value of the CDAC with a reference voltage V ref , and outputting the comparison result. The comparison result is output to the two-way selector. After the comparison is completed, a comparison completion flag signal is output to the adaptive asynchronous clock generator. The adaptive asynchronous clock generator comprises a delay module DELAY and a plurality of NAND gates and NOT gates and is used for controlling the successive approximation steps. The application accelerates the logic operation, and each bit operation can be accelerated.

The invention discloses a starting and protecting circuit and system of a boost converter. The circuit comprises a selection circuit, a comparison circuit, a feedback circuit and a protection circuit, the selection circuit is connected with the comparison circuit and is used for outputting the starting signal or the reference voltage signal according to the control signal; the comparison circuit is used for comparing a feedback signal of the output end of the boost converter with a signal output by the selection circuit and then outputting a comparison signal; the feedback circuit and the protection circuit are connected with the output end of the comparison circuit, and the feedback circuit is used for outputting an enabling feedback signal; the protection circuit is used for determining whether to output a feedback abnormal signal according to the starting completion signal and the comparison signal, and the feedback abnormal signal is used for representing that the feedback signal is abnormal. And stable rising of the output voltage and stable operation of the system are ensured. Through starting signal control, feedback signal monitoring and abnormity protection, system reliability is improved, chip damage is avoided, and external interference influence is reduced.