44 results about "Output compare" patented technology

The invention discloses a single-pin trimming circuit, which relates to the technical field of analog circuit design and comprises a comparator module, a first input end of the comparator module is connected to a single pin, a second input end of the comparator module is connected to a reference voltage, and the comparator module is used for comparing an input voltage of the single pin with the reference voltage and outputting a comparison signal; the input end of the time sequence decoding module is connected to the output end of the comparator module, and the time sequence decoding module is configured as follows: a, the logic state of a trimming position is judged according to the duration time of the pulse in the comparison signal; and b, addressing different trimming positions according to the number of pulses in the comparison signal, and further generating a multi-position trimming control signal through a series of pulse signals input by the single pin. Accurate control of a multi-bit fuse trimming circuit in a chip is realized by using single-pin resources.

The application provides a comparator and a decision feedback equalization circuit, comprising a first input circuit, which is used for generating a first differential signal according to an input signal and a first reference signal under the control of a control signal; a first positive feedback circuit, which is used for accelerating the difference between the first differential signal; a second input circuit, which is used for generating a second differential signal according to the input signal and a second reference signal under the control of the control signal; wherein the first reference signal is greater than the second reference signal; a second positive feedback circuit, which is used for accelerating the difference between the second differential signal; and an output circuit, which is connected with the output end of the first input circuit and is used for amplifying and latching the voltage signal of the output end of the first input circuit or the voltage signal of the output end of the second input circuit in a regeneration stage to output a comparison result. The response rate of the comparator in the application is high, the power consumption is small, the working voltage is low and the inter-symbol interference can be eliminated.

The robot controller includes a communicator, a storage, and a processor. An input signal is input to the communicator. The storage stores the control software. The processor creates the command signal including the command value for operating the robot based on the input signal and the control software. The processor reads out the past input signal and the past command signal from the storage or from external source. After updating the control software, the processor creates a confirmation command signal based on the past input signal and the control software. The processor compares the past command signal with the confirmation command signal and outputs the comparison result.

The invention belongs to the technical field of integrated circuits, and particularly relates to a burning circuit with a configurable port mapping function and a burning method thereof. Comprising a mapen signal generating circuit which is used for detecting and counting rising edges of clock signals CLKPmap input by a clock mapping IO port, when a counting value reaches a preset fixed threshold value, data signals DATAPmap input by a data mapping IO port serve as to-be-matched data, the to-be-matched data are compared with reference data bit by bit, and when the counting value reaches the preset fixed threshold value, the to-be-matched data are obtained; a comparison result signal mapen is output to enable the port configuration circuit; the port configuration circuit is used for selecting a mapping pair port or a default pair port as a burning port under the enabling of the comparison result signal mapen; according to the method, the default port and the mapping port are selected, so that the layout flexibility of the PCB is improved, the wiring complexity is reduced, and meanwhile, the adaptability of a packaging form is improved.

Provided are a malicious attack protection circuit, a system-on-chip including the same, and an operating method thereof. The malicious attack protection circuit includes a reference interrupt generator to output a reference interrupt signal every reference interrupt period, a variable clock manager for outputting an operating clock signal to a logic circuit outside the malicious attack protection circuit and a variable clock signal having a variable period, a variable interrupt generator to output an interrupt signal every variable interrupt period based on the variable clock signal, a comparison circuit to compare the reference interrupt signal with the interrupt signal and output a comparison result signal, and a controller that interrupts the output of the operating clock signal input to the logic circuit, according to the comparison result signal.

The application discloses a reconfigurable strong PUF circuit and method with strong nonlinear response, an STT-MRAM storage unit array is used for storing data information "0" or "1", an odd array access transistor is used for accessing the STT-MRAM storage unit of an odd bit, and an even array access transistor is used for accessing the STT-MRAM storage unit of an even bit; an odd array excitation selection transistor is used for controlling the write signal of the STT-MRAM storage unit of the odd bit, and an even array excitation selection transistor is used for controlling the write signal of the STT-MRAM storage unit of the even bit; an array selection circuit ASC selects an odd row STT-MRAM storage unit and an even row STT-MRAM storage unit from the STT-MRAM storage unit array, inputs the resistance comparison into a sensing amplifier circuit SA, and outputs a comparison result. The application makes the PUF response have strong nonlinearity, thereby significantly improving the security, and improving the performance of the PUF in speed, power consumption, area and the like.

A kind of digital audio removes the stable earphone amplifier of jitter, including correction module, correction module is set between input interface and amplification module, for correcting the deviation of clock jitter.It is also provided with storage module, energy analysis module, detection module and amplification control module;Storage module obtains digital audio file from player, and is stored in storage module;Energy analysis module extracts the waveform vibration curve of audio file to be played or being played from storage module, and carries out analysis, extracts waveform feature and sends to detection module;Detection module extracts waveform data from the signal output by amplification module, and extracts the features of waveform data;Detection module compares the waveform features sent by energy analysis module with the waveform features actually played by amplification module, and outputs comparison result, solves the volume variation and instability caused by correction module.

The utility model relates to a heating system dry burning protection circuit which comprises a power switch S1, a detection circuit, a comparison circuit, a comparator, successive approximation logic and a digital circuit, one end of the detection circuit is connected with a power supply, the other end of the detection circuit is connected with a heating wire, and the detection circuit is provided with a first constant current source and a detection switch S2 and generates a first voltage signal VE; the comparison circuit comprises a detection resistor and an adjustable constant current source to generate a second voltage signal VS, the positive and negative input ends of a comparator respectively receive the first voltage signal VE and the second voltage signal VS and output a comparison result to successive approximation logic, and the successive approximation logic can adjust the current of the adjustable constant current source and output a heating wire resistance value digital code DXlt; n-1: 0gt; the digital circuit is based on the digital code DXlt; n-1: 0gt; whether the heating wire is dry-burnt or not is judged according to the relative change, an expensive and complex microcontroller (MCU) is prevented from being used, and effective monitoring and intelligent protection of the state of the heating wire are achieved through low-cost hardware.

The embodiment of the invention discloses a clock signal frequency detection circuit. The circuit comprises a first edge pulse generator, a first latch, a switch module, a time length comparison module and a second edge pulse generator. The first edge pulse generator is used for generating a first clock edge pulse signal according to the edge of a to-be-tested clock signal; the first latch is used for receiving a first clock edge pulse signal and generating a first control signal according to the first clock edge pulse signal; the switch module is switched on or switched off according to the first control signal; the time length comparison module is used for comparing the period of the first clock edge pulse signal with reference time and outputting a comparison result; the second edge pulse generator is used for generating a second clock edge pulse signal according to the edge of the comparison result. According to the technical scheme provided by the embodiment of the invention, the time length comparison module is opened at the edge of the to-be-detected clock signal and closed after comparison, so that low-power-consumption clock signal frequency detection is realized.

An ADC system may include an ADC, a comparator, a voltage source, a comparator output polarity control circuit and a comparator output counter. An analog input signal may be input to a first input of the comparator, and an output of the voltage source may be input to a second input of the comparator. The comparator may generate an output to the comparator output polarity control circuit, and the comparator output counter may count clock cycles while the comparator output is asserted and may assert a monitor output based on the comparator output counter value. The monitor output may be an interrupt, an alarm or other system alerts and may control system operation.

The application discloses a chip design verification system and method, an electronic device and a storage medium, and relates to the technical field of integrated circuit design. Since the excitation descriptor chain table generated by the dynamic scheduler according to the target test scene can directly present whether it contains a transparent attribute, if the transparent attribute exists, the descriptor chain table is directly transmitted to the output comparator through a bypass channel, bypassing the complex calculation link of the reference model; if not, the traditional path is taken to process the reference model. The application provides a differentiated path selection mechanism, changes the data flow direction of the verification platform, and under the condition that the excitation descriptor chain table contains the transparent attribute, the comparison between the excitation descriptor chain table and the to-be-verified execution result can be performed in advance without waiting for the reference model operation, thereby improving the verification efficiency of the to-be-tested design.

The invention discloses a low-power-consumption tag detection system for a wireless communication chip, and the system comprises a state control module which is provided with a low-frequency timer, and is used for controlling the chip to be switched among three state stages of dormancy, preparation and detection through reading a configuration value of a chip register; the input end of the adaptive ADC acquisition module is connected with the antenna end of the chip and the reference current source, and the adaptive ADC acquisition module is used for comparing the antenna voltage with the reference voltage and outputting a comparison pulse signal; and the input end of the digital logic control module is connected with the output end of the adaptive ADC acquisition module, and the digital logic control module is used for comparing the pulse signals, performing shaping, counting and logic judgment, outputting a quantized value, comparing the quantized value with a preset voltage threshold interval, outputting a label approach judgment result, and judging whether the dormancy stage is interrupted or not based on the label approach judgment result. According to the invention, the environmental noise and the real tag signal can be effectively distinguished, the false triggering rate is obviously reduced, and low-power-consumption operation of the chip is realized.

This application provides a numerical statistics method and a numerical statistics system for executing the method. The numerical statistics system transmits the statistical data to be collected to a first arithmetic unit, which includes multiple arithmetic circuits and an addition circuit. The multiple comparison circuits simultaneously receive the statistical data and output comparison results. The comparison results are transmitted to the multiple addition circuits, which output sum data. The sum data is transmitted to a second arithmetic unit for accumulation, and the accumulation result is stored in a memory, completing the statistical analysis.

The application discloses a logic acceleration circuit and method of high-speed capacitive SAR ADC. The logic acceleration circuit comprises a two-way selector, a latch, a comparator and an adaptive asynchronous clock generator. The two-way selector is used for selecting the output latch result and the comparator result and is connected to the switch of the control capacitor array analog-digital converter (CDAC). The latch is used for latching the comparator result and is connected to the two-way selector. The comparator is used for comparing the output value of the CDAC with a reference voltage V ref , and outputting the comparison result. The comparison result is output to the two-way selector. After the comparison is completed, a comparison completion flag signal is output to the adaptive asynchronous clock generator. The adaptive asynchronous clock generator comprises a delay module DELAY and a plurality of NAND gates and NOT gates and is used for controlling the successive approximation steps. The application accelerates the logic operation, and each bit operation can be accelerated.

The utility model provides a watchdog circuit with an anti-mis-closing function, which comprises a reset control circuit, a logic control circuit, a multi-bit comparator circuit and a watchdog module, and is characterized in that the reset control circuit is used for outputting an asynchronous reset synchronous evacuation signal to a reset end of the watchdog module after a clock period is added when an asynchronous reset signal is cancelled; the logic control circuit is used for outputting a multi-bit set value to a first input end of the multi-bit comparator circuit; the multi-bit comparator circuit is used for comparing a multi-bit set value with a multi-bit constant and outputting a comparison signal to the enable end of the watchdog module. The clock of the watchdog module is input into the crystal oscillator clock and is reset by the external reset control circuit, and enabling failure caused by an impact event is avoided through multi-bit control, so that the effects of preventing mistaken closing and stabilizing clock signals are achieved.

The present invention relates to a memory and a reading circuit thereof. The reading circuit comprises: a first signal generation circuit, used for generating a first signal; a reference signal generation circuit, used for establishing a reference signal on the basis of the first signal; a bit line pre-charging circuit, used for pre-charging a bit line when a pre-charging signal is received; a comparison circuit, connected to the reference signal generation circuit, the bit line, and a selected memory cell, and used for, when an electrical signal obtained by reading the selected memory cell is superimposed with an electrical signal from the pre-charged bit line, comparing the superimposed signal with the reference signal, and outputting a comparison result; and a first signal pre-charging circuit, connected to the first signal generation circuit, and used for pre-charging the first signal generation circuit when the pre-charging signal is received, so as to accelerate the establishment of the first signal. In the present invention, by providing the first signal pre-charging circuit, when the pre-charging signal arrives, the establishment of the first signal is accelerated, thereby preventing the occurrence of a false "1" when reading data "0" of a memory cell.

A preamble detection circuit, an operating method thereof, and a memory device are provided. The preamble detection circuit includes a comparison circuit configured to compare a level of a data strobe signal with a level of a reference voltage and to output a comparison signal, and a reset signal generation circuit configured to output a reset signal having a pulse width corresponding to a preamble period of the data strobe signal based on the comparison signal.

The application discloses a kind of storage computing conversion circuits, including shift addition unit, capacitor array unit, comparison unit and SAR control logic unit, by shift addition unit to the input analog signal is shifted weighted addition processing, to obtain the first voltage signal after processing;Capacitor array unit is handled to the reference voltage signal inputted from outside, to obtain the second voltage signal after processing;The first input end of comparison unit is connected with the output end of shift addition unit, the output end of comparison unit is connected with the output end of capacitor array unit, to compare first voltage signal and second voltage signal, to output comparison result;The input end of SAR control logic unit is connected with the output end of comparison unit, to output digital signal according to comparison result;Thus, by analog circuit to realize shift addition function, can reduce the delay and area overhead caused by traditional digital shift adder, to improve conversion efficiency.

This invention provides an oscillation circuit, a self-calibration method for the oscillation circuit, and a chip. The oscillation circuit includes an oscillation module, a comparison module, and a logic control module. The input terminal of the comparison module is connected to the output terminal of the oscillation module, and the input terminal of the logic control module is connected to the output terminal of the comparison module. The output terminal of the logic control module is fed back to the oscillation module and the comparison module. The oscillation module outputs a clock signal. The comparison module compares the clock signal and an adjustable reference voltage under the action of the output signal of the logic control module and outputs the comparison result. The logic control module generates a control signal based on the comparison result and outputs it to the comparison module and the oscillation module to calibrate the frequency of the clock signal to a target value. This invention uses a closed-loop feedback mechanism to compare the clock signal and the adjustable reference voltage, and adaptively adjusts the target parameters of the oscillation module based on the comparison result, thereby reducing cost and power consumption and improving calibration accuracy.

The application provides a successive approximation analog-digital converter and a conversion method thereof, the analog-digital converter comprising: a sequentially connected capacitor switch array, a comparator and a digital logic circuit; the capacitor switch array accepts an input analog signal, samples and converts the analog signal, and outputs a converted signal to the comparator for comparison; the comparator compares the converted signal, and outputs a comparison result to the digital logic circuit; the digital logic circuit outputs a feedback control signal to the capacitor switch array according to the comparison result, and outputs a digital signal, wherein the number of bits of the digital signal is N, and N is a positive integer; and the switches in the capacitor switch array are switched according to the feedback control signal to open and close. N The application can be applied to analog signals with common-mode voltage, and has simple structure and is easy to implement.

The invention provides an A / D converter which is provided with a comparator capable of outputting a comparison result at a high speed with a simple structure. The A / D converter (10) is a successive approximation type A / D converter provided with a comparator (100). As a P-type MOS transistor, a comparator (100) is provided with a first transistor (TR1), a second transistor (TR2), and a third transistor (TR3). A comparator (100) is provided with a fourth transistor (TR4), a fifth transistor, and an eighth transistor, the source of which is connected to a ground potential (VSS), the drain of which is connected to a second node (N2), and the gate of which is connected to a reference potential, a third node, and a first signal, respectively. The comparator (100) is provided with a sixth transistor (TR6), a seventh transistor (TR7), and a ninth transistor (TR9), the sources of which are connected to the ground potential (VSS), the drains of which are connected to the third node (N3), and the gates of which are connected to the second node (N2), the comparison potential, and the first signal, respectively.

The invention relates to the technical field of data interaction, and provides an NAND memory reading circuit, which comprises a pre-charging circuit for pre-charging a NAND memory to a first high voltage or a first low voltage; the NAND memory is used for reading the first voltage signal of the pre-charging circuit and the second voltage signal of the ping-pong discharge path corresponding to the current period, and controlling the whole circuit to enter a charging state or a discharging state; the ping-pong bleeder path is switched between a second high voltage and a second low voltage according to the first voltage signal read by the NAND memory; the comparison circuit is used for comparing the first voltage signal stored in the NAND memory with a reference voltage value and outputting a comparison result; the register circuit is used for storing a second voltage signal corresponding to the previous period; and the output circuit outputs a corresponding output signal according to the comparison result and the second voltage signal. According to the scheme, charges on the BL are utilized to the maximum extent, additional supplementary consumption is reduced, and the voltage needed by pre-charging is reduced.

The invention relates to metastable state detection and correction in analog-to-digital signal converters. Embodiments disclosed herein relate to detecting metastable states to reduce noise and improve performance of an analog-to-digital converter (ADC) (120). In an example, an ADC (120) is provided that includes comparator circuitry (comparator 215), synchronization circuitry (synchronizers 225 and 230), digital output circuitry (SAR circuitry 235), and stability check circuitry (digital stability checker circuitry 240). The comparator circuitry performs a comparison of an analog input signal and an analog feedback signal and outputs a result of the comparison. Synchronization circuitry samples the results of the comparison at different times, resulting in a first sampled value and a second sampled value. The digital output circuitry generates a digital output signal based on the first sampling value and outputs the digital output signal. Stability check circuitry determines whether a metastable condition occurs with respect to the analog-to-digital converter based on the first sampled value and the second sampled value, and outputs an indication of whether the metastable condition occurs.

The present invention relates to a self-diagnosis apparatus of an electronic device, including a vector memory configured to store a test function code for testing a device under test (DUT) equipped with a plurality of cores performing arithmetic operations, a function test expectation value corresponding to a function test according to the test function code, a design for test (DFT) test code for testing, a DFT test expectation value corresponding to a DFT test according to the DFT test code, and a non-test function code for general arithmetic operations or operations of the DUT, a test data memory configured to store test data, and a secure area test controller configured to select a test mode, control an environment variable of a test signal applied to the DUT and test the DUT, compare the function test expectation value with a test function code result value, and compare the DFT test expectation value with a DFT test code result value to output comparison result information.

The present disclosure relates to a decision feedback equalizer, a receiver and a chip, the decision feedback equalizer comprising: a comparison circuit for comparing a first differential input signal and a second differential input signal and outputting a comparison result; the logic circuit is used for performing logic operation irrelevant to the comparison result according to a clock input signal and a tap enable signal representing whether a feedback tap of the decision feedback equalizer is activated or not so as to generate a logic operation result; and the switching circuit is used for selectively reducing the voltage of the higher one of the first differential input signal and the second differential input signal according to the comparison result and the logical operation result. Therefore, the data transmission time delay of the data branch of the decision feedback equalizer can be reduced.

A system (300) includes a memory (206) configured to store test patterns. A first lockstep core (102) and a second lockstep core (104) are configured to receive a same set of test patterns. During a reset of the first lockstep core and the second lockstep core, a first scan output is generated from the first lockstep core (102) and a second scan output is generated from the second lockstep core (104). A comparator (306) can be coupled to the first lockstep core and the second lockstep core and configured to compare the first scan output and the second scan output. If the first and second scan outputs are the same, the first and second lockstep cores (102, 104) can be initialized to a similar state. The first and second lockstep cores can comprise non-resettable flip-flops.

This application relates to a test machine and its service board. The service board includes: a waveform generation module connected to a waveform synthesis module, which outputs waveform data to the waveform synthesis module; a waveform synthesis module connected to a parallel-to-serial conversion module, which splits the waveform data output by the waveform generation module into parallel data and sends it to the parallel-to-serial conversion module; a parallel-to-serial conversion module connected to the device under test (DUT) and a comparison module, which performs parallel-to-serial conversion and delay processing on the received parallel data, sends the delayed serial data to the DUT, and performs delay and serial-to-parallel conversion on the feedback data from the DUT, outputting sampled data to the comparison module; and a comparison module receiving the sampled data sent by the parallel-to-serial conversion module and outputting the comparison result. By centralizing the data conversion and delay processing within the parallel-to-serial conversion module, other modules outside the parallel-to-serial conversion module can use a low-speed clock to process data, reducing data processing power consumption.

Embodiments of the present application relate to average current control in a stepper motor. A stepper motor driver includes an H-bridge including a first output and a second output. The H-bridge includes a low side transistor (LS2) coupled between the first output and ground. A reference current circuit (502) is configured to generate a reference current. The reference current circuit (502) has a reference output. An averager circuit (550) includes an input and an output. The input of the averager circuit (550) is coupled to the first output of the H-bridge. A comparator (555) includes a first comparator input and a second comparator input. The first input of the comparator (555) is coupled to the output of the averager circuit (550) and the second input of the comparator (555) is coupled to the reference output.

The read circuit of the antifuse memory of the present invention is used for logic to read a specific antifuse cell in the antifuse memory. It includes: a pre-charged PMOS, the source of which is connected to the internal power supply of the memory, the drain of which is connected to the bit line of the selected specific antifuse cell, and a read enable signal input to its gate; the pre-charged PMOS pre-charges the bit line to a predetermined level of the internal power supply of the memory; a comparator, the level of the bit line is input to the negative input of the comparator, a reference level is input to the positive input of the comparator, the comparator compares the level of the bit line with the reference level, and outputs the comparison result from its output; a feedback circuit, which is composed of a PMOS, the source of which is connected to the internal power supply of the memory, the drain of which is connected to the bit line of the selected specific antifuse cell, and the gate of which is connected to the output of the comparator; and a latch, which receives the comparison result output from the output of the comparator, latches the comparison result, and outputs it. The feedback circuit is configured to slow down the rate of voltage drop of the bit line when the bit line of the selected specific antifuse cell is discharged due to a decrease in the resistance value of the specific antifuse cell.

The application discloses a self-oscillation comparator and method for successive approximation analog-to-digital converter, and belongs to the field of analog and mixed signal integrated circuit design. The application comprises a differential input stage, a self-oscillation core, an isolation and clock control unit, an oscillation detection module, a counting decision module and an output interface module. The application converts the input differential voltage into the difference of the number of times of flipping of two oscillation nodes within a fixed time window, and counts the difference by the oscillation detection module and the counting decision module to output the comparison result. The application realizes the orderly switching of the sampling, isolation, comparison and reset stages by the multiphase clock control, effectively reduces the random noise and input kickback interference, improves the decision robustness of the comparator under the condition of low power voltage and small input difference, and can be widely applied in low-power medium-speed SAR ADC, sensor interface and mixed signal system chip.