278results about How to "Improve current drive capability" patented technology

A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wherein a semiconductor forming the channel region has a lattice strain.

Methods for forming asymmetric gate structures comprising spacer elements disposed on the opposed sides of a gate electrode and having a different width are disclosed. The asymmetric gate structures are employed to form an asymmetric design of a halo region and extension regions of a field effect transistor using a symmetric implantation scheme, or to further enhance the effectiveness of asymmetric implantation schemes. The transistor performance may be significantly enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even be completely avoided to further enhance the transistor performance.

A method and structure for a bipolar transistor comprising a patterned isolation region formed below an upper surface of a semiconductor substrate and a single crystal extrinsic base formed on an upper surface of the isolation region. The single crystal extrinsic base comprises a portion of the semiconductor substrate located between the upper surface of the isolation region and the upper surface of the semiconductor substrate. The bipolar transistor further comprises a single crystal intrinsic base, wherein a portion of the single crystal extrinsic base merges with a portion of the single crystal intrinsic base. The isolation region electrically isolates the extrinsic base from a collector. The intrinsic and extrinsic bases separate the collector from an emitter. The extrinsic base comprises epitaxially-grown silicon. The isolation region comprises an insulator, which comprises oxide, and the isolation region comprises any of a shallow trench isolation region and a deep trench isolation region.

In an image sensor, the current through the in-pixel readout transistor is sensed by a circuit that is external to the pixel, and according to the measured current value a feedback current is supplied to charge the read-line parasitic capacitance. The feedback current is supplied by a circuit that also is external to the pixel area. The amplifier structure is reconfigurable so that it can be used both to read out and to reset the pixel.

In a driving circuit, for controlling the turning on and off of a main semiconductor switching device of an insulated gate type, in an insulated gate semiconductor switching device for electric power conversion, bipolar semiconductor devices of an insulated gate control type, particularly insulated gate bipolar transistors (IGBTs) are used at the output stage of a circuit that controls the gate voltage of the main semiconductor switching device.

A field effect transistor including a gate isulation portion, an organic semiconductor portion, a source electrode and a drain electrode, wherein when a voltage is applied to the gate at 70° C. for 5.0±0.1 hours so that the field strength in the gate insulation portion would be 100±5 MV/m, the change in the threshold voltage is within 5 V. The organic semiconductor portion has a high driving stability, of which the change in characteristics by driving is thereby small.

The present invention is configured such that a resistance variable element (16) and a rectifying element (20) are formed on a substrate (12). The resistance variable element (16) is configured such that a resistance variable layer (14) made of a metal oxide material is sandwiched between a lower electrode (13) and an upper electrode (15). The rectifying element (20) is connected to the resistance variable element (16), and is configured such that a blocking layer (18) is sandwiched between a first electrode layer (17) located on a lower side of the blocking layer (18) and a second electrode layer (19) located on an upper side of the blocking layer (18). The resistance variable element (16) and the rectifying element (20) are connected to each other in series in a thickness direction of the resistance variable layer (14), and the blocking layer (18) is formed as a barrier layer having a hydrogen barrier property.

A diode (QN1) is connected in parallel to one of two bipolar transistors (PB1, NB1) constituting a semiconductor-controlled rectifier or SCR (400) in such a direction as to encourage positive feedback. This enhances current drivability and accelerates a turn-on operation.

The present invention relates to a high linearity GaN fin-type high electron mobility transistor and a manufacture method thereof. From bottom to top, the transistor sequentially comprises a substrate, a buffer layer, a barrier layer, and a passivation layer. A source electrode is arranged at one end above the barrier layer and a drain electrode is arranged at the other end. The passivation layer is arranged above the barrier layer between the source electrode and the drain electrode. A groove is arranged in the passivation layer. A T-shaped gate is arranged in the groove. The transistor is characterized in that GaN-based three-dimensional fins in periodical arrangement are etched only on the barrier layer and the buffer layer in an area below the groove, the length of the GaN-based three-dimensional fins is equal to the length of the groove, and an isolation groove that is etched is arranged between adjacent GaN-based three-dimensional fins. The transistor has high linearity and output current, strong gate control capability, good heat dissipation performance, and high frequency characteristic. The manufacture method is simple and reliable, and is applicable to high power, high linearity microwave power devices.

The invention discloses a bulk-silicon-based manufacturing method for a vertically stacked under-gate type silicon nano-wire metal oxide semiconductor field effect transistor (SiNWFET). The method comprises the following steps of: providing a bulk silicon substrate on which SiGe layers and Si layers are alternately grown; photo-etching and etching the SiGe layers and the Si layers to form fin-shaped active regions, and taking the residual SiGe layers and the residual Si layers as source and drain regions; selectively etching and removing the SiGe layers in the fin-shaped active regions to form silicon nano-wires which are vertically stacked; forming a virtual isolation layer on the bulk silicon substrate between the source region and the drain region; forming a gate trench in the virtual isolation layer; forming gate oxide layers on the silicon nano-wires; forming a gate in the gate trench; removing the virtual isolation layer to form an isolated trench; and forming an isolation dielectric layer in the isolated trench. Due to the adoption of the virtual isolation layer, control over the contour of the gate trench is facilitated; the conventional gate oxide layers are adopted; and the silicon nano-wires are vertically stacked, so that the integration level and current driving capability of a device can be improved.

The invention relates to a power unit control plate of a high-voltage frequency converter. The power unit control plate is connected between a main control plate of the high-voltage frequency converter and a power unit of the high-voltage frequency converter, and is a receiving-transmitting serial communication structure; receiving serial communication is defined from the main control plate to the power unit, and transmitting serial communication is defined from the power unit to the main control plate; and an input serial communication signal firstly passes through an input buffer filter circuit to filter out an interfering signal so as to enhance the current drive capability and interference-free feature of the signal, thereby furthest reducing the electromagnetic interference influence in communication. The power unit control plate comprises an address dip switch which is connected with a programmable logic device and is corresponding to the address of a component in the power unit, thereby guaranteeing that a command is accurately and reliably transferred. A temperature sensor is used for measuring the temperature of the component in the power unit and transferring a characteristic curve to adjust the opening voltage of the component so that the opening loss of the component reaches the optimum.

The invention belongs to the technical field of galvanic corrosion measurement for metal materials, in particular relates to a multi-channel galvanic corrosion measurement device. According to the multi-channel galvanic corrosion measurement device, an SOC (System on a Chip) processor structural design is adopted; the front end of an electrode connection cable is connected with an electrode; the rear end of the electrode connection cable is connected into a voltage/current measurement switching unit; two ends of a front end signal conditioning circuit are bridged with a reference source afterbeing electrically communicated with an A/D (Analog-to-Digital) conversion circuit; the front end of the front end signal conditioning circuit is electrically connected with the voltage/current measurement switching unit; the output end of the A/D conversion circuit is electrically communicated with a main control module after being connected in series with a multi-channel electric isolation unit; an SOC processor is arranged in the main control module; the main control module is electrically connected with a display module, a storage module and a communication module respectively, so that electric information control is realized; and a signal input by a reference electrode is incorporated into the front end signal conditioning circuit after being amplified, so that a signal processing system is formed. The multi-channel galvanic corrosion measurement device has the characteristics of simple overall structure, reliable principle, convenience for use and operation, accuracy in measurement data, flexibility for control and wide application range.

The invention discloses a vertically-stacked strain Si/SiGe heterojunction CMOS device structure and a preparation method thereof. The device comprises a silicon substrate, a relaxation SiGe buffer layer, a relaxation Si0.7Ge0.3 virtual substrate, an n<+> delta doping layer, a relaxation Si0.7Ge0.3 interval layer, a strain Si trench, a relaxation Si0.7Ge0.3 intermediate layer, a strain Si0.5Ge0.5 trench, a relaxation Si0.7Ge0.3 cap layer and a Si cap layer from the bottom up in sequence. An n-MOSFET trench adopts a tensile strain Si material, a p-MOSFET trench adopts a compression strain SiGe material, and the n-MOSFET and the p-MOSFET adopt a vertically-stacked structure, and share one polycrystalline SiGe gate electrode, so that electron and hole migration rates are improved greatly, speed and integration level of chips are improved, and new technological approaches are provided for high speed and high frequency development of the Si device and an integrated circuit.

The invention provides a double-layer isolation longitudinal stacked semiconductor nanowire MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The double-layer isolation longitudinal stacked semiconductor nanowire MOSFET comprises a semiconductor substrate, a first semiconductor nanowire MOSFET, a second semiconductor nanowire MOSFET, an isolation medium layer and a buried oxide layer, wherein the first semiconductor nanowire MOSFET further comprises a first semiconductor nanowire group and a first gate oxide layer; the second semiconductor nanowire MOSFET further comprises a second semiconductor nanowire group and a second gate oxide layer; the isolation medium layer is arranged between the first semiconductor nanowire MOSFET and the second semiconductor nanowire MOSFET; and the buried oxide layer is arranged between the first semiconductor nanowire MOSFET and the semiconductor substrate. According to the invention, by using the structural design that the first semiconductor nanowire MOSFET has the longitudinal stacked first semiconductor nanowire group and the second semiconductor nanowire MOSFET has the longitudinal stacked second semiconductor nanowire group, the process can be debugged in a completely independent way and high integration level of the device is obtained. At the same time, by using the double-layer isolation longitudinal stacked semiconductor nanowire MOSFET provided by the invention, the electrical property of the field effect transistor is improved and the device current driving capability is improved in multiples; and the double-layer isolation longitudinal stacked semiconductor nanowire MOSFET provided by the invention is suitable for the technical field of advanced nanodevices.

The invention discloses a manufacturing method of a three-dimensional array grid-last type Si-NWFET (Silicon-Nanowire Field Effect Transistor) based on an SOI (Silicon On Insulator). The manufacturing method comprises the following steps of: alternatively growing silicon layers and germanium-silicon layers on the SOI, forming a fin-shaped active region, forming silicon nanowires in the fin-shaped active region, depositing amorphous carbon in a groove as a virtual isolating layer, then carrying out a grid-last process, and finally and simultaneously carrying out deposition on a groove isolating medium and an interlayer isolating medium. The manufacturing method disclosed by the invention has the advantages that due to existence of an oxygen embedding layer in the SOI, the isolating effect between a grid and an SOI substrate is effectively improved, and the adoption of the grid-last process is beneficial to the control of the profile of the grid and the electrical property of a device; the utilization of the amorphous carbon as the virtual isolating layer is beneficial to the control of the profiles of the grid and the grid groove; and in addition, the silicon-nanowire field effect transistor (Si-NWFET) structure is designed by adopting a three-dimensional array silicon-nanowire structure, so that the number of the nanowires is increased, and the current driving capability of the device is improved.

In a complex semiconductor device, electronic fuses may be formed in the active semiconductor material by using a semiconductor material of reduced heat conductivity selectively in the fuse body, wherein, in some illustrative embodiments, the fuse body may be delineated by a non-silicided semiconductor base material.