410results about How to "Reduce the occupied area" patented technology

The invention discloses a display panel, a method for preparing the same and a display device. The display panel comprises at least one first data line. The first data lines penetrate a functional device zone. The display panel, the method and the display device have the advantages that the portions, which penetrate the functional device zone, of the first data lines are first transparent electricconduction lines, arrangement regions for data lines which penetrate a second non-display zone can be increased, accordingly, the distances between the data lines which penetrate the second non-display zone can be increased, coupling resistance between the adjacent data lines can be lowered, and the problem of abnormal display of existing display panels due to the fact existing data lines are excessively densely arranged can be solved; the display panel is provided with the first transparent electric conduction lines, the quantities of data lines required to be arranged in a border zone can be reduced, accordingly, the purpose of reducing the areas occupied by the border zone can be achieved, and the screen-to-body ratio of the display panel further can be increased.

The invention relates to a filter, in particular to a low-pass filter based on TSV (Through-Silicon-Via) technology. The low-pass filter based on the TSV technology comprises a spiral inductance unit, a rewiring layer and a TSV component, wherein the spiral inductance unit comprises a spiral inductor I and a spiral inductor II, the rewiring layer comprises an input end, an output end, grounding metal, an interconnecting layer I and an interconnecting layer II, the TSV component comprises five coaxial through silicon vias of a through silicon via I, a through silicon via II, a through silicon via III, a through silicon via IV and a through silicon via V respectively which are the same in structure, and each coaxial through silicon via comprises a first dielectric layer, an outer metal layer, a second dielectric layer and a metal core layer in sequence from outside to inside; according to the invention, the coaxial through silicon vias are adopted to realize vertical capacitors, compared with the common plane structure capacitors, the occupied areas of the capacitors are greatly reduced, and the sizes of the devices are reduced to micron magnitudes, so that the circuit integration can be improved, and further the cost is reduced.

The invention discloses a touch electrode structure, a touch screen panel and a display device. The touch electrode structure comprises multiple self-capacitance electrode groups arranged in a matrix shape, wherein each self-capacitance electrode group comprises two L-shaped self-capacitance electrodes which are insulated mutually and complement each other, that is, existing three rectangular and parallel self-capacitance electrodes are combined into the two L-shaped self-capacitance electrodes which complement each other under the premise that the touch precision is unchanged, thus, under the premise that the touch precision of the touch screen panel is guaranteed, the number of the self-capacitance electrodes can be reduced, the number of leads which are connected with the self-capacitance electrodes in the one-to-one correspondence manner can be reduced correspondingly, the opening ratio of the touch screen panel can be increased, besides, the number of peripheral wires connected with the leads in the one-to-one correspondence manner can be reduced, the frame width of the touch screen panel can be reduced, in addition, the number of wiring terminals for connecting the peripheral wires in a touch detection chip can be reduced, and the area occupied by the touch detection chip can be reduced.

The invention discloses a thin-film transistor, an array substrate and a display device. An active layer area which corresponds with a gap between a source electrode and a drain electrode in the thin-film transistor is designed to a bent shape. Relative to a linear active layer area which corresponds with the gap between the source electrode and the drain electrode in the prior art, the length of the active layer area which corresponds with the gap between the source electrode and the drain electrode increases, thereby settling a problem of off current surge. Furthermore, on condition that the areas of the thin-film transistors are same, the length of the active layer area which corresponds with the gap between the source electrode and the drain electrode increases, thereby reducing the area of the thin-film transistor on condition that the off current is ensured. Particularly, when the thin-film transistor is used for high-resolution display, a relatively large aperture ratio can be ensured.

A universal fixture for ultrasonic cleaning to film coated substrate is composed of sliding and fixed rectangular frames with 4 holes at 4 corners, 4 slide rods inserted in said 4 holes, several clampers, and several water-through supporting rods.

The invention relates to a non-refrigeration infrared focal plane array seeker. The structure is characterized in that one end part of a bridge leg is connected with a bridge surface, and the other end part of the bridge leg is connected to a base through an anchor post; the base is a read-out integrated circuit substrate, and the surface of the base is provided with a reflection film layer; the bridge surface is hanged deadly above the reflection film layer, and forms a vacuum clearance layer with the base; the bridge leg is arranged at two sides corresponding to the bridge surface, and the respective lower surface of the bridge leg and the bridge surface are distributed on the same plane; the bridge surface is sequentially provided with a support layer, an absorption layer, an insulation layer, a heat sensitive layer and a protection layer from bottom to up; the bridge leg is sequentially provided with a heat resistance layer, an electric conduction layer and a passivation layer from bottom to up; and the anchor post consists of a metal tungsten post and an oxide silicon post, and is sequentially provided with metal tungsten and silicon oxide materials from the inside to outside. The anchor post provided by the invention is a novel anchor post, compared with the traditional anchor post formed by the traditional filling technology, the area occupied by the anchor post is shortened, and the technology difficulty is reduced.

The invention relates to a one-time programmable memory based on a variable-resistance memory and a preparation method thereof, belonging to the technical field of microelectronic manufacture and thememory. The one-time programmable memory comprises the variable-resistance memory with the characteristic of bipolar conversion and a diode with the rectification characteristic which are connected inseries. The one-time programmable memory based on the variable-resistance memory adopts the diode with the rectification characteristic as a gating unit, adopts the variable-resistance memory with the characteristic of bipolar conversion as a memory unit, connects the diode and the variable-resistance memory in series, not only has simple structure, easy integration, high density and low cost, but also has rectification function when in low impedance state, can restrict read crosstalk in a crossed array structure, avoid misreading, can adopt integration of the crossed array structure and canrealize higher memory density.

The invention relates to a novel technical scheme for producing an LED (Light Emitting Diode) soft light bar and belongs to the technical field of LED landscape and decorative illumination application. The traditional soft light bar is poor in radiating property, high in light depreciation, short in service life and high in cost. According to the novel technical scheme, an LED chip is directly attached to a flexible PCB (Printed Circuit Board). The novel technical scheme has the advantages: 1) the LED chip is directly packaged on the PCB, the LED bracket for packaging the LED and the complex production technology are omitted, the cost is greatly saved and the market potential is huge; 2) the surface of the LED chip is clung to a PCB copper sheet, and the thermal resistance is less than one time of the thermal resistance of the packaged LED radiated through pins, such as 3528LED, 5050LED, and the like, used by the traditional soft light bar, so that the service life is longer; and 3) the LED chip is directly attached to the PCB, so that the area occupied by the LED is smaller, the product is smaller and the cost is lowered.

The invention provides an oversampling 64-time sigma-delta modulation circuit with an effective bit being 18. The circuit comprises an interpolation filter and a sigma-delta modulator. The interpolation filter is used for conducting oversampling interpolation and filtering on digital input signals. The input end of the sigma-delta modulator is connected with the output end of the interpolation filter, the sigma-delta modulator is used for modulating oversampled digital signals, shaping quantized noise introduced by a quantizer, moving noise in the signal bandwidth out of the bandwidth, and meanwhile guaranteeing that transmission of the signals is not affected, and output 1-bit 0/1 code streams need to be restored through a backward-stage analog reconstruction filter so as to acquire analog signals. An improved structure is adopted in a half-band filter in the interpolation filter so that the area of the half-band filter can be greatly reduced; for the sigma-delta modulator, a monocycle high-order structure easier to achieve is adopted, the stability problem is analyzed, the high signal to noise ratio is achieved, and meanwhile stability of the modulator is guaranteed.

The invention provides a touch drive unit as well as a driving method and a touch drive circuit of the touch drive unit, belongs to the technical field of touch drive and aims at solving the problems of complex structure, large area, unstable output and large noise of the existing touch drive circuit. The touch drive unit comprises a shift register module, a gating module and an output module, wherein the shift register module comprises a first control port, an access port and a trigger signal output port, and is connected with the gating module and used for generating a trigger signal; the gating module comprises a second control port and a gating signal port, and is connected with the shift register module and used for controlling the output module; the output module comprises an output port, a stable level port and a touch signal port, and is used for outputting a stable level or touch signal according to the control of the gating module.

The invention relates to a process for preparing vacuum glass. The steps of the process are, (1) keeping a leaking plate mould flat on a glass substrate, on which die orifices are equispaced and compartmentally prepared, (2) coating the supporting pulp on the leaking plate mould to form backstops which are distributed compartmentally and have the same height, inverting the glass substrate on bottom glass, (3) preparing an opening which is inserted in a suction glass tube on the glass, and adopting supporting pulp to seal edges, (4) putting the glass into a heating furnace and treating, (5) connecting the suction glass with a vacuum device until vacuum degree in the vacuum glass reaches 10-2-10-4Pa, hot fusing and sealing the glass tube, thereby obtaining vacuum glass finished products. The invention has the advantages of simple preparation technology, easy operation, lower investment, lower rejection rate, perfect quality and higher production efficiency. Further, the invention adopts mechanical separator system to replace manual operation, which effectively reduces costs of vacuum glass and is applicable for industrial production.

The invention discloses a voltage regulator and a reference voltage generating circuit thereof. The voltage regulator comprises a reference voltage generating circuit, a comparator, a driving unit and a feedback unit, wherein the input end of the driving unit is connected with the output end of the comparator; the output end of the driving unit serves as the output end of the voltage regulator; the input end of the feedback unit is connected with the output end of the driving unit; the output end of the feedback unit is connected with the first input end of the comparator; the reference voltage generating circuit comprises a first voltage dividing unit and a second voltage dividing unit; the first voltage dividing unit is used for dividing a first voltage in the working mode of a load unit to generate a first reference voltage input to the second input end of the comparator; the second voltage dividing unit is used for dividing a second voltage in the standby mode of the load unit to generate a second reference voltage input to the second input end of the comparator; and the second reference voltage is greater than the first reference voltage. According to the invention, the influence of amplitude perturbation on the work of the load unit can be lowered, and the floor area of a decoupling capacitor is small.

The invention relates to a thin film transistor substrate and a manufacturing process thereof. The thin film transistor substrate comprises a plurality of first scanning beams, second scanning beams, data wires, first pixel electrodes, second pixel electrodes, first thin film transistors and second thin film transistors. The first scanning beams are parallel with each other, the second scanning beams are parallel with the first scanning beams as well as insulated and overlapped with the first scanning beams; and the data wires are vertically insulated and crossed with the first scanning beams and the second scanning beams. Grids of the first thin film transistors are connected to the first scanning beams, source electrodes are connected to the data wires, and drain electrodes are connected to the first pixel electrodes; and grids of the second thin film transistors are connected to the second scanning beams, source electrodes are connected to the data wires, and drain electrodes are connected to the second pixel electrodes. The thin film transistor substrate has a high aperture opening ratio.

The invention discloses a power dividing phaser for four-arm helical antenna feed. Through the small power dividing phaser, one input, four power equal divisions and output with phase sequentially differing by 90 degrees are achieved, the input port is located at the bottom of a module and is of a parallel double-line structure, meanwhile, feed is conducted on two symmetrical strip-shaped line coupling units, the input signal power is divided equally, and the phase difference is 180 degrees. Direct-through ports and coupling ports of the two strip-shaped line coupling units which are symmetrical in structure and divided equally in power are connected with four output port electrodes of the side face of an LTCC multilayer base plate through metal wires respectively. By means of the power dividing phaser, the area occupied by the circuit is reduced greatly for further reducing the occupied area and meeting the performance requirement, the integration level and reliability of the power dividing phaser are improved, the bandwidth is wide, the working band ranges from 1.0 GHz to 2.0 GHz, and the power dividing phaser can be suitable for a four-arm helical antenna at different frequencies.

The invention belongs to a micro electro mechanical (MEMS) processing field and relates to a monolithic embedded integrated silicon acceleration and pressure composite sensor. The objective of the invention is to provide the monolithic embedded integrated silicon acceleration and pressure composite sensor and a typical processing method for manufacturing the sensor. The composite sensor is of an integrated structure. An accelerometer includes a mass block-elastic diaphragm structure with a force sensitive resistor; a pressure gauge includes a pressure sensitive diaphragm with a force sensitive resistor and a sealed prefabricated cavity. The method includes the following steps of: a stress concentration structure processing step which is optional; a sensitive resistor processing step; a metal lead layer processing step; and accelerometer mass block-elastic diaphragm structure processing step. According to the monolithic embedded integrated silicon acceleration and pressure composite sensor of the invention, the accelerometer and the pressure gauge are designed in the same area, and therefore, the area of a chip can be saved, and high sensitivity can be realized when size is small. The sensor fabricated through adopting the method has functions of a pressure gauge and an accelerometer.

The invention discloses a highly automatic plate-overturning and plate-picking production line for producing large-size decorative plates. The highly automatic plate-overturning and plate-picking production line comprises a material mixing machine set, a material distribution mechanism, a kiln, a kiln tail fixed roller table, a kiln furniture, a plate-picking mechanism, a deviation-correcting mechanism and an overturning mechanism, wherein a belt conveyor is disposed between the material mixing unit and the material distribution mechanism; an inlet and an outlet of a material distribution machine position of the material distribution mechanism are respectively equipped with a deviation-correcting roller table and a receiving roller table; the other end of the receiving roller table is connected with a conveying roller table in a matching manner; a kiln inlet and a kiln outlet are respectively equipped with a kiln-incoming roller table and a kiln-outgoing roller table; shuttling roller tables are disposed between the kiln-incoming roller table and the conveying roller table and are used for conveying in a matching manner; the kiln-outgoing roller table is equipped with the shuttling roller tables and the kiln tail fixed roller table which are used for conveying in a matching manner; the kiln tail fixed roller table is sequentially matched with the plate-picking mechanism and the deviation-correcting mechanism for conveying along the movement direction of rollers; and the overturning mechanism and the shuttling roller tables are also disposed between the kiln tail fixed roller table and the deviation-correcting roller table.

The invention relates to a thin film transistor, a manufacturing method thereof and a corresponding device which are used for solving the problem that in a thin film transistor in the prior art, the long channel length limits application of a high resolution display panel. The thin film transistor comprises an active layer, a source, a drain, a first grid and a second grid, wherein one end of the active layer is provided with the active layer is provided with a conductive doping area; the source and the drain are arranged below and above one end of the active layer far away from the doping area respectively; and the first grid and the second grid are arranged below and above the active layer respectively and insulated from the active layer. The thin film transistor comprises the two grids which are distributed on the upper surface and the lower surface of the active layer respectively. Due to the fact that channels only form on the surface of the active layer, the upper layer channel and the lower layer channel can be formed on the upper surface and the lower surface of the active layer in work, the upper channel and the lower channel are connected through the conductive doping area at one end of the active layer, the length of the channels is the sum of the lengths of the channels on the upper surface and the lower surface, and the occupied area is saved better when the same channel length of the current structure is required.

The invention provides an efuse array, an efuse device and an efuse blowing method. The efuse array comprises a plurality of word lines, at least one bit line, a plurality of cells, a plurality of first selection devices, and at least one second selection device. The word lines are interlaced with the bit line. The cells are disposed in an array, and each corresponds to one set of the interlaced word line and bit line. Each first selection device is coupled to one of the word lines, and the second selection device is coupled to the bit line. The invention is capable of reducing the sensing circuits needed for blowing the cells, and reducing the occupied area of the efuse array.

The invention discloses a thin film transistor array substrate. The TFT array substrate comprises a gate metal layer, a gate insulating layer, a semiconductor layer, a source/drain metal layer, a planar layer, a first protection layer, a first electrode layer, a second protection layer and a second electrode layer, wherein the first electrode layer comprises pixel electrodes, the second electrode layer comprises public electrodes, communicating holes are formed in the planar layer, and the pixel electrodes make contact with the drain metal layer through the communicating holes. The invention further provides a display panel and a manufacturing method of the display panel. According to the manufacturing method, etching is performed on the first protection layer with the planar layer as a light shielding cover to form the communicating holes penetrating through the first protection layer and the planar layer so that the pixel electrodes can make contact with the drain metal layer through the communicating holes, the occupied area of the communicating holes is reduced, and thus the requirement for a high aperture rate can be met; besides, the communicating holes are only formed in the process of one light cover, and thus the manufacturing cost and the complexity of the technology are reduced.

The present invention provides a non-feedback interpolator for compensating dynamic filter, the six-order interpolation and the bilinearity interpolation share same hardware circuit, and process brightness and color interpolation to an image block according to one interpolation operating position, including a horizontal filter, a first vertical filtering unit, a second vertical filtering unit, a third vertical filtering unit, a first multiplexer and a bilinearity filter, wherein, the delay-frequency of different filtering calculus are balanced by a selector and a bypass path in each vertical filtering unit. This interpolator can achieve interpolation calculus of integrated six-order filter and bilinearity filter to improve efficient and saving area.