34630 results about "Insulation layer" patented technology

According to the invention, a finger-operated switch for activating and operating an ultrasonic surgical handpiece is provided. The power output of the surgical handpiece is responsive and proportional to the pressure applied to the finger-operated switch. The finger-operated switch includes, but not limited to, force sensitive resistors whose resistance is proportional to the force applied by the finger of the human operator of the surgical handpiece, force sensitive capacitors whose capacitance is proportional to the pressure, deflection or compression of the insulation layer between two electrodes or is proportional to the spacing between the two conductive layers, strain gauges mounted underneath or integral to the housing of the surgical handpiece such that the pressure applied thereto results in an output change in the strain gauges, magnets or ferromagnets encased or embedded in an elastomer with a sensor inside the surgical handpiece that detects the field strength of the magnet and monitors changes relative to the force applied to the handpiece housing, and piezo film or piezo ceramic whose charge or voltage is proportional to the force applied.

The invention relates to a preparation method and an application of multistage-spreading heat-dissipation fire-proof heat-insulation composite fabric. The multistage-spreading heat-dissipation fire-proof heat-insulation composite fabric is formed by successively arranging and laminating a metal foil reflection layer, a phase change temperature limitation layer, an interval composite membrane heat-insulation layer and a flame-retardant comfortable layer, wherein the metal foil reflection layer has high reflectivity and an enhanced heat-dissipation function; the phase change temperature limitation layer has functions of high energy consumption absorption and evenly-distributed heat conduction; the interval composite membrane heat-insulation layer has the functions of reflection insulation and even distribution of heat; and the flame-retardant comfortable layer has the functions of low-contact heat conduction, heat insulation and comfort. When the front side of the multistage-spreading heat-dissipation fire-proof heat-insulation composite fabric is under the action of open fire and strong heat flow environment, the back side of the multistage-spreading heat-dissipation fire-proof heat-insulation composite fabric can be kept below 50DEG C which is near the safe temperature state of the human skin, and the integral structural form and the mechanical property are stable. The natural thickness of the composite fabric is 5-15mm, the compression thickness of the composite fabric is 3-8mm, and the square meter quality of the composite fabric is 400-1500g / m<2>. The composite fabric is fire-proof heat-insulation material which is totally sealed, stuck and sewn and can be used for individual protection and environment heat insulation in special high-temperature occasions, such as fire control, military, exploration, safe escape and industry and the like.

Exemplary embodiments of the present invention provide a wafer-level light emitting diode (LED) package and a method of fabricating the same. The LED package includes a semiconductor stack including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; a plurality of contact holes arranged in the second conductive type semiconductor layer and the active layer, the contact holes exposing the first conductive type semiconductor layer; a first bump arranged on a first side of the semiconductor stack, the first bump being electrically connected to the first conductive type semiconductor layer via the plurality of contact holes; a second bump arranged on the first side of the semiconductor stack, the second bump being electrically connected to the second conductive type semiconductor layer; and a protective insulation layer covering a sidewall of the semiconductor stack.

According to some embodiments, a fin type active region is formed under an exposure state of sidewalls on a semiconductor substrate. A gate insulation layer is formed on an upper part of the active region and on the sidewalls, and a device isolation film surrounds the active region to an upper height of the active region. The sidewalls are partially exposed by an opening part formed on the device isolation film. The opening part is filled with a conductive layer that partially covers the upper part of the active region, forming a gate electrode. Source and drain regions are on a portion of the active region where the gate electrode is not. The gate electrode may be easily separated and problems causable by etch by-product can be substantially reduced, and a leakage current of channel region and an electric field concentration onto an edge portion can be prevented.

A method for fabricating magnetic side shields for an MR sensor of a magnetic head. Following the deposition of MR sensor layers, a first DLC layer is deposited. Milling mask layers are then deposited, and outer portions of the milling mask layers are removed such that a remaining central portion of the milling mask layers is formed having straight sidewalls and no undercuts. Outer portions of the sensor layers are then removed such that a relatively thick remaining central portion of the milling mask resides above the remaining sensor layers. A thin electrical insulation layer is deposited, followed by the deposition of magnetic side shields. A second DLC layer is deposited and the remaining mask layers are then removed utilizing a chemical mechanical polishing (CMP) liftoff step. Thereafter, the first DLC layer and the second DLC layer are removed and a second magnetic shield layer is then fabricated thereabove.

An battery-powered electrosurgical instrument includes a blade having a conductor edge portion and insulation layer with geometric shapes and composition that concentrate electrosurgical energy and reduce or eliminate the production of smoke and eschar and reduce tissue damage, thereby providing more efficient application of electrosurgical energy. The more efficient use of electrosurgical energy permits configuring the system to be battery-powered. The system may be portable or configured as a battery-backup powered system.

To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

A relaying pad is formed in a predetermined portion in an insulation layer of the single-crystal thin film device, in a region where the single-crystal thin film device is formed. The relaying pad is for providing connection wiring through the insulator substrate. With this configuration it is possible to prevent an increase in an aspect ratio of a contact hole formed in an insulation layer in a region in which a transferred device is formed, the semiconductor device including a substrate on which the transferred device and a deposited device coexist.

In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.

A nonvolatile memory device includes a plurality of interlayer dielectric layers and conductive layers for gate electrodes alternately stacked over a substrate, a channel trench passing through the interlayer dielectric layers and the conductive layers and exposing the substrate, a charge blocking layer and a charge trap or charge storage layer formed on sidewalls of the trench, a coupling prevention layer formed at the surface of the charge trap or charge storage layer, and a tunnel insulation layer formed over the coupling prevention layer.

A field effect transistor which comprises a semiconductor substrate having a source region and a drain region separated by a channel region; a conductive floating gate formed over a first portion of the channel region adjacent to the doped source region and recessed into the semiconductor substrate; and being separated from the first portion of the channel region by a first insulation layer; and a conductive control gate formed substantially over but electrically isolated from the floating gate and formed over the entire channel region; along with a method for fabricating such is provided.

A method of forming a fin field effect transistor on a semiconductor substrate includes forming a vertical fin protruding from the substrate. A buffer oxide liner is formed on a top surface and on sidewalls of the fin. A trench is then formed on the substrate, where at least a portion of the fin protrudes from a bottom surface of the trench. The trench may be formed by forming a dummy gate on at least a portion of the fin, forming an insulation layer on the fin surrounding the dummy gate, and then removing the dummy gate to expose the at least a portion of the fin, such that the trench is surrounded by the insulation layer. The buffer oxide liner is then removed from the protruding portion of the fin, and a gate is formed in the trench on the protruding portion of the fin.

An LED array package structure having a silicon substrate is disclosed. The LED array package structure comprises a silicon substrate having a plurality of cup-structures thereon, a reflective layer disposed on the silicon substrate, a transparent insulation layer disposed on the reflective layer, a conductive layer disposed on the transparent insulation layer and a plurality of LEDs disposed respectively on the conductive layer in each cup-structures.

Each of the memory strings includes: a first columnar semiconductor layer extending in a vertical direction to a substrate; a plurality of first conductive layers formed to sandwich an insulation layer with a charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction. Respective ends of the plurality of first conductive layers in the first direction are formed in a stepwise manner in relation to each other, entirety of the plurality of the second conductive layers are formed in an area immediately above the top layer of the first conductive layers, and the plurality of first conductive layers and the plurality of second conductive layers are covered with a protection insulation layer that is formed continuously with the plurality of first conductive layers and the second conductive layers.