626results about How to "Avoid shorting" patented technology

Conventional electrochromic devices frequently suffer from poor reliability and poor performance. Improvements are made using entirely solid and inorganic materials. Electrochromic devices are fabricated by forming an ion conducting electronically insulating interfacial region that serves as an IC layer. In some methods, the interfacial region is formed after formation of an electrochromic and a counter electrode layer. The interfacial region contains an ion conducting electronically insulating material along with components of the electrochromic and/or the counter electrode layer. Materials and microstructure of the electrochromic devices provide improvements in performance and reliability over conventional devices.

A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as an etch mask, to form a fin only on a gate formation region, the second mask pattern to expose only a gate electrode formation region. A gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layer is formed. Source and drain regions are formed on the remaining portion of the active region where the gate electrode was not formed. Gate electrode separation becomes adequate and manufacturing costs can be reduced.

A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.

Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The conductive gate structure forms gates in device trenches in an active device region and forms a gate bus in a gate bus trench. The gate bus trench that connects to the device trenches can be wide to facilitate forming a gate contact to the gate bus, while the device trenches can be narrow to maximize device density. CMP process can be used to planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

A photovoltaic device includes a substrate having at least two surfaces and a multilayered film disposed on at least a portion of at least one surface of the substrate. Elongated nanostructures are disposed on the multilayered film. The device incorporates a top layer of the multilayered film contacting the elongated nanostructures that is a tunnel junction. The device has at least one layer deposited over the elongated nanostructures defining a portion of a photoactive junction. A solar panel includes at least one photovoltaic device. The solar panel isolates each such devices from its surrounding atmospheric environment and permits the generation of electrical power.

In order to avoid an edge-effect (increased electrical field line density at the edges of electrolytically to be processed work pieces) during the electrolytic processing of work pieces 3.x in a conveyorized system, the electric currents originating from various counter electrodes 5.x in the plant are set to values in function of the electrolytically to be processed surface areas of the work pieces 3.x as far as they are located directly opposite the respective ones of the various counter electrodes 5.x. Moreover, the distance between the work pieces 3.x and the counter electrodes 5.x is chosen to be 50 mm maximum. Means 19 for individually controlling and adjusting every single current supply unit 15.x of the counter electrodes 5.x are provided for this purpose. Said means 19 are configured in such a manner that the respective electric currents originating from the various counter electrodes 5.x are settable to values in function of the electrolytically to be processed surface areas of the work pieces 3.x, as far as they are located directly opposite the respective various counter electrodes 5.x.

Methods, systems, and apparatuses for extracting non-polar lipids from microalgae are achieved using a lipid extraction device having an anode and a cathode that forms a channel and defines a fluid flow path through which an aqueous slurry is passed. An electromotive force is applied across the channel at a gap distance in a range from 0.5 mm to 200 mm to cause the non-polar lipids to be released from the algae cells. The non-polar lipids can be extracted at a high throughput rate and with low concentrations of polar lipids such as phospholipids and chlorophyll.

The invention is directed to unique high-surface area BEOL capacitor structures with high-k dielectric layers and methods for fabricating the same. These high-surface area BEOL capacitor structures may be used in analog and mixed signal applications. The capacitor is formed within a trench with pedestals within the trench to provide additional surface area. The top and bottom electrodes are created using damascene integration scheme. The dielectric layer is created as a multilayer dielectric film comprising for instance Al2O3, Al2O3/Ta2O5, Al2O3/Ta2O5/Al2O3 and the like. The dielectric layer may be deposited by methods like atomic layer deposition or chemical vapor deposition. The dielectric layer used in the capacitor may also be produced by anodic oxidation of a metallic precursor to yield a high dielectric constant oxide layer.

A composite hard mask is disclosed that enables sub-100 nm sized MTJ cells to be formed for advanced devices such as spin torque MRAMs. The hard mask has a lower non-magnetic metallic layer such as Ru to magnetically isolate an overlying middle metallic spacer such as MnPt from an underlying free layer. The middle metallic spacer provides a height margin during subsequent processing to avoid shorting between a bit line and the MTJ cell in the final device. An upper conductive layer may be made of Ta and is thin enough to allow a MTJ pattern in a thin overlying photoresist layer to be transferred through the Ta during a fluorocarbon etch without consuming all of the photoresist. The MTJ pattern is transferred through the remaining hard mask layers and underlying MTJ stack of layers with a second etch step using a C, H, and O etch gas composition.

Provided are an organic light emitting display device and a method for manufacturing the same. A color filter is disposed on a substrate. An overcoating layer is disposed on the color filter and includes a plurality of protrusions or a plurality of recesses. The plurality of protrusions and the plurality of recesses are disposed on the color filter to be overlapped with the color filter. A buffer layer for reducing step difference is disposed on the overcoating layer. The buffer layer has a higher refractive index than the overcoating layer and reduces a step difference caused by the plurality of protrusions and the plurality of recesses. An organic light emitting element including an anode, an organic light emitting layer, and a cathode is disposed on the buffer layer. Since the buffer layer has a higher refractive index than the overcoating layer, light extraction efficiency can be increased.

An apparatus and method for sensor architecture based on bulk machining of Silicon-On-Oxide wafers and fusion bonding that provides a symmetric, nearly all-silicon, hermetically sealed MEMS device having a sensor mechanism formed in an active semiconductor layer, and opposing silicon cover plates each having active layers bonded to opposite faces of the sensor mechanism. The mechanism is structured with sensor mechanical features structurally supported by at least one mechanism anchor. The active layers of the cover plates each include interior features structured to cooperate with the sensor mechanical features and an anchor structured to cooperate with the mechanism anchor. A handle layer of each cover plate includes a pit extending there through in alignment with the cover plate anchor. An unbroken rim of dielectric material forms a seal between the cover plate anchor and the pit and exposes an external surface of the cover plate anchor.

It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed.

Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. By applying a high voltage to an OTP element coupled to the P-terminal of a diode and switching the N-terminal of a diode to a low voltage for suitable duration of time, a current flows through the OTP element may change the resistance state. On the polysilicon diode, the spacing and doping level of a gap between the P- and N-implants can be controlled for different breakdown voltages and leakage currents. The Silicide Block Layer (SBL) can be used to block silicide formation on the top of polysilicon to prevent shorting. If the OTP element is a polysilicon electrical fuse, the fuse element can be merged with the polysilicon diode in one piece to save area.

A multilayered high performance capacitor formed of two or more conductors with a dielectric layer and one or more a dielectric-conductor interface layer sandwiched in between the conductors. The capacitor may be fabricated using many thin layers, at the nano level, providing a nanocapacitor. The capacitor may employ an interleaved structured where numerous conductor layers are interleaved with other conductor layers. The dielectric layers may be multilayered or a single layer and may consist of materials with high dielectric constants ranging from 800 to over 1 million, including materials in the perovskite-oxide family. The capacitor can be shaped, sized and the appropriate materials selected to obtain breakdown voltages within the range of 0.1 to over 11 MV/cm and to obtain specific energies and energy densities equivalent to or exceeding the power characteristics of known capacitors, fuel cells, and batteries. The nanocapacitor may be combined with other nanocapacitors to form stacks, packs, or grids of cells where the cells may be connected in series, parallel or both to provide increased energy or power characteristics