1516results about "Conductive pattern reinforcement" patented technology

The invention is an optical reader having a plurality of image sensors. Each image sensor of a plural image sensor optical reader can be disposed on an imaging module that can include a light source. In one embodiment, a frame of image data captured via actuation of an image sensor of a first imaging module and actuation of illumination of a second imaging module is subjected to decoding. The various modules of a multiple imaging module reader can be adapted to have different best focus positions so that a field depth of the reader is improved.

Embodiments of the present invention relate generally to solder bump formation and semiconductor device assemblies. One embodiment related to a method for forming a bump structure includes providing a semiconductor device (10) having a bond pad (12), and forming a first masking layer (20) overlying the bond pad (12). The first masking layer (20) is patterned to form a first opening (22) overlying at least a portion of the bond pad (12). A second masking layer (40) is formed overlying the first masking layer (20), and the second masking layer (40) is patterned to form a second opening (42) overlying at least a portion of the first opening (22). The method further includes forming a stud (30) at least within the first opening (22) and a solder bump (60) at least within the second opening (42).

PCT No. PCT/EP96/05140 Sec. 371 Date Apr. 23, 1998 Sec. 102(e) Date Apr. 23, 1998 PCT Filed Nov. 21, 1996 PCT Pub. No. WO97/19206 PCT Pub. Date May 29, 1997The invention relates to a method for the electrolytic deposition of metal coatings, in particular of copper coatings with certain physical-mechanical and optical properties and uniform coating thickness. According to known methods using soluble anodes and applying direct current, only uneven metal distribution can be attained on complex shaped workpieces. By using a pulse current or pulse voltage method, the problem of the coatings being of varying thickness at various places on the workpiece surfaces can indeed be reduced. However, the further problem of the geometric ratios being changed continuously during the depositing process by dissolving of the anodes is not resolved thus. This can be avoided by using insoluble anodes. In order to guarantee sufficient stability of the anodes and a bright coating even at those points on the workpiece surfaces, onto which the metal is deposited with high current density, it is essential to add compounds of an electrochemically reversible redox system to the depositing solution.

A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material.

The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing. The present invention is related to a process for manufacturing multilayer printed circuit boards which comprises disposing an interlayer resin insulating layer on a substrate formed with a conductor circuit, creating openings for formation of via holes in said interlayer resin insulating layer, forming an electroless plated metal layer on said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to provide a conductor circuit and via holes, wherein the electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

To provide a suspension board with circuit that enables its terminals to be bonded to the other terminals with sufficient strength with simple structure, to ensure sufficient bonding reliability, the suspension board with circuit 11 includes a suspension board 12, a base layer 13 formed on the suspension board 12, and a conductive layer 14 formed on the base layer 13 and a cover layer 18 with which the conductive layer 14 is covered, wherein external connection terminals 17 to be bonded to terminals 28 of a read/write board 29 are formed without the suspension board 12 and/or the base layer 13 being formed.

An optical reader in one embodiment can include a substrate defining an opening and solder pads coupled to the substrate proximate the opening. A laser diode including first, second, and third electrical leads can also be coupled to the substrate. First, second and third solder pads can be provided on the substrate and the first, second, and third electrical leads of the laser diode can be coupled to the first, second, and third solder pads. An optical reader in another embodiment can include a substrate having a first surface and a second surface. A laser diode assembly configured to emit a laser beam can be coupled to the first surface and an illumination assembly that can include light emitting diodes can be coupled to the second surface.

An electroplating apparatus prevents anode-mediated degradation of electrolyte additives by creating a mechanism for maintaining separate anolyte and catholyte and preventing mixing thereof within a plating chamber. The separation is accomplished by interposing a porous chemical transport barrier between the anode and cathode. The transport barrier limits the chemical transport (via diffusion and/or convection) of all species but allows migration of ionic species (and hence passage of current) during application of sufficiently large electric fields within electrolyte.

The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

A method for deplating defective capacitors comprising forming a plurality of capacitors on a semiconductor substrate, forming a plurality of metal contacts on the plurality of capacitors, and depositing a layer of photoresist on the semiconductor substrate. The photoresist layer is patterned so that the plurality of metal contacts are exposed, which are then contacted with an electrically conductive solution. The metal contacts, which are disposed over defective capacitors, are subsequently deplated. A method for forming a multi-chip module comprising forming a thin-film polymeric interconnect structure having a pair of sides, one of which is disposed on a silicon substrate having active or passive devices and the other of which has a computer chip mounted thereon. A multi-chip module formed by the method.

The impact strength resistance of a solder joint portion of a semiconductor device is improved. The semiconductor device has a joint structure wherein a jointing layer which does not contain sulfur substantially is arranged between an underlying conductive layer and a lead-free solder layer and further between the jointing layer and the lead-free solder layer is formed an alloy layer comprising elements of these layers.

A reinforced solder bump connector structure is formed between a contact pad arranged on a semiconductor chip and a ball pad arranged on a mounting substrate. The semiconductor chip includes at least one reinforcing protrusion extending upwardly from a surface of an intermediate layer. The mounting substrate includes at least one reinforcing protrusion extending upwardly from a ball pad, the protrusions from both the chip and the substrate being embedded within the solder bump connector. In some configurations, the reinforcing protrusion from the contact pad and the ball pad are sized and arranged to have overlapping under portions. These overlapping portions may assume a wide variety of configurations that allow the protrusions to overlap without contacting each other including pin arrays and combinations of surrounding and surrounded elements. In each configuration, the reinforcing protrusions will tend to suppress crack formation and/or crack propagation thereby improving reliability.

In order to avoid an edge-effect (increased electrical field line density at the edges of electrolytically to be processed work pieces) during the electrolytic processing of work pieces 3.x in a conveyorized system, the electric currents originating from various counter electrodes 5.x in the plant are set to values in function of the electrolytically to be processed surface areas of the work pieces 3.x as far as they are located directly opposite the respective ones of the various counter electrodes 5.x. Moreover, the distance between the work pieces 3.x and the counter electrodes 5.x is chosen to be 50 mm maximum. Means 19 for individually controlling and adjusting every single current supply unit 15.x of the counter electrodes 5.x are provided for this purpose. Said means 19 are configured in such a manner that the respective electric currents originating from the various counter electrodes 5.x are settable to values in function of the electrolytically to be processed surface areas of the work pieces 3.x, as far as they are located directly opposite the respective various counter electrodes 5.x.

Methods for fabricating a conductive contact (through-via) through a full thickness of a substrate such as a semiconductor wafer or interposer substrate, and semiconductor devices and systems incorporating the conductive through-via are provided. The conductive contact is fabricated by applying a metal layer onto a backside of a substrate, forming a through-hole through the substrate and the metal layer, sealing the hole in the metal layer by an electroless plating process, and filling the hole by an electroplating or an electroless plating process.

A producing method of a suspension board with circuit that can permit a terminal portion to be formed by electrolysis plating without exposing a conductor layer to outside and also can reduce the number of processes, and the suspension board with circuit produced by the same producing method. After an insulating base layer 3 is formed on a suspension board 2 in a specific pattern in which a second opening 12 is formed, a thin metal film 13 is formed on an entire surface of the insulating base layer 3 and on a surface of the suspension board 2 including the second opening 12 exposed from the insulating base layer 3.Then, a conductor layer 4 is formed in the form of a wired circuit pattern on the thin metal film 13. Thereafter, the insulating cover layer 10 is formed in such a manner that a pad opening 11 is formed in the insulating cover layer 10 and then a pad portion 16 is formed in the pad opening 11 using the suspension board 2 as a lead portion of the electrolysis plating. Thereafter, a first opening 25 larger than the second opening 12 is formed in the suspension board 2 at a portion thereof corresponding to the second opening 12.