6422 results about "Etching" patented technology

The invention discloses a printed circuit board defect detection system. The image acquisition module is used for acquiring a multispectral image of a printed circuit board to be detected, and the image preprocessing module is used for denoising, enhancing and normalizing the acquired image. The feature extraction module extracts geometric and spectral information from the preprocessed image, including the shape and layout structure of the circuit. The deep learning module processes the extracted preliminary geometric and spectral information, and the basic network sub-module performs feature extraction through a pre-trained convolutional neural network to generate high-level features. And the self-adaptive adjustment sub-module carries out fine adjustment on the high-level features through defect sample data with labels, and generates specific features for identifying and classifying various defects of the printed circuit board. The defect identification and classification sub-module combines high-level features and specific features to realize accurate detection of short circuit, open circuit, insufficient etching, welding defects and the like. And the visualization module is used for marking the position and the type of the defect and generating a detection report.

The invention discloses a continuous zooming laser interference end point detection system, which is used for semiconductor etching and thin film process end point detection, and comprises an illumination module, a laser interference module and an imaging module, the laser interference module comprises a laser, a beam splitter, a beam splitting cube, a lens and a detector, a laser beam emitted by the laser passes through the beam splitter, the beam splitting cube and the lens and then is focused to a to-be-detected area on the surface of a wafer, and the surface of the wafer reflects the laser to the detector for detection; the focal length of the lens is continuously adjustable; the illumination module comprises a light source which is arranged on one side of the lens, and an illumination light beam emitted by the light source is used for illuminating a to-be-detected area on the surface of the wafer; and the imaging module comprises a camera which is arranged on one side of the lens and is used for recording and outputting image information of a to-be-detected area on the surface of the wafer. According to the invention, through continuous zooming and large numerical aperture of the lens, high-definition imaging and etching of a long working distance and accurate detection of a thin film process end point are realized.

The invention provides a high-reliability planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed, etching and ion implantation are carried out, and a current sharing layer, a body region, a P-type well region and an N-type source region are formed; forming a barrier layer again, etching and depositing to form an insulating medium layer; a barrier layer is formed again, and etching and deposition are carried out to form a gate dielectric layer; the preparation method comprises the following steps: forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, removing the barrier layer, and completing the preparation. The gate reliability of the device can be effectively improved, and the follow current loss and reverse recovery speed of a body diode can be effectively improved.

The invention discloses an MEMS device architecture, which comprises a cap layer, a device layer and a substrate layer, the cap layer is bonded with the device layer, the bonded whole is bonded with the substrate layer, the cap layer is manufactured based on a first silicon substrate, the bottom of the cap layer is provided with a cavity structure, and the cap layer is internally provided with a high-deep groove structure. A silicon dioxide film is arranged on the groove wall of the high-deep groove structure, polycrystalline silicon is deposited and filled in the high-deep groove structure, and a silicon dioxide layer is arranged on the upper surface of the first silicon substrate; the device layer is manufactured based on an SOI wafer and comprises a first silicon structure layer composed of top layer silicon, a buried oxide layer and a second silicon structure layer composed of back substrate silicon. The substrate layer comprises a second silicon substrate, a bottom layer cavity is formed in the top face of the second silicon substrate, and exhaust holes are formed in the bottom face of the second silicon substrate. According to the method, deep groove etching, polycrystalline silicon groove filling and bonding technologies are combined, advanced materials such as the SOI wafer and the polyimide layer are utilized, and excellent signal isolation and flexibility of various MEMS IMU applications are achieved.

The invention discloses a desulfurizer and a desulfurization method using the desulfurizer, belongs to the technical field of desulfurizer processing, and aims to solve the problems that in the gas desulfurization engineering of a zinc oxide type desulfurizer in the prior art, gas molecules are not easy to diffuse and adsorb on particle surfaces, and the desulfurization efficiency is low. The sulfur capacity, the specific surface area and the desulfurization efficiency of the desulfurizer need to be further improved. The desulfurizer is prepared by mixing molten salt etching modified kaolin, loaded activated carbon and sol according to the weight ratio of (8-9): (13-15): 60 into a mixed glue solution and then emulsifying and granulating, the kaolin is modified through molten salt etching, the activated carbon loaded with zinc and magnesium metal oxides and nitrides is prepared and used as a base material, silica sol is used as an auxiliary agent, and the desulfurizer is prepared. Through emulsification and granulation, the sulfur capacity and the specific surface area of the desulfurizer are effectively improved, and the desulfurization efficiency of using the desulfurizer for desulfurization is also improved.

The invention discloses a modified graphite felt electrode for an all-vanadium redox flow battery and a preparation method of the modified graphite felt electrode, and belongs to the technical field of redox flow battery electrode materials. The preparation method comprises the following steps: graphite felt electrochemical oxidation etching treatment; self-assembling a conductive layer on the oxidized and etched graphite felt to obtain the graphite felt attached with the conductive layer; and loading a metal and nitrogen-doped carbon (M and NC) nano catalyst layer on the graphite felt attached with the conductive layer to obtain the modified graphite felt electrode. Various properties of the graphite felt are comprehensively improved through matrix treatment, structure change and load catalysis, mild electrochemical oxidation etching is adopted, a carbon fiber structure is protected, a self-assembled net-shaped conductive layer forms a stable conductive channel, the specific surface area is remarkably increased, a nitrogen-doped carbon shell is adopted to wrap metal nanodots to form an M-NC catalytic layer, and the specific surface area is remarkably increased. The catalyst layer is not easy to dissolve out, the capacity fading rate is obviously improved, the loading capacity of the catalyst layer on the reticular structure conducting layer with a larger specific surface area is larger, and meanwhile, the process is simple and low in cost.

The invention discloses an in-situ whisker reinforced aerogel heat insulation composite material and a preparation method thereof, and the aerogel heat insulation composite material with high specific strength is prepared through fiber etching, whisker modification of fibers, sol preparation and dipping, aging, supercritical drying and high-temperature sintering. Aluminum oxide-silicon oxide composite aerogel is used for modifying ceramic fibers, whiskers are generated on the surfaces of the fibers in situ, the interface bonding force between the aerogel and the fibers is increased, and the mechanical property of the aerogel heat insulation composite material is remarkably improved.

The invention relates to the technical field of PCB etching, in particular to a PCB etching device and method, and the device comprises a box body which is used for containing an etching solution; the conveying mechanism is used for vertically conveying the PCBs; the spraying mechanism is used for spraying etching liquid to the two sides of the PCB; the dehumidification mechanism is used for erasing residual etching liquid on the PCB; the reciprocating mechanism is used for driving the spraying mechanism to do reciprocating motion; the conveying mechanism comprises two guide wheel devices which are symmetrical up and down, and one guide wheel device is connected with a driving device. According to the PCB etching device and etching method, the PCB can be conveyed in a vertical state by arranging the conveying mechanism, so that the contact time of the etching liquid and the two sides of the PCB is the same, the etching effects of the two sides of the PCB are more synchronous, the etching liquid can be sprayed to the two sides of the PCB at the same time through the spraying mechanism, the PCB can receive the etching liquid at the same time, and the etching efficiency of the PCB is improved. And the etching synchronism of the two sides of the PCB is ensured, so that the etching efficiency and quality are improved.

The invention relates to a simplified gas delivery system for atomic layer etching. According to the system, the overall cost is reduced by omitting the requirements of a gas tank and a pressure gauge. A preset mass flow controller (MFC) and a three-way valve can accurately control the gas flow in the surface modification step and the sputtering step of the ALE process. By means of the self-limiting property of the ALE process, the system does not need to maintain the steady-state pressure of the chamber, and the efficiency can be improved only by controlling the volume of the conveyed gas.

The invention provides a method for adjusting the height of a grid electrode and a semiconductor structure, and belongs to the field of semiconductors. The method of adjusting gate height includes providing a semiconductor substrate. And etching back the hard mask layer in the NMOS region to reduce the thickness of the hard mask layer in the NMOS region. And after back etching, gate structures are respectively formed in the PMOS region and the NMOS region. And filling a dielectric layer, wherein the dielectric layer covers the gate structure of the NMOS region. And patterning a groove, etching the groove in the PMOS region, and when the groove is etched in the PMOS region, the thickness lost by the hard mask layer in the PMOS region is basically equal to the thickness lost by etching the hard mask layer in the NMOS region. By depositing the hard mask layer and etching the hard mask layer, the thickness of the hard mask layer in the PMOS region is basically equal to that of the hard mask layer in the NMOS region, so that the height of the formed grid electrode in the PMOS region is basically equal to that of the grid electrode in the NMOS region, and the performance of the device can be improved.

The invention relates to a method and device for high-precision laser selective etching of a curved-surface multilayer film system, and the method comprises the following steps: obtaining a battery image of the surface of a curved-surface perovskite battery through a visual imaging system, and transmitting the battery image to a main control unit; the main control unit locates the position of the P1 line; the distance measuring unit identifies the height between the laser scribing head and the surface of the curved-surface perovskite battery; the moving module drives the laser scribing head to etch the P1 line on the surface of the curved-surface perovskite cell to obtain a P1 scribed line; the main control unit obtains a reference positioning line of the P1 scribed line; an offset value is added on the battery image according to the reference positioning line of the P1 scribed line, so that the P2 line and the P3 line are positioned; and the moving module drives the laser scribing head to etch the P3 line on the surface of the curved-surface perovskite cell to obtain a P3 scribed line. The distance measuring unit can dynamically adapt to the real-time motion state of the workpiece, and the problem of focus deviation is avoided.

The invention discloses a structure and a manufacturing method of a circuit board with interconnection of any layers of through holes, two ends of an isolation strip which needs to be insulated between layers at the through holes of the circuit board are respectively provided with a concave etching position, the concave etching positions serve as isolation rings, and the concave etching positions are formed after an isolation disc arranged on an inner-layer core plate is etched in a concave mode; the manufacturing method comprises the following steps that a circuit board is provided, a drilling position is arranged on the circuit board, and the drilling position is a position needing to be drilled in subsequent processing; the two ends of the interlayer isolation strip needing insulation at the drilling position of the circuit board are each provided with an isolation disc with the outer diameter larger than the outer diameter of the drilling position. A through hole is drilled in the position, corresponding to the drilling position, of the circuit board, so that the isolation disc on the inner layer is exposed in the through hole, then the isolation disc in the hole is removed through concave etching, and a concave etching position serving as an isolation ring is formed; and after the circuit board is subjected to copper deposition and electroplating, a structure of interconnection of any layers of the through holes is formed. According to the method, a plurality of signals can be transmitted in the same hole, and the purpose of interconnection of any layer in the through hole can be achieved.

Tin oxide films are used to create air gaps during semiconductor substrate processing. Tin oxide films, disposed between exposed layers of other materials, such as SiO2 and SiN can be selectively etched using a plasma formed in an H2-containing process gas. The etching creates a recessed feature in place of the tin oxide between the surrounding materials. A third material, such as SiO2 is deposited over the resulting recessed feature without fully filling the recessed feature, forming an air gap. A method for selectively etching tin oxide in a presence of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, or SiCN, includes, in some embodiments, contacting the substrate with a plasma formed in a process gas comprising at least about 50% H2. Etching of tin oxide can be performed without using an external bias at the substrate and is preferably performed at a temperature of less than about 100° C.

The invention provides a manufacturing and processing photoetching method and system of a display panel, and relates to the technical field of photoetching processing. According to the method, the display panel substrate is subjected to cleaning, prime coating and partition division to form an imageable micro-mark covering all exposure partitions, and the thickness and the uniformity are measured after lower-layer supporting glue and upper-layer imaging glue are sequentially formed; carrying out in-situ acquisition and modeling by taking the micro-mark as an imaging object, and generating an exposure correction instruction and an overlapping energy table; performing partition exposure and real-time correction by using a digital micromirror, and completing development to obtain an anti-etching window with a steep side wall; and setting an etching window according to the exposure record and the window quality data, and executing low-damage etching and defect recovery to form stability evaluation data. According to the method, comprehensive improvement of high-precision exposure, pattern consistency and electrical stability is realized.

A manufacturing method of a semiconductor structure and the semiconductor structure, the manufacturing method of the semiconductor structure comprising: providing a substrate comprising a first region and a second region; forming a laminated structure formed by alternately stacking a plurality of first material layers and a plurality of second material layers on the first region; first etching is executed, a groove is formed in one end of the laminated structure, and the second area is exposed out of the bottom of the groove; executing second etching, removing part of the plurality of second material layers through the grooves and keeping the plurality of first material layers arranged at intervals; wherein before the second etching is executed, a protection layer is formed on the surface of the second area, and the protection layer at least extends towards the surface of the first area. According to the method, the semiconductor device with relatively high reliability can be obtained.

The invention provides a high-reliability trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate to form a drain metal layer, and carrying out the epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed on the drift layer, etching and ion implantation are carried out, a first P-type well region, a protruding part, a first low-resistance region, a second low-resistance region and a third low-resistance region are formed, and the low-resistance region comprises the first low-resistance region, the second low-resistance region and the third low-resistance region; a barrier layer is formed again, etching and ion implantation are carried out, and a P-type source region, an N-type source region, a conductive region and a protection region are formed; a barrier layer is formed again, an insulating medium layer is formed through etching and oxidation, and a groove is formed in the insulating medium layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. Through optimization design of the gate structure and the source structure, the purpose of improving the reliability of the device is achieved.

A method for ultraviolet-laser transfer and cleaning of microelectronic devices includes transferring a microelectronic device from a donor substrate to a receiver substrate, and cleaning the microelectronic device after transfer. Prior to transfer, the microelectronic device is coupled to the donor substrate via a sacrificial layer containing gallium. A first ultraviolet laser beam ablates the sacrificial layer to release the microelectronic device from the donor substrate, leaving behind a gallium residue on the newly exposed surface of the microelectronic device. A second ultraviolet laser beam ablates the gallium residue to clean the microelectronic device. The first and second ultraviolet laser beams may be generated by the same ultraviolet laser. As compared to liquid etching, laser ablation of the gallium residue eliminates a wet-chemistry step and may be performed by the same laser apparatus used for transfer. Laser cleaning is particularly advantageous when the receiver substrate is intolerant to liquid etching.

The embodiment of the invention discloses an etching method, an etching device and a solar cell module. The etching method comprises the following steps: controlling a light spot overlapping rate to be smaller than a preset overlapping rate; generating laser with preset performance parameters; shaping the laser into rectangular flat-topped light; and focusing the rectangular flat-topped light into a light spot with a preset size, and etching the perovskite functional layer in the to-be-etched cell according to the light spot overlapping rate. According to the technical scheme provided by the embodiment of the invention, the etching method is set, the perovskite functional layer is etched by adopting point contact, the laser beam adopts rectangular flat-topped light, each pulse independently acts on the film layer, single-pulse etching is performed on the perovskite functional layer in the to-be-etched cell, heat accumulation in an optical pulse overlapping region is avoided, and electrode deposition is more facilitated.

The invention provides a superlattice infrared detector chip manufacturing method, and belongs to the technical field of infrared detector manufacturing. The problem that the product performance or the product yield is low due to the fact that the precision fluctuation of the photoetching technology when the hard mask is removed is not considered in the current hard mask removing scheme is solved; comprising the following steps: forming a hard mask: growing the hard mask with a certain thickness on the surface of a wafer made of a superlattice material; photoetching an upper electrode table top; etching a hard mask: taking the photoresist as a mask, and etching the hard mask by adopting an ICP (Inductively Coupled Plasma) technology to obtain an upper electrode mesa mask pattern; degumming and cleaning an upper electrode table board; photoetching a lower electrode table board: adopting photoresist as a mask of a lower electrode table board area, and manufacturing the lower electrode table board area through a photoetching technology; carrying out ICP etching on the table board; performing wet etching on the table board; degumming and cleaning a lower electrode table board; forming a passivation layer film; opening holes in the passivation layer; manufacturing a gold electrode; the method is applied to preparation of the superlattice infrared detector chip.

The invention relates to the technical field of radio frequency integrated circuits and advanced semiconductor packaging, in particular to a multilayer spiral inductor structure based on an RDL process and a preparation method. The preparation method comprises the steps of seed layer deposition, gradient line width coil formation through photoetching and electroplating, alternate dielectric layer deposition, through hole etching to form vertical interconnection copper columns, air bridge forming through a photoresist sacrificial layer process and silicon nitride passivation packaging. Through fan-shaped topological layout, dielectric material collaborative optimization and three-dimensional interconnection structure design, the self-resonant frequency bandwidth is effectively improved, conductor and dielectric loss is reduced, and miniaturization integration and high reliability of high-frequency inductance elements are achieved.

The embodiment of the invention provides a perovskite solar cell, a preparation method thereof and a perovskite solar cell module. The perovskite solar cell comprises a substrate and a transparent conductive oxide layer, wherein the transparent conductive oxide layer is provided with a plurality of first regions and second regions which are arranged in a staggered manner; a first etching groove is formed in the transparent conductive oxide layer in the first region; the insulating protection layer is positioned in the first region; the first charge transport layer, the perovskite light absorption layer and the second charge transport layer are located in the second region; the second etching groove is positioned in the insulating protection layer; the electrode layer is positioned on the second charge transmission layer and the insulation protection layer and in the second etching groove; and the third etching groove is positioned in the electrode layer of the first region. According to the technical scheme of the invention, the insulation protection layer in the perovskite solar cell can protect the perovskite light absorption layer, reduces the damage of laser scribing to the perovskite light absorption layer, and improves the stability of a perovskite solar cell module.

The invention relates to a rapid gas delivery system and method for atomic layer etching. The system utilizes a compact gas buffer disposed near the gas distribution unit, enabling faster and more efficient delivery of gas to the chamber. The controller manages the gas flow of the gas buffer to maintain an amount of gas within the gas buffer required to perform a single ALE cycle. When one gas buffer delivers gas to the chamber for a partial ALE step, gas is concurrently delivered to the other gas buffer. The configuration not only can improve the efficiency, but also can save components such as a pressure gauge, thereby saving the cost.

Systems and methods are provided for etching molybdenum in a wet ALE process. The methods disclosed herein use a wide variety of techniques and wet etch chemistries to oxidize a molybdenum surface and form a self-limiting, molybdenum oxide passivation layer in a surface modification step of the wet ALE process. For example, the methods use: (a) ultra-violet (UV) photolysis of peroxide oxidizers to create oxidizing radicals, which limit oxidation of the molybdenum surface and provide quasi-self-limiting oxidation behavior, (b) steric hinderance of oxidizers having large reactant molecules to achieve better self-limiting oxidation behavior, and / or (c) ligand-assisted oxidation to change the surface chemistry of the molybdenum oxide passivation layer and ensure self-limiting oxidation behavior. After forming the molybdenum oxide passivation layer using one or more of the oxidation techniques disclosed herein, the passivation layer is selectively removed in a dissolution step of the wet ALE process to etch the molybdenum surface.

The invention provides a production scheduling method of multi-cavity etching equipment and related equipment. The method comprises the following steps: acquiring wafer batches in an etching parallel processing mode, available machine information and an available processing path set of each machine for the wafer batches of each process type; obtaining a process type transfer matrix; according to the available machine information, an etching scheduling task is generated for the wafer batch arriving in the planned period, and the etching scheduling task comprises a first-stage machine scheduling task and a second-stage machine internal cavity scheduling task; in the first stage, a distribution strategy for machine scheduling is created, and in the second stage, a sub-batch fragmentation strategy of each wafer batch in a cavity is created; and when the task execution time reaches the triggering time of any adjustment task, creating a non-processing state instruction of the cavity, and alternately executing the triggered adjustment tasks in sequence. According to the method, a two-stage allocation scheduling production scheduling algorithm is used, and the dual scheduling task of wafer batches on the machine and cavity level is synchronously realized.

The invention discloses a curved circuit three-dimensional printing-oriented base material surface modification and adhesive force enhancement method, which comprises the following steps of: performing surface modification on the surface of an insulating curved surface base material, and integrally plating copper after modification, so that a layer of uniform conductive copper film is formed on the surface of the base material; anti-etching mask ink is selectively jet-printed on the base material, curing is carried out after jet printing is completed until the anti-etching mask ink is completely dried, and an anti-etching film with a conductive pattern is formed on the surface of the insulation curved surface base material; then, the conductive copper film is soaked in etching liquid for selective etching, and the conductive copper film which is not covered with the anti-etching film is gradually dissolved until the original insulating curved surface base material is exposed; and then soaking in an alkaline solution until the anti-etching film with the conductive pattern is completely dissolved and falls off to obtain the insulating curved-surface base material with a clean surface and a complete conductive pattern. According to the method disclosed by the invention, the adhesive force between the conductive material and the insulating curved surface base material is greatly enhanced, and high-precision and high-reliability preparation of the curved surface circuit is realized.

The invention discloses a back surface structure of a TBC battery, a preparation method of the back surface structure, the TBC battery and a preparation method of the TBC battery, and belongs to the technical field of solar batteries. According to the back surface structure of the TBC battery, the first doped polycrystalline silicon layer is provided with the high-concentration doped region and the low-concentration doped region, so that on one hand, good contact between a metal electrode and polycrystalline silicon is ensured, and meanwhile, the battery has relatively low contact resistance and high conversion efficiency. According to the back surface structure of the TBC battery or the preparation method of the TBC battery provided by the invention, on the basis of ensuring that the thickness of the first doped polycrystalline silicon layer is not reduced, by arranging the low-concentration doped region, the adverse effect of laser patterning processing on subsequent wet etching of polycrystalline silicon is reduced, the wet etching effect of the polycrystalline silicon is ensured, and the production efficiency of the TBC battery is improved. Therefore, on the basis of ensuring the battery performance, the difficulty of the preparation process is reduced, and the battery manufacturing yield is improved.

The invention relates to the technical field of solar cell preparation, and discloses a laser patterned polycrystalline silicon passivation cell, a preparation method and a photovoltaic module. The preparation method comprises the following steps: preparing a passivation contact structure and an oxidation film on the surface of a silicon substrate; laser patterning processing is carried out on the surface of the silicon substrate, the passivation contact structure and the non-metallization area of the oxidation film, so that the processed non-metallization area is not subjected to alkali etching resistance, and doping atoms are pushed into the silicon substrate through laser diffusion to form a doping area; performing alkali wash etching to form an alkali wash etching region etched into the silicon substrate, and leaving a doped region on the silicon substrate exposed in the alkali wash etching region; respectively depositing a passivation antireflection film and an antireflection film on the front surface and the back surface of the silicon substrate; and preparing the metal electrode. According to the preparation method, parasitic absorption loss can be avoided, the transverse transmission capability of internal carriers can be enhanced, the light utilization rate and the photoelectric conversion efficiency of the cell are further improved, the process window is larger, and the process steps are simple.

The invention discloses a processing method of a millimeter wave radar circuit board, which adopts a continuous blind slot to replace a plurality of independent blind hole structures in a traditional structure, so that a continuous radio frequency circuit pattern can be formed, the signal shielding area is effectively increased, and the millimeter wave radar circuit board has a better signal shielding effect. Besides, the processing method of the embodiment of the invention also cancels the procedures of repeated electroplating, single-side copper reduction, circuit etching and the like in the traditional processing method, and can directly realize the manufacturing of the outer circuit, the first copper layer and the second copper layer through activation and copper deposition, thereby greatly shortening the processing flow of the millimeter wave radar circuit board, and improving the production efficiency of the millimeter wave radar circuit board. And the production efficiency of the millimeter wave radar circuit board is improved. In addition, the invention further discloses the millimeter-wave radar circuit board formed by the processing method of the millimeter-wave radar circuit board.

The invention relates to a copper-molybdenum-titanium etching solution as well as a preparation method and application thereof. The copper-molybdenum-titanium etching solution comprises a main agent, the main agent is prepared from organic acid, a fluorine-containing compound, a surfactant, organic alkali, a corrosion inhibitor, hydrogen peroxide and deionized water. The copper-molybdenum-titanium etching solution provided by the invention does not contain phosphorus, the cost and environmental protection risk in a wastewater treatment link are greatly reduced, and meanwhile, the copper-molybdenum-titanium etching solution contains low fluorine, so that the etching solution has good etching activity, corrosion to equipment is effectively reduced, a powerful guarantee is provided for stable operation of production, and the copper-molybdenum-titanium etching solution is suitable for industrial production. And meanwhile, the safety of an operation environment is improved. Especially, under the condition of low hydrogen peroxide content, the copper-molybdenum-titanium etching solution shows excellent etching performance. In addition, the etching solution also has long copper service life, can effectively inhibit the negative influence of copper ions on the etching performance, prolongs the effective service time of the etching solution in a high copper content state, greatly reduces the replacement frequency of the etching solution, reduces the production cost, and improves the production efficiency.

A MEMS sensor and a preparation method therefor. The method comprises: forming a first oxide layer on a substrate wafer, performing patterned etching on the first oxide layer, and performing deposition and doping on the first oxide layer that has undergone the patterned etching, so as to form a first polycrystalline silicon layer; performing patterned etching on the first polycrystalline silicon layer to form a wiring, and depositing a second oxide layer on the first polycrystalline silicon layer; upon performing patterned etching on the second oxide layer, performing deposition and doping to form a second polycrystalline silicon layer; performing patterned etching on the second polycrystalline silicon layer to form bonding anchor points and a capacitive plate having a lower height than the bonding anchor points; bonding a device wafer with the bonding anchor points, and performing patterned etching on the device wafer to generate a movable structure, so as to obtain a device layer; and bonding the side of the device wafer distant from the substrate wafer with a cover layer.