6075 results about "Etching" patented technology

Annular and linear contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

Methods of controlling the step coverage and pattern loading of a layer on a substrate are provided. The dielectric layer may be a silicon nitride, silicon oxide, or silicon oxynitride layer. The method comprises depositing a dielectric layer on a substrate having at least one formed feature across a surface of the substrate and etching the dielectric layer with a plasma from oxygen or a halogen-containing gas to provide a desired profile of the dielectric layer on the at least one formed feature. The deposition of the dielectric layer and the etching of the dielectric layer may be repeated for multiple cycles to provide the desired profile of the dielectric layer.

Methods for accurate and conformal removal of atomic layers of materials make use of the self-limiting nature of adsorption of at least one reactant on the substrate surface. In certain embodiments, a first reactant is introduced to the substrate in step (a) and is adsorbed on the substrate surface until the surface is partially or fully saturated. A second reactant is then added in step (b), reacting with the adsorbed layer of the first reactant to form an etchant. The amount of an etchant, and, consequently, the amount of etched material is limited by the amount of adsorbed first reactant. By repeating steps (a) and (b), controlled atomic-scale etching of material is achieved. These methods may be used in interconnect pre-clean applications, gate dielectric processing, manufacturing of memory devices, or any other applications where removal of one or multiple atomic layers of material is desired.

A method to achieve a very low effective dielectric constant in high performance back end of the line chip interconnect wiring and the resulting multilayer structure are disclosed. The process involves fabricating the multilayer interconnect wiring structure by methods and materials currently known in the state of the art of semiconductor processing; removing the intralevel dielectric between the adjacent metal features by a suitable etching process; applying a thin passivation coating over the exposed etched structure; annealing the etched structure to remove plasma damage; laminating an insulating cover layer to the top surface of the passivated metal features; optionally depositing an insulating environmental barrier layer on top of the cover layer; etching vias in the environmental barrier layer, cover layer and the thin passivation layer for terminal pad contacts; and completing the device by fabricating terminal input/output pads. The method obviates issues such as processability and thermal stability associated with low dielectric constant materials by avoiding their use. Since air, which has the lowest dielectric constant, is used as the intralevel dielectric the structure created by this method would possess a very low capacitance and hence fast propagation speeds. Such structure is ideally suitable for high density interconnects required in high performance microelectronic device chips.

Plasma-based atomic layer etching of materials may be of benefit to various semiconductor manufacturing and related technologies. For example, plasma-based atomic layer etching of materials may be beneficial for adding and/or removing angstrom thick layers from a surface in advanced semiconductor manufacturing and related technologies that increasingly demand atomistic surface engineering. A method may include depositing a controlled amount of a chemical precursor on an unmodified surface layer of a substrate to create a chemical precursor layer and a modified surface layer. The method may also include selectively removing a portion of the chemical precursor layer, a portion of the modified surface layer and a controlled portion of the substrate. Further, the controlled portion may be removed to a depth ranging from about 1/10 of an angstrom to about 1 nm. Additionally, the deposition and selective removal may be performed under a plasma environment.

Methods of preparing a clean surface of germanium tin or silicon germanium tin layers for subsequent deposition are provided. An overlayer of Ge, doped Ge, another GeSn or SiGeSn layer, a doped GeSn or SiGeSn layer, an insulator, or a metal can be deposited on a prepared GeSn or SiGeSn layer by positioning a substrate with an exposed germanium tin or silicon germanium tin layer in a processing chamber, heating the processing chamber and flowing a halide gas into the processing chamber to etch the surface of the substrate using either thermal or plasma assisted etching followed by depositing an overlayer on the substantially oxide free and contaminant free surface. Methods can also include the placement and etching of a sacrificial layer, a thermal clean using rapid thermal annealing, or a process in a plasma of nitrogen trifluoride and ammonia gas.

A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing either one of but not both of the top/bottom portion and the sidewall portion of the film by wet etching which removes the one of the top/bottom portion and the sidewall portion of the film more predominantly than the other according to the different chemical resistance properties.

A system and method for depositing a film within a reaction chamber are disclosed. An exemplary system includes a temperature measurement device, such as a pyrometer, to measure an exterior wall surface of the reaction chamber. A temperature of the exterior wall surface can be controlled to mitigate cleaning or etching of an interior wall surface of the reaction chamber.

A substrate processing apparatus which is capable of enhancing productivity in manufacturing product substrates. In process chambers 106 and 107 of an etching apparatus 100, etching is carried out on a substrate as an object to be processed, and dummy processing is carried out on at least one non-product substrate before execution of the etching. A host computer 200 determines whether or not the dummy processing is to be executed. The host computer 200 determines whether or not the interior of each of the process chambers 106 and 107 is in a stable state, and omits the execution of the dummy processing when it is determined that it is in the stable state.

A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing either one of but not both of the top/bottom portion and the sidewall portion of the film by wet etching which removes the one of the top/bottom portion and the sidewall portion of the film more predominantly than the other according to the different chemical resistance properties.

An optoelectronic device, comprising an active region and a waveguide structure to provide optical confinement of light emitted from the active region; a pair of facets on opposite ends of the device, having opposite surface polarity; and one of the facets which has been roughened by a crystallographic chemical etching process, wherein the device is a nonpolar or semipolar (Ga,In,Al,B)N based device.

This invention relates to an improved process for the selective etching of TiN from silicon dioxide (quartz) and SiN surfaces commonly found in semiconductor deposition chambers equipment and tools. In the process, an SiO₂ or SiN surface having TiN thereon is contacted with XeF₂ in a contact zone to selectively convert the TiN to a volatile species and then the volatile species is removed from the contact zone. XeF₂ can be preformed or formed in situ by reaction between Xe and a fluorine compound.

The present invention provides a bonded substrate fabricated to have its final active layer thickness of 200 nm or lower by performing the etching by only 1 nm to 1 μm with a solution having an etching effect on a surface of an active layer of a bonded substrate which has been prepared by bonding two substrates after one of them having been ion-implanted and then cleaving off a portion thereof by heat treatment. SC-1 solution is used for performing the etching. A polishing, a hydrogen annealing and a sacrificial oxidation may be respectively applied to the active layer before and/or after the etching. The film thickness of this active layer can be made uniform over the entire surface area and the surface roughness of the active layer can be reduced as well.

The invention concerns a method for producing a gallium nitride (GaN) epitaxial layer characterised in that it consists in depositing on a substrate a dielectric layer acting as a mask and depositing on the masked gallium nitride, by epitaxial deposit, so as to induce the deposit of gallium nitride patterns and the anisotropic lateral growth of said patterns, the lateral growth being pursued until the different patterns coalesce. The deposit of the gallium nitride patterns can be carried out ex-situ by dielectric etching or in-situ by treating the substrate for coating it with a dielectric film whereof the thickness is of the order of one angstrom. The invention also concerns the gallium nitride layers obtained by said method.

A method of filling recesses or grooves on a patterned surface with a layer of film, by combining depositing a film by PEALD/PPECVD on the patterned surface and etching the film, wherein the deposition and the etching are separately controlled, and wherein the conditions for deposition can be controlled by controlling RF power.

A process for fabricating a leadless plastic chip carrier includes selectively etching at least a first surface of a leadframe strip to partially define at least a plurality of contact pads and a die attach pad; selectively plating at least one layer of metal on a second surface of the leadframe strip, on an undersurface of at least the plurality of contact pads and the die attach pad; mounting a semiconductor die on the first surface, on the partially defined die attach pad; wire bonding the semiconductor die to ones of the contact pads; encapsulating the wire bonds and the semiconductor die in a molding material such that the molding material covers a first portion of the die attach pad and first portions of the contact pads; selectively etching a second surface of the leadframe strip to define a second portion of the contact pads and a second portion of the die attach pad by etching the second surface with the at least one layer of metal resisting etching; and singulating the leadless plastic chip carrier from the leadframe strip.

A method for forming an active pillar of a vertical channel transistor includes forming a hard mask pattern on a substrate, etching vertically the substrate using the hard mask pattern as an etch barrier to form an active pillar, and etching horizontally to remove by-product remaining on the exposed substrate, the hard mask pattern and the active pillar and at the same time to reduce line width of the hard mask pattern and the active pillar, wherein a unit cycle in which the vertical etching and the horizontal etching are each performed subsequently once, respectively, is performed repeatedly at least two times or more. According to the present invention, an active pillar having vertical profiles on its sidewalls and having height and line width (or diameter) required in a highly integrated vertical channel transistor can be provided.

The present invention provides reagents for use in an automated environment for removing or etching embedding media by exposing a biological sample to be stained in histochemical or cytochemical procedures without the dependence on organic solvents. The reagents comprise components optimized to facilitate removal or etching of the embedding media from the biological sample. The present invention also provides reagents for use in an automated environment for cell conditioning biological samples wherein the cells are predisposed for access by reagent molecules for histochemical and cytochemical staining procedures. The reagents comprise components optimized to facilitate molecular access to cells and cell constituents within the biological sample.

The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.

Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

The present invention provides systems and methods of forming an epitaxial film on a substrate. After heating in a process chamber, the substrate is exposed to a silicon source and at least one of SiH2(CH3)2, SiH(CH3)3, Si(CH3)4, 1,3-disilabutane, and C2H2, at a temperature of greater than about 250 degrees Celsius and a pressure greater than about 1 Torr so as to form an epitaxial film on at least a portion of the substrate. Then, the substrate is exposed to an etchant so as to etch the epitaxial film and any other films formed during the deposition. The deposition and etching may be repeated until a film of a desired thickness is achieved. Numerous other aspects are disclosed.

An apparatus and method for providing an etching gas source for etching one or more microstructures located within a process chamber. the apparatus has a gas source supply line attached to a gas source and one or more chambers for containing an etching material. In use, the etching material is transformed into an etching material vapor within one or more of the chamber and the gas supply line provides a supply of carrier gas to the etching material vapor and also supplies the etching material vapor transported by the carrier gas to the process chamber. Advantageously, the apparatus of the invention does not require the incorporation of any expansion chambers or other complicated mechanical features in order to achieve a continuous flow of etching gas.

Disclosed is a semiconductor wafer whose pattern is composed of a plurality of chip areas delimited by a plurality of streets which at least one or more streets are not straight. Those chip areas may be rectangular ones of same or different sizes delimited by streets which are wholly or partly staggered, or ones of different shapes and/or sizes delimited by streets which are bent or curved so that they may separate adjacent chip areas. Such a semiconductor wafer can be separated into chips by: coating one of the opposite surfaces of each semiconductor wafer with a photo-resistive film; exposing the coated surface of the semiconductor wafer to the light to remove the coating area lying on the streets; subjecting the street-exposed wafer surface to chemical etching to make grooves in conformity with the streets; and separating the semiconductor wafer into chips. The separating step may include making grooves deep enough to reach the front side of the wafer by chemical etching or grinding the grooved wafer on its rear side to remove the remaining thickness of the grooved wafer.

A method for the plasma-free etching of silicon using the etching gas ClF₃ or XeF₂ and its use are provided. The silicon is provided having one or more areas to be etched as a layer on the substrate or as the substrate material itself. The silicon is converted into the mixed semiconductor SiGe by introducing germanium and is etched by supplying the etching gas ClF₃ or XeF₂. The introduction of germanium and the supply of the etching gas ClF₃ or XeF₂ may be performed at the same time or alternatingly. In particular, it is provided that the introduction of germanium be performed by implanting germanium ions in silicon.

In accordance with the present invention, improved methods for reducing the dislocation density of nitride epitaxial films are provided. Specifically, an in-situ etch treatment is provided to preferentially etch the dislocations of the nitride epitaxial layer to prevent threading of the dislocations through the nitride epitaxial layer. Subsequent to etching of the dislocations, an epitaxial layer overgrowth is performed. In certain embodiments, the etching of the dislocations occurs simultaneously with growth of the epitaxial layer. In other embodiments, a dielectric mask is deposited within the etch pits formed at the dislocations prior to the epitaxial layer overgrowth.

Fabrication methods and processes are described, the methods and processes occurring at a low-temperature and involving passivation. The methods and processes easily incorporate annealing, deposition, patterning, lithography, etching, oxidation, epitaxy and chemical mechanical polishing for forming suitable devices, such as diodes and MOSFETs. Such fabrication is a suitable and more cost-effective alternative to a process of diffusion or doping, typical for forming p-n junctions. The process flow does not require temperatures above 700 degrees Centigrade. Formation of p-n junctions in discrete silicon diodes and MOSFETs are also provided, fabricated at low temperatures in the absence of diffusion or doping.

A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.

A method for fabricating a recess gate in a semiconductor device includes etching a silicon substrate to form a trench that defines an active region, forming a device isolation layer that gap-fills the trench, forming a hard mask layer over the silicon substrate, the hard mask layer comprising a stack of an oxide layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the active region, and forming a recess region with a dual profile by first etching and second etching the channel target region using the hard mask layer as an etch barrier, wherein the second etching is performed after removing the amorphous carbon layer.

Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).