3653 results about "Photolithography" patented technology

Disclosed are methods and apparatus for qualifying a photolithographic reticle. A reticle inspection tool is used to acquire images at different imaging configurations from each of a plurality of pattern areas of a test reticle. A reticle near field for each of the pattern areas of the test reticle is recovered based on the acquired images from each pattern area of the test reticle. A lithography model is applied to the reticle near field for the test reticle to simulate a plurality of test wafer images, and the simulated test wafer images are analyzed to determine whether the test reticle will likely result in an unstable or defective wafer.

To provide an onium salt which is used for a chemically amplified resist composition having excellent solvent solubility, high sensitivity, high contrast, and excellent lithographic performances such as exposure latitude and linewidth roughness, in photolithography using high-energy radiation, a chemically amplified resist composition comprising the onium salt as a photoacid generator, and a pattern forming process using the chemically amplified resist composition.SOLUTION: An onium salt having the following formula (1) is provided. [R1-R12 independently represent H, halogen, or a C1-C20 hydrocarbyl group optionally including a heteroatom; one of R13 and R14 represents a substituent having a terminal sulfonic acid anion; the other represents H, halogen, or a C1-C20 hydrocarbyl group optionally including a heteroatom; and Z+ represents an onium cation.]SELECTED DRAWING: None

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide thick-bottom oxide layer groove MOS structure and a preparation method thereof, the silicon carbide thick-bottom oxide layer groove MOS structure comprises a plurality of parallel MOS cells, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the lightly doped N layer is arranged in the middle of the N drift layer, the arc-shaped contour design with the inclined top is introduced to the two sides, the injection area is accurately controlled through the photoetching technology, the phenomenon that the edge electric field concentration of the N drift layer is effectively dispersed is effectively dispersed, in this way, electric field distribution is more uniform, breakdown voltage is improved, and local electric field concentration is reduced; moreover, the contact between the laterally symmetrical P-layer and the N substrate layer enhances the charge balance capability, and reduces the leakage current.

The invention discloses an implementation method of a multi-chip high-density connection photoetching technology, an implementation method of a photoetching technology for multi-chip interconnection, a chip-level chip interconnection method, a manufacturing method of a mask plate line and photoetching equipment. The implementation method of the multi-chip high-density connection photoetching technology comprises the following steps: selecting a first mask plate to align and expose with a first original pattern unit in a first M * N chipset through a second alignment mark, and transferring a pattern of the first mask plate to an exposure area covering the first original pattern unit; longitudinally moving the substrate by M times of the longitudinal size of the original pattern or transversely moving the substrate by N times of the transverse size of the original pattern to execute alignment exposure, and completing exposure of corresponding areas of other M * N chip groups; and other masks are selected to repeatedly perform exposure on other corresponding pattern units of the first M * N chip set, and longitudinal movement or transverse movement is repeatedly performed to complete exposure of corresponding areas of the corresponding pattern units in other M * N chip sets. According to the scheme, high-density interconnection of multiple chips is realized.

The invention belongs to the technical field of semiconductors, and particularly discloses a photoetching hot spot detection method and system based on a graph neural network. The method comprises the following steps: decomposing each polygonal metal in a layout into rectangles by scanning in the horizontal direction, and taking the rectangles as nodes of the layout; adding an internal edge and an external edge between the rectangles according to a specific rule; the diagonal vertex coordinates of the rectangles are used as node features, the minimum distance between the rectangles represents edge features, and graph representation of the layout is completed; inputting the graph representation of the layout into a message passing layer of a GNN model to perform graph feature extraction, and performing global maximum pooling and global average pooling on each dimension of all node features to obtain global graph representation; and classifying the global graph representation into hotspots and non-hotspots. According to the invention, the accuracy and calculation efficiency of layout hot spot detection can be improved.

The invention provides a manufacturing and processing photoetching method and system of a display panel, and relates to the technical field of photoetching processing. According to the method, the display panel substrate is subjected to cleaning, prime coating and partition division to form an imageable micro-mark covering all exposure partitions, and the thickness and the uniformity are measured after lower-layer supporting glue and upper-layer imaging glue are sequentially formed; carrying out in-situ acquisition and modeling by taking the micro-mark as an imaging object, and generating an exposure correction instruction and an overlapping energy table; performing partition exposure and real-time correction by using a digital micromirror, and completing development to obtain an anti-etching window with a steep side wall; and setting an etching window according to the exposure record and the window quality data, and executing low-damage etching and defect recovery to form stability evaluation data. According to the method, comprehensive improvement of high-precision exposure, pattern consistency and electrical stability is realized.

The embodiment of the invention provides a wafer electroplating method and a wafer electroplating product thereof. The method comprises the following steps: preparing a seed layer on the surface of a wafer; photoetching the seed layer to obtain a to-be-electroplated region with a preset pattern; carrying out first electroplating operation on the to-be-electroplated area at a first preset current density to obtain a metal coating; and after the first electroplating operation is finished, carrying out second electroplating operation on the to-be-electroplated area at a second preset current density so as to enable the metal coating to reach a preset thickness, wherein the second preset current density is 65 to 75 times of the first preset current density. According to the method, the adhesion of the metal coating can be effectively enhanced, the metal coating is prevented from falling off, meanwhile, the maximum current capable of being used by the second electroplating operation is improved, and therefore the total duration of the electroplating process is effectively shortened.

The invention relates to the technical field of radio frequency integrated circuits and advanced semiconductor packaging, in particular to a multilayer spiral inductor structure based on an RDL process and a preparation method. The preparation method comprises the steps of seed layer deposition, gradient line width coil formation through photoetching and electroplating, alternate dielectric layer deposition, through hole etching to form vertical interconnection copper columns, air bridge forming through a photoresist sacrificial layer process and silicon nitride passivation packaging. Through fan-shaped topological layout, dielectric material collaborative optimization and three-dimensional interconnection structure design, the self-resonant frequency bandwidth is effectively improved, conductor and dielectric loss is reduced, and miniaturization integration and high reliability of high-frequency inductance elements are achieved.

The invention discloses a multilayer three-dimensional stacked circuit board and a preparation method thereof, and the method specifically comprises the steps: obtaining a substrate with a single conductive surface, and carrying out the spraying of a stress buffer layer on the conductive surface of the substrate; covering a layer of insulating material on the stress buffer layer, and forming a pattern insulating layer through photoetching; performing pulse electroplating processing on the exposed pattern of the pattern insulating layer to obtain a first circuit board; silk-screening a flexible connection layer on the pattern bonding pad layer of the first circuit board, and carrying out three-dimensional stacking processing on the flexible connection layer to obtain a second circuit board; and assembling a circuit protection layer on the second circuit board, and processing a stress release groove between the second circuit board and the circuit protection layer to obtain the multi-layer three-dimensional stacked circuit board. Through the design of the stress buffer layer and the stress release groove, interlayer stress can be reduced, circuit board breakage or cracking caused by overlarge interlayer stress is avoided, and the technical problem that large interlayer stress is generated in the circuit board preparation process in the prior art is solved.

The invention relates to an experimental method for manufacturing a through hole by using gray exposure, and aims to realize a through hole structure with a specific inclination angle and depth-to-width ratio through collaborative design of photoetching and etching processes. The method comprises the following steps: determining a through hole angle and a depth-to-width ratio, selecting an etching condition, designing a gray mask structure based on an etching rate selection ratio, implementing gray exposure to obtain a mask pattern, etching, removing residual photoresist and finally forming a target through hole. And by regulating and controlling the selection ratio k of the mask to the substrate material, the inclination angle beta of the through hole and the depth H, designing the gray-scale mask morphology conforming to the target structure. The gray mask can be constructed by adopting gray photoresist or an optical modulation mask, and the inclination morphology parameter, the etching time and the etching rate of the gray mask meet a specific relation, so that high-precision structure control is realized. The method is suitable for the fields of MEMS, micro-optical devices and the like with high requirements on the morphology precision of the through hole, and has the effects of good structure consistency and high process repeatability.

The invention discloses a high-dynamic surface single-frame measurement method based on a multi-view digital speckle correlation method, and belongs to the technical field of multi-view digital speckles, and the method comprises the steps: constructing a speckle projection collection system based on a four-view camera and a photoetching speckle projection module, and collecting a single-frame image of a measured workpiece based on the speckle projection collection system; processing a single-frame image of the measured workpiece based on a multi-scale robust multi-view matching algorithm to obtain an intermediate depth map and a pixel-by-pixel space inclined plane; iterative calculation is carried out on the intermediate parameters of the space inclined plane pixel by pixel based on a digital speckle correlation method, and final parameters of the space inclined plane are obtained; and fusing the final depth map based on the final parameters of the space inclined plane and the left-right consistency superposition test to obtain final point cloud data. According to the invention, a workpiece with a high dynamic surface in a field of view can be quickly reconstructed by using a single-frame image, a high-integrity and high-precision point cloud is obtained, and the measurement precision can reach 0.03-0.07 mm.

To provide a curable resin composition for white three-dimensional molded objects that possesses various properties during photolithography while achieving plastic-like white appearance.SOLUTION: A curable resin composition for white three-dimensional molded objects comprises a cationically polymerizable organic compound (A), a radically polymerizable organic compound (B), and a one-end-capped polyalkylene oxide compound with a specific structure.SELECTED DRAWING: None

The invention discloses a photoresist model training method, device and equipment and a computer storage medium. The method comprises the following steps: acquiring a photoetching design layout, a mask layout and a photoetching process parameter information set; constructing an initial photoresist model according to the first parameter; carrying out first training with a preset number of iterations on the initial photoresist model to obtain a first photoresist model; screening the index value of the graphic index in the last iteration process from the training log; under the condition that the index value of the graphic index is determined to be greater than a preset threshold value, updating a parameter in the initial photoresist model into a second parameter to obtain an updated initial photoresist model, and returning to carry out first training of a preset number of iterations on the initial photoresist model according to the mask layout and the photoetching design layout to obtain a first photoresist model, and obtaining a trained photoresist model until the index value is smaller than or equal to a preset threshold value. According to the embodiment of the invention, the photoresist model training efficiency can be improved.

The invention relates to a photoresist and an application method thereof, and belongs to the technical field of photolithography, the photoresist comprises a solvent, and a resin, a polymer monomer, a photosensitizer and a fluorescent agent which are dispersed in the solvent, the size of the fluorescent agent is less than 100 nanometers, and the fluorescent agent can be removed through ashing, so that after the photoresist is developed, the photosensitizer can be removed through ashing. According to the method, the residual photoresist defect can be nondestructively detected by utilizing the fluorescence emitted by the fluorescent agent in the residual photoresist, and the fluorescence detection is low in cost and high in efficiency, the fluorescent agent is easy to remove, and the fluorescent agent residue is avoided, so that the detection cost of the residual photoresist defect can be greatly reduced, and the detection efficiency of the residual photoresist defect is improved; and the application prospect of the photoresist is widened.

A method for detecting printing defects in a photolithography mask that will print on a wafer when using the photolithography mask in a specific photolithography system to print semiconductor structures on the wafer, the method comprising: acquiring a first aerial image of the photolithography mask using a mask inspection system; generating a second aerial image of the photolithography mask by applying a machine learning model (26) to the first aerial image, wherein the machine learning model is trained to map a first aerial image acquired by a mask inspection system to a second aerial image that emulates the application of the specific photolithography system to the photolithography mask; and detecting printing defects in the photolithography mask by comparing the second aerial image to a reference image.

The invention provides a method for aligning a bonding body wafer on a non-infrared exposure machine, which comprises the following steps of: providing the bonding body wafer which comprises a plurality of wafers in bonding connection, and forming alignment marks on the bonding surfaces of the wafers which are mutually bonded; manufacturing an alignment photomask, wherein the alignment photomask is provided with an alignment mark window pattern; forming an alignment mark window on the surface of the bonding body wafer by utilizing photoetching and etching processes through an alignment photomask, and exposing the alignment mark on the bonding surface through the alignment mark window; and carrying out photoetching alignment through the exposed alignment mark. According to the method, the alignment problem when the alignment mark on the non-infrared exposure machine is positioned in the bonding body wafer is solved. The invention further provides a preparation method of the semiconductor device, the alignment method is adopted for alignment after the front face and the back face of a bonding body wafer are thinned, then the pattern face of the device is processed, and possible pollution to the bonding face and possible damage to the pattern face are avoided.

The invention relates to the technical field of piezoelectric single-crystal filters, in particular to a filter based on a heterogeneous integrated piezoelectric single-crystal thin film and a preparation method, the filter comprises a Si substrate, a dry film, the piezoelectric single-crystal thin film, a SiO2 layer and a Si wafer are sequentially arranged on the Si substrate, metal balls are arranged on the Si wafer, the metal balls are connected with electrodes, and the electrodes are connected with the piezoelectric single-crystal thin film. And the electrode passes through the Si wafer and the SiO2 layer and is connected with the piezoelectric single crystal film. When the filter is prepared, bonding packaging can be performed after a cavity area is etched on a dry film, a resonance area is directly defined through a photoetching process, the influence of etching on the strength of the piezoelectric single crystal film is avoided, a silicon wafer bonding technology can be combined, double-sided packaging can be realized, and batch production is supported; in the process, only the electrode patterning step needs to be adjusted according to the type of the filter, and then the existing MEMS process integration is utilized, so that the preparation of the FBAR and the XBAR on the same production line is realized, the process compatibility is good, and the problems that the existing preparation method is poor in compatibility and is difficult to realize large-scale production are solved.

The scheme provided by the embodiment of the invention provides a photoetching image correction method and device based on an OPC (Optical Proximity Correction) technology and a storage medium. The method comprises the following steps: simulating different cross-layer exposure processes of a wafer through a photoetching imaging model, and obtaining a prediction result of a photoetching image of each layer of material; taking the target layout as the input of a photoetching imaging model, carrying out OPC correction, correcting a prediction result, and outputting a corrected Mask layout file; checking items are set through OPC verify, pixel point EPE checking is conducted on the corrected Mask layout file, accuracy checking is conducted on the corrected Mask layout file, and the optimally corrected Mask layout file is output. The technical problems that how to reduce CD Loss and how to effectively reduce the Shot risk caused by a manual correction mode are effectively solved.

The invention discloses a layout generation method for load effect compensation and a related device, which are applied to the technical field of photoetching and comprise the following steps: acquiring photomask data; carrying out grid division on the mask graph according to the photomask data, and determining layout density in each grid; comparing the layout density of each grid with a target density, and determining a density difference value corresponding to each grid; determining a virtual graph corresponding to each grid according to the density difference value; and adding a corresponding virtual graph in a layout area corresponding to the grid to form a compensated mask plate graph. By performing grid division on the mask plate graph, calculating the specific layout density in each grid and adding the corresponding virtual graph to the layout area corresponding to the grid according to the difference value between the layout density and the target density, the graph density of the layout area in each grid can be effectively compensated, so that the load effect of each area in the layout is balanced, and the performance of the mask plate is improved. And the etching uniformity is improved.

The invention belongs to the technical field of semiconductors, and relates to a method for electroplating metal on the back surface of a wafer, which comprises the following steps of: forming at least two positioning holes on the edge of the wafer, and forming an electroplating metal layer on the back surface of the wafer through the positioning holes, so that a groove pattern formed between the electroplating metal layer and the wafer is the same as a pattern of a cutting channel on the front surface of the wafer; therefore, the use of a double-sided photoetching machine can be avoided, the equipment cost is obviously reduced, the process flow is simple, the industrial production is easy, the fragment rate is obviously reduced, the production efficiency is obviously improved, and the application prospect is wide.

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the following steps: removing the second pseudo gate structure to expose the second active structure and the gate isolation layer; coating photoresist on the second active structure and the gate isolation layer in the first semiconductor unit, and at least removing the gate isolation layer in the second semiconductor unit through a photoetching process; sequentially removing the first pseudo gate structure and the photoresist to expose the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit and the first active structure and the second active structure in the second semiconductor unit; and forming a first gate structure and a second gate structure based on the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, and simultaneously forming a third gate structure and a fourth gate structure based on the first active structure and the second active structure in the second semiconductor unit.

The embodiment of the invention discloses a photoetching mask updating method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring a target chip layout, constructing a mask pattern and a level set function, and performing photoetching simulation on the mask pattern to obtain a wafer pattern; determining target loss according to the difference between the target chip layout and the wafer pattern, obtaining a first optimization item through a conjugate gradient optimizer, and obtaining a second optimization item through an adaptive moment estimation optimizer; performing attention processing on the target chip layout to obtain a target attention map, and adjusting the second optimization item based on the target attention map; updating the level set function based on the first optimization item and the adjusted second optimization item, and updating the mask pattern based on the updated level set function; according to the embodiment of the invention, while the complexity of the mask pattern is reduced, the pattern error of the mask pattern is effectively reduced, so that the correction precision of the mask pattern is improved, and the method can be widely applied to scenes such as cloud technology and chip manufacturing.

The invention provides an epitaxial wafer edge morphology compensation type wafer double-sided polishing device and method, and belongs to the technical field of semiconductor wafer ultra-precision machining. The polishing main machine comprises an upper fixed disc, a lower fixed disc and a wafer driving mechanism; the pressure loading system is used for applying adjustable pressure to the fixed disc; the polishing solution supply system is used for conveying a flow-adjustable polishing solution to the processing interface; the central control unit is in communication connection with the two systems and executes edge morphology compensation control logic, specifically, the machining pressure is adjusted in a segmented mode, and the flow of the polishing solution and the pressure are subjected to coupling change. According to the method, the atomic level flatness of the wafer surface is ensured, the edge morphology is accurately controlled, the edge thickening of the epitaxial layer is perfectly counteracted, and the photoetching yield of high-end chip manufacturing is remarkably improved.

The present disclosure provides an alignment method and application of a cyanobiphenyl liquid crystal composite doped with an organic donor material. The organic small molecule is doped in the host cyanobiphenyl liquid crystal, and the small molecule donor / cyanobiphenyl liquid crystal mixture is directionally induced to assemble by virtue of the large surface energy difference between the superhydrophobic structured substrate and the superhydrophilic flat substrate. The liquid crystal molecules form a uniform arrangement under the action of the liquid bridge, driving the self-assembly of the small molecule donor to be embedded in the cyanobiphenyl liquid crystal, forming a structure of electron donor-donor, enhancing the conductivity of the liquid crystal composite device, studying the influence of the surface tension of the solvent on the performance of the composite, and giving a direction for the selection of the solvent. Compared with the methods of inducing the alignment of liquid crystal molecules and donor small molecules by using electric fields, magnetic fields, photolithography, capillary methods, etc., this method is simpler and more feasible, easy to transfer, the circuit pattern is easy to design, and has good stability.

The invention provides a method for improving adhesion of photoresist and a wafer, which comprises the following steps: providing a wafer, forming a carbon dot layer on the surface of the wafer, the carbon dot layer comprising a plurality of carbon dots, and all the carbon dots being randomly distributed on the surface of the wafer; a patterned photoresist layer is formed on the surface of the wafer, the patterned photoresist layer is provided with an opening, part of the carbon dot layer is exposed out of the opening, and the patterned photoresist layer on the outer side of the opening covers the remaining part of the carbon dot layer; etching a part of thickness of the wafer by taking the patterned photoresist layer as a mask; and removing the photoresist layer and the carbon dot layer. According to the invention, the carbon dot layer in which the carbon dots are randomly distributed is formed between the surface of the wafer and the photoresist layer, so that a good contact surface is formed between the photoresist layer and the wafer, and the adhesion between the photoresist layer and the wafer is improved.

The invention relates to a diffractive optical element beam shaping method based on spatial frequency filtering, and the method comprises the steps: obtaining an incident beam, and obtaining corresponding geometric analysis phase distribution based on a preset homogenized beam; the homogenized light beam is adjusted to be a rectangular flat-topped light beam, and phase correction processing is carried out on the obtained geometric analysis phase; the geometric analysis phase after phase correction is processed based on a spatial frequency filtering method, a processed light field regulation and control distribution requirement is obtained, and the processed light field regulation and control distribution requirement has phase and amplitude regulation and control requirements at the same time; and designing a diffractive optical element, so that the diffractive optical element meets the required light field regulation and distribution requirements, and shaping an incident light beam into the rectangular flat-topped light beam by using the diffractive optical element. According to the invention, the light beam homogenization effect with high uniformity, sharp edge and high diffraction efficiency can be realized, and wide application prospects are obtained in the aspects of laser welding, photoetching, biomedicine and the like.

The invention belongs to the technical field of semiconductors, and provides a cleavage method, which adopts non-mechanical means such as etching, corrosion and the like to avoid the action of mechanical stress on a slice wafer, thereby greatly reducing the possibility of cracks on the end face of the slice wafer. Specifically, the cleavage method is implemented according to the following steps: growing silicon oxide on the back surface of a thin wafer to form a mask layer; coating photoresist on the surface of one side, deviating from the sheet wafer, of the mask layer to form a second glue layer; photoetching the second adhesive layer to construct a second cleavage region which is overlapped with the first cleavage region on the front surface of the thin wafer; removing silicon oxide on the mask layer relative to the position of the second cleavage region; coating at least two layers of photoresist on the front surface of the thin wafer to form a first adhesive layer; photoetching the first adhesive layer, and displaying a first cleavage area through a developing step; performing dry etching on the front surface of the sheet wafer; and performing wet etching on the back surface of the sheet wafer.

The invention provides an IGBT (Insulated Gate Bipolar Translator) device structure and a preparation method thereof. The preparation method comprises the following steps: forming a plurality of gate trenches in an active region, and forming a gate oxide layer and a polycrystalline silicon layer; forming a grid line mask pattern; forming a polysilicon gate line, and reserving a gate line mask pattern on the polysilicon gate line; a hard mask medium is deposited, a first window and a second window which expose the surface of the active area are formed, and the second window exposes the grid line mask pattern on the grid line; etching is carried out, based on the etching selection ratio, the semiconductor substrate in the first window is partially removed to form an emitter region contact hole, and the grid line mask pattern in the second window is not removed to protect the grid line; and removing the grid line mask pattern in the second window by a wet method to form a grid line contact hole. According to the invention, the preparation of the emitter region contact hole and the line contact hole only needs to use one mask plate for photoetching and etching, compared with the traditional process, one mask plate is effectively reduced, the process flow is simplified, the production period is shortened, and the production efficiency is improved while the tape-out cost is reduced.

The invention relates to the technical field of semiconductors, in particular to a columnar array enhanced photoelectric detector and a preparation method thereof, and the method comprises the following steps: depositing a continuous GaN layer on a substrate through an epitaxial growth method; forming a columnar array structure pattern and an electrode region on the GaN layer through a photoetching process, and removing a part of the GaN layer through an etching process to form an exposed columnar GaN array; depositing a metal electrode layer on two sides of the GaN array, and forming ohmic contact or Schottky contact with the GaN layer to obtain a photoelectric detector; the photoelectric detector is connected with a peripheral circuit to form a complete columnar array enhanced photoelectric detector system, the GaN layer of the columnar array structure is adopted, multiple times of reflection and interference on incident light are achieved, and therefore the detection efficiency and the response speed of the photoelectric detector are improved.

The invention belongs to the technical field of solar cell materials, and discloses a GaAs solar cell with a moth-eye micro-nano structure anti-reflection layer and a preparation method of the GaAs solar cell in order to enhance the solar spectrum utilization rate and improve the photoelectric conversion efficiency of the solar cell. The method comprises the following steps: growing a thin film with a nano-column structure on a Si substrate with a SiO2 layer in an MBE autocatalytic growth mode, spin-coating PMMA on the surface of the thin film, and transferring the nano-column structure to a GaAs and carbon nanotube heterojunction solar cell through a two-dimensional material wet transfer technology to prepare the solar cell with the moth-eye micro-nano structure anti-reflection layer. Compared with a nanoimprint lithography technology and a photolithography technology, the method provided by the invention is more convenient to operate and more environment-friendly, and does not need to use some harmful gases and harmful chemicals to etch the micro-nano structure. According to the GaAs heterojunction solar cell with the moth-eye bionic micro-nano structure anti-reflection layer prepared by the method, the material used by the anti-reflection layer is not limited, and the utilization rate of sunlight can be remarkably improved, so that the photoelectric conversion efficiency of a device is remarkably improved.