2215 results about "Photolithography" patented technology

Disclosed are methods and apparatus for qualifying a photolithographic reticle. A reticle inspection tool is used to acquire images at different imaging configurations from each of a plurality of pattern areas of a test reticle. A reticle near field for each of the pattern areas of the test reticle is recovered based on the acquired images from each pattern area of the test reticle. A lithography model is applied to the reticle near field for the test reticle to simulate a plurality of test wafer images, and the simulated test wafer images are analyzed to determine whether the test reticle will likely result in an unstable or defective wafer.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide thick-bottom oxide layer groove MOS structure and a preparation method thereof, the silicon carbide thick-bottom oxide layer groove MOS structure comprises a plurality of parallel MOS cells, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the lightly doped N layer is arranged in the middle of the N drift layer, the arc-shaped contour design with the inclined top is introduced to the two sides, the injection area is accurately controlled through the photoetching technology, the phenomenon that the edge electric field concentration of the N drift layer is effectively dispersed is effectively dispersed, in this way, electric field distribution is more uniform, breakdown voltage is improved, and local electric field concentration is reduced; moreover, the contact between the laterally symmetrical P-layer and the N substrate layer enhances the charge balance capability, and reduces the leakage current.

The invention discloses an implementation method of a multi-chip high-density connection photoetching technology, an implementation method of a photoetching technology for multi-chip interconnection, a chip-level chip interconnection method, a manufacturing method of a mask plate line and photoetching equipment. The implementation method of the multi-chip high-density connection photoetching technology comprises the following steps: selecting a first mask plate to align and expose with a first original pattern unit in a first M * N chipset through a second alignment mark, and transferring a pattern of the first mask plate to an exposure area covering the first original pattern unit; longitudinally moving the substrate by M times of the longitudinal size of the original pattern or transversely moving the substrate by N times of the transverse size of the original pattern to execute alignment exposure, and completing exposure of corresponding areas of other M * N chip groups; and other masks are selected to repeatedly perform exposure on other corresponding pattern units of the first M * N chip set, and longitudinal movement or transverse movement is repeatedly performed to complete exposure of corresponding areas of the corresponding pattern units in other M * N chip sets. According to the scheme, high-density interconnection of multiple chips is realized.

The invention provides a manufacturing and processing photoetching method and system of a display panel, and relates to the technical field of photoetching processing. According to the method, the display panel substrate is subjected to cleaning, prime coating and partition division to form an imageable micro-mark covering all exposure partitions, and the thickness and the uniformity are measured after lower-layer supporting glue and upper-layer imaging glue are sequentially formed; carrying out in-situ acquisition and modeling by taking the micro-mark as an imaging object, and generating an exposure correction instruction and an overlapping energy table; performing partition exposure and real-time correction by using a digital micromirror, and completing development to obtain an anti-etching window with a steep side wall; and setting an etching window according to the exposure record and the window quality data, and executing low-damage etching and defect recovery to form stability evaluation data. According to the method, comprehensive improvement of high-precision exposure, pattern consistency and electrical stability is realized.

The invention relates to the technical field of radio frequency integrated circuits and advanced semiconductor packaging, in particular to a multilayer spiral inductor structure based on an RDL process and a preparation method. The preparation method comprises the steps of seed layer deposition, gradient line width coil formation through photoetching and electroplating, alternate dielectric layer deposition, through hole etching to form vertical interconnection copper columns, air bridge forming through a photoresist sacrificial layer process and silicon nitride passivation packaging. Through fan-shaped topological layout, dielectric material collaborative optimization and three-dimensional interconnection structure design, the self-resonant frequency bandwidth is effectively improved, conductor and dielectric loss is reduced, and miniaturization integration and high reliability of high-frequency inductance elements are achieved.

The invention relates to an experimental method for manufacturing a through hole by using gray exposure, and aims to realize a through hole structure with a specific inclination angle and depth-to-width ratio through collaborative design of photoetching and etching processes. The method comprises the following steps: determining a through hole angle and a depth-to-width ratio, selecting an etching condition, designing a gray mask structure based on an etching rate selection ratio, implementing gray exposure to obtain a mask pattern, etching, removing residual photoresist and finally forming a target through hole. And by regulating and controlling the selection ratio k of the mask to the substrate material, the inclination angle beta of the through hole and the depth H, designing the gray-scale mask morphology conforming to the target structure. The gray mask can be constructed by adopting gray photoresist or an optical modulation mask, and the inclination morphology parameter, the etching time and the etching rate of the gray mask meet a specific relation, so that high-precision structure control is realized. The method is suitable for the fields of MEMS, micro-optical devices and the like with high requirements on the morphology precision of the through hole, and has the effects of good structure consistency and high process repeatability.

A method for detecting printing defects in a photolithography mask that will print on a wafer when using the photolithography mask in a specific photolithography system to print semiconductor structures on the wafer, the method comprising: acquiring a first aerial image of the photolithography mask using a mask inspection system; generating a second aerial image of the photolithography mask by applying a machine learning model (26) to the first aerial image, wherein the machine learning model is trained to map a first aerial image acquired by a mask inspection system to a second aerial image that emulates the application of the specific photolithography system to the photolithography mask; and detecting printing defects in the photolithography mask by comparing the second aerial image to a reference image.

The invention discloses a layout generation method for load effect compensation and a related device, which are applied to the technical field of photoetching and comprise the following steps: acquiring photomask data; carrying out grid division on the mask graph according to the photomask data, and determining layout density in each grid; comparing the layout density of each grid with a target density, and determining a density difference value corresponding to each grid; determining a virtual graph corresponding to each grid according to the density difference value; and adding a corresponding virtual graph in a layout area corresponding to the grid to form a compensated mask plate graph. By performing grid division on the mask plate graph, calculating the specific layout density in each grid and adding the corresponding virtual graph to the layout area corresponding to the grid according to the difference value between the layout density and the target density, the graph density of the layout area in each grid can be effectively compensated, so that the load effect of each area in the layout is balanced, and the performance of the mask plate is improved. And the etching uniformity is improved.

The embodiment of the invention discloses a photoetching mask updating method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring a target chip layout, constructing a mask pattern and a level set function, and performing photoetching simulation on the mask pattern to obtain a wafer pattern; determining target loss according to the difference between the target chip layout and the wafer pattern, obtaining a first optimization item through a conjugate gradient optimizer, and obtaining a second optimization item through an adaptive moment estimation optimizer; performing attention processing on the target chip layout to obtain a target attention map, and adjusting the second optimization item based on the target attention map; updating the level set function based on the first optimization item and the adjusted second optimization item, and updating the mask pattern based on the updated level set function; according to the embodiment of the invention, while the complexity of the mask pattern is reduced, the pattern error of the mask pattern is effectively reduced, so that the correction precision of the mask pattern is improved, and the method can be widely applied to scenes such as cloud technology and chip manufacturing.

The invention provides an epitaxial wafer edge morphology compensation type wafer double-sided polishing device and method, and belongs to the technical field of semiconductor wafer ultra-precision machining. The polishing main machine comprises an upper fixed disc, a lower fixed disc and a wafer driving mechanism; the pressure loading system is used for applying adjustable pressure to the fixed disc; the polishing solution supply system is used for conveying a flow-adjustable polishing solution to the processing interface; the central control unit is in communication connection with the two systems and executes edge morphology compensation control logic, specifically, the machining pressure is adjusted in a segmented mode, and the flow of the polishing solution and the pressure are subjected to coupling change. According to the method, the atomic level flatness of the wafer surface is ensured, the edge morphology is accurately controlled, the edge thickening of the epitaxial layer is perfectly counteracted, and the photoetching yield of high-end chip manufacturing is remarkably improved.

The invention discloses a logic chip mask defect detection method, and relates to the technical field of integrated circuit manufacturing, and the method comprises the following steps: S1, constructing a scattering response model of sub-wavelength inorganic particles on the surface of a mask, and constructing a scattering response model of sub-wavelength inorganic particles on the surface of the mask under a set multi-angle polarized light incidence condition; non-linear disturbance influence of inorganic particles with different particle sizes on the reflected light phase in each incident polarization state is simulated, and a scattering response template containing standard phase disturbance characteristics is generated; and S2, based on a scattering response template, carrying out pixel-by-pixel matching analysis on the acquired multi-angle polarization phase diagram on the surface of the mask, identifying a local area matched with the template, and marking the local area as a suspected scattering interference area. According to the method, through construction of the scattering response template and multi-angle polarization consistency analysis, accurate distinguishing of artifacts and real defects is achieved, the recognition precision and stability under complex interference are improved in combination with structure retention type phase reconstruction and dynamic threshold recognition, and mask quality control and photoetching yield improvement are facilitated.

The invention discloses an isomorphic four-core hollow-core anti-resonance optical fiber for an ultraviolet band photoetching process, which belongs to the technical field of optical fiber communication, and comprises an outer cladding and four isomorphic hollow-core light guide units which are arranged in the outer cladding and are distributed at equal intervals in a rectangular array manner, anti-resonance structures are symmetrically arranged in each isomorphic hollow-core light guide unit in the vertical direction and the horizontal direction, and the anti-resonance structures enclose to form an air fiber core; the anti-resonance structure is formed by nesting a plurality of layers of circular and elliptical anti-resonance tubes. And the four isomorphic hollow-core light guide units respectively work in the wavelength ranges of 280 to 380 nm, 220 to 280 nm, 160 to 220 nm and 100 to 160 nm. The isomorphic four-core hollow-core anti-resonance optical fiber structure provided by the invention has a multi-channel transmission capability, and is suitable for multi-beam parallel transmission in a high-resolution ultraviolet lithography system.

The invention relates to a photoetching ordered microcosmic fixed abrasive polishing pad and a preparation method thereof. Compared with the prior art, the method has the advantages that the to-be-photoetched surface of the substrate is photoetched according to the photoetched pattern, so that the plurality of microscopic grinding columns are orderly distributed and formed on the grinding material base according to the preset distribution and arrangement mode, the distribution shape, direction and position of the microscopic grinding columns on the grinding material base are kept unchanged, and regular distribution and uniform distribution can be presented; the distribution and the size of the micro grinding columns can be adjusted according to the photoetching pattern to meet different polishing requirements, then the micro grinding columns of the substrate are compositely filled with the filling body to keep the stability of the micro grinding columns, and the polishing pad can be suitable for the micro level to meet the requirement of the manufacturing procedure below 5nm, so that the production efficiency is improved, and the production cost is reduced. The microcosmic grinding columns are formed through photoetching to replace traditional grinding particles, the chemical stability of the polishing pad during polishing is improved, the removal rate is increased, the surface roughness is reduced, and the polishing effect of the polishing pad on a polishing product is improved.

The invention discloses an electroplating process method for preparing a deep-etching thick metal mask, and belongs to the technical field of micro electro mechanical system electroplating processes. Comprising the following steps: firstly, carrying out photoetching and patterning on the surface of a wafer by using positive photoresist; then, carrying out seed layer sputtering on the wafer subjected to pattern photoetching, and forming a to-be-electroplated region with a preset pattern through a stripping process; then, photoetching is carried out on the to-be-electroplated area through negative photoresist, and a thick photoresist layer with the thickness larger than that of a preset metal coating is formed; and finally, the electroplating area is electroplated, and the metal coating with the preset thickness is obtained. According to the method, the negative photoresist process is adopted, so that the transverse growth of the metal coating is effectively inhibited, the perpendicularity of the side wall of the metal coating is improved, and meanwhile, the damage to the surface of the wafer when the seed layer in the non-electroplating area is removed is avoided. The problems that mushroom-shaped protrusions are easily formed on the edge of a plating layer, crystal grains are coarsened and the like in the electroplating process of an existing electroplating method are solved.

The embodiment of the invention discloses a photoetching mask method and device, and is applied to the field of semiconductors. The method comprises the following steps: acquiring an image to be photoetched, processing the image to be photoetched by using a target network to obtain a coarsened mask image, processing the coarsened mask image again by using an ILT to obtain a target mask image, and performing photolithography masking by using the target mask image. The target network is a conversion network trained based on a training sample, the training sample comprises a sample image and a reference image, and the reference image is an image which is synthesized by ILT and contains sub-resolution auxiliary features. Wherein the coarsened mask image is an image which is similar to an image which is synthesized by an ILT technology and contains sub-resolution auxiliary features. And refining processing is carried out on the coarsened mask image by using an ILT technology to obtain a more accurate target mask image. Therefore, on the basis of ensuring the precision of the photoetching mask, the calculation complexity is reduced, and the efficiency of the photoetching mask is improved.

The invention discloses a chip carrier plate flexible leveling system and a control method, and relates to the technical field of photoetching machine parts and chip production. According to the scheme provided by the invention, a parallelism detection device constructed based on a strain detection device is utilized, and a mapping relation between a strain value and an inter-plate distance is established; during use, a plurality of parallelism detection devices are arranged between a chip carrier plate and a target substrate, high-precision parallelism measurement and feedback adjustment are realized through a mapping relation between strain values and inter-plate distances and based on numerical value differences of strain measurement values, accurate inter-plate parallelism adjustment is realized, and the accuracy of the inter-plate parallelism is improved. The technical problem that an existing leveling system is large in parallelism detection and leveling effect error is solved.

The invention discloses a PEM proton exchange membrane for water electrolysis and a preparation method thereof, and relates to the technical field of water electrolysis. The proton exchange membrane is composed of five layers of structures including a modified sulfonated composite resin layer, an enhancement layer, a water retention layer, a catalyst layer and an anti-permeation layer, the preparation method comprises the following steps: the modified sulfonated composite resin layer is prepared by dispersing perfluorinated sulfonic acid resin and sulfonated lignin in a solvent, coating and drying; the reinforcing layer is prepared by blending a PTFE (Polytetrafluoroethylene) emulsion, a carbon nanotube and a tetrafluoroethylene-hexafluoropropylene copolymer, and then carrying out casting sintering, plasma treatment and hot press molding; the water retention layer is prepared by adopting an electrostatic spinning technology; the catalyst layer is formed by spraying a precursor solution step by step and drying; the anti-permeation layer is prepared through photoetching-etching array construction, resin coating and fluorosilane modification. The prepared proton exchange membrane has excellent mechanical strength, proton conductivity and stability, and is suitable for the field of PEM water electrolysis.

The invention relates to the technical field of semiconductor manufacturing, photoetching alignment and feature recognition, and particularly discloses a photoetching alignment compensation system and method based on feature targeting. An exposed pattern on the surface of a wafer is used as a unique target reference, a built-in visual imaging structure coaxial with a photoetching light path is adopted, a sub-pixel-level feature extraction and dynamic reference real-time updating mechanism is combined, the dynamic deformation of the wafer is calculated, high-frequency compensation of a workpiece table is achieved, and nanoscale overlay precision is achieved. The core improvement of the invention lies in that a light path coaxial visual integrated structure is designed to solve the problem of external imaging parallax; a feature point self-adaptive weighted matching algorithm is provided, and the deformation compensation precision is improved; and constructing a reference map real-time micro-updating mechanism, and eliminating progressive deformation drift of the wafer. The system does not need to manufacture a special physical alignment mark, continuously verify a feature matching state in the whole exposure process and quickly trigger safety protection when the matching degree is abnormal, is suitable for a photoetching alignment process for manufacturing advanced process chips of 3nm and below, has an alignment error of less than or equal to 1.1 nm under a 12-inch wafer standard test condition, reduces the dependence on an ultra-precise workpiece table, and has a good application prospect. The system has the advantages of autonomous controllability, high interference resistance and controllable cost.

The invention discloses a scanning type exposure method and system adopting a parallel digital micromirror array, and relates to the technical field of photoetching exposure and maskless direct writing of mask.The scanning type exposure method comprises the steps that parallel digital micromirror initial mapping is established through a reference target exposure detection registration method; generating a block distortion field parameter table according to the initial mapping of the parallel digital micromirror, determining a micro-mark insertion position based on the block distortion field parameter table, and generating an expected coordinate; performing micro-mark exposure on the expected coordinate position, acquiring imaging data of the inserted micro-mark position, extracting an actual measurement coordinate from the imaging data of the micro-mark position, calculating a residual error by taking the expected coordinate and the actual measurement coordinate as an input difference, and writing the residual error into a residual error set; incremental fitting is carried out according to the residual set, the block distortion field parameter table is updated, and the exposure controller controls the parallel digital micromirror array to remap the pattern according to the updated block distortion field parameter table and triggers exposure. The method provided by the invention has better effects in coordinate mapping consistency and block parameter manageability.

The invention provides a wafer-level cluster coplanar waveguide electrode array, a preparation method and a test system. The coplanar waveguide electrode array comprises an insulating substrate and a plurality of coplanar waveguide electrodes which are arranged in a periodic array; each coplanar waveguide electrode comprises a central transmission section, a probe pad and a gradual transition section; through the design of the central transmission section and the gradual transition section of the coplanar waveguide configuration, the whole-course impedance matching from an external probe to a nano gap is ensured, so that nanosecond and even picosecond-level ultrafast electric pulses can be transmitted to the cluster function unit with extremely low loss and distortion; through overlay and multi-step photoetching and in combination with a negative feedback electromigration technology, a nano gap is manufactured with high success rate, and a cluster function unit is integrated; besides, a test system integrating a coplanar waveguide electrode array and a high-end test instrument is used for exciting and capturing the ultrafast response of a cluster functional unit, and the single write-in time of a cluster device is directly pushed to a subnanosecond level (lt;

The present invention is a resist composition containing a hypervalent iodine compound, a carboxy-group-containing polymer, and a solvent, where the carboxy-group-containing polymer includes a repeating unit of a carboxylic acid derivative, represented by the following formula (1), and the polymer has a dispersity Mw / Mn of 1.30 or less, where Mw is a weight-average molecular weight and Mn is a number-average molecular weight measured by gel permeation chromatography. This can provide: a non-chemically amplified resist composition excellent in sensitivity and limiting resolution in photolithography using a high-energy beam; a laminate including the resist composition; a patterning process using the resist composition; and a method for manufacturing the resist composition.

The invention relates to the technical field of photoetching equipment, in particular to a light offset module, a calibration device and a calibration method.The light offset module comprises an integrated tool, an offset mirror and a first diaphragm; the first end of the integrated tool is provided with a first mounting groove, and the second end is provided with a second mounting groove; the offset mirror is embedded in the first mounting groove, and the first diaphragm is arranged in the second mounting groove; a channel extending along the axis of the first diaphragm is arranged in the integrated tool, light emitted by an autocollimator included in the calibration device sequentially passes through the first diaphragm, the channel and the offset mirror, and the offset mirror enables the light to be reflected to the autocollimator in the preset direction. The device is compact in structure, can accurately compensate and calibrate the offset of the light beam in the light path, facilitates accurate and efficient adjustment, and guarantees the quality and reliability of the light beam output by the light source.

The invention discloses a double-feedback control debugging method of an ultra-precision servo system, and relates to the technical field of semiconductor manufacturing equipment. In order to solve the defects that in the prior art, coupling interference is serious in the debugging process, frequency domain performance optimization is insufficient, filter configuration does not have adaptivity, and an efficient anti-interference debugging mechanism under multi-source disturbance is lacked, the technical scheme provided by the invention comprises the steps that a double-feedback servo system comprising a speed ring and a position ring is constructed; debugging a speed feedback loop, optimizing controller gain parameters based on frequency domain analysis, and outputting speed loop response characteristics; a position feedback loop is debugged, and position loop controller parameters are configured in combination with speed loop response and acceleration sensor signals; the notch filter is automatically adjusted according to the dynamic vibration characteristics; and frequency domain self-adaptive debugging of the double-feedback controller is completed. The method is suitable for servo control debugging work of high-precision motion systems such as a wafer carrying table in semiconductor manufacturing equipment, and is especially suitable for nanoscale positioning scenes such as a photoetching machine and measuring equipment.

Coated nanotubes and bundles of nanotubes are formed into membranes useful in optical assemblies in EUV photolithography systems. These optical assemblies are useful in methods for patterning materials on a semiconductor substrate. Such methods involve generating, in a UV lithography system, UV radiation. The UV radiation is passed through a coating layer of the optical assembly, e.g., a pellicle assembly. The UV radiation that has passed through the coating layer is passed through a matrix of individual nanotubes or matrix of nanotube bundles. UV radiation that passes through the matrix of individual nanotubes or matrix of nanotube bundles is reflected from a mask and received at a semiconductor substrate.

The invention provides a manufacturing method of a type-II superlattice medium-wave infrared focal plane array chip and an infrared detector, and belongs to the field of infrared focal plane array chips. The problem that in the prior art, the surface leakage current of an infrared focal plane array chip is large due to the fact that the mesa etching depth is large is solved. The method comprises the following steps: growing and cleaning an epitaxial material; hard mask deposition, mesa photoetching and etching: obtaining a required mesa pattern on the hard mask through a photoetching technology, then etching an epitaxial material, etching the epitaxial material to form the mesa pattern, the mesa pattern comprising an upper electrode region and a lower electrode region, etching the upper electrode region to the boundary of the barrier layer and the absorption region, and etching the lower electrode region to the boundary of the barrier layer and the absorption region; etching a lower electrode region to the lower ohmic contact layer; manufacturing a metal electrode; a connecting piece is manufactured on the metal electrode to be connected with a reading circuit, and manufacturing of the infrared focal plane array chip is completed; the invention is applied to the II-type superlattice medium-wave infrared detector.

The invention relates to the technical field of radio frequency integrated circuits and advanced semiconductor packaging, in particular to a radio frequency resistor calibration structure based on an RDL process and a manufacturing method, and the radio frequency resistor calibration structure comprises a main resistor module, a redundant resistor module, a laser fine tuning module, a shielding layer module and a temperature compensation module. The main resistor module is sputtered into a film through a low-temperature coefficient metal alloy, and the high-frequency skin effect is reduced by adopting a snakelike or interdigital geometric layout; and the redundant resistor module drives metal ions to migrate through a narrow-neck structure and an electromigration effect, and compensates photoetching line width deviation and uneven sputtering thickness. The laser fine tuning module adjusts a conductive path through selective ablation or annealing of pulse laser, and forms closed-loop calibration in combination with real-time feedback of the metal induction electrode. And the consistency regulation and control of radio frequency circuit parameters of a packaging level are realized.

The invention discloses a method for representing overlay precision measurement accuracy, and belongs to the field of semiconductor manufacturing. The method comprises the following steps: designing a first overlay mark (current layer to current layer) and a second overlay mark (current layer to previous layer); performing first photoetching, measuring a second overlay mark to obtain an optimal correction value, and reworking the wafer; performing second photoetching, exposing the first wafer by using the optimal correction value, and exposing the second wafer by using the optimal correction value superposed with the preset offset; measuring to obtain a first overlay error value (OVL1, the mark on the first wafer), a second overlay error value (OVL2, the mark on the second wafer) and a third overlay error value (OVL3, the marks on the two wafers); on the basis of the OVL1, the OVL2 and the OVL3, the actually-measured overlay offset delta OVL = OVL2-OVL1-OVL3 is calculated, wherein the delta OVL = OVL2-OVL1-OVL3; and comparing the delta OVL with a preset offset to represent the measurement accuracy. The method is non-destructive, efficient, low in cost and high in accuracy.

The invention discloses a mask pattern repairing method, device and product, and relates to the technical field of semiconductor integrated circuits. The mask plate graph repairing method comprises the following steps: carrying out photoetching simulation on a mask plate graph by adopting a photoetching model to obtain a prediction graph corresponding to the mask plate graph; performing photoetching rule inspection on the prediction graph to obtain the position and the type of a defect point violating a photoetching rule in the prediction graph; according to the position of the defect point, determining a to-be-repaired area of the defect point on the mask plate graph; identifying a pattern edge in the to-be-repaired area, and calculating the influence degree of the position change of the pattern edge on the geometric deviation between the predicted pattern and the design layout by adopting the photoetching model; determining an adjustment parameter of the graph edge according to the type and the influence degree of the defect point; and adjusting the pattern edge according to the adjustment parameter to obtain a repaired mask plate pattern. According to the method, the defects in the mask plate graph can be repaired more efficiently.

A photolithography machine with an alignment system is described. The photolithography machine can identify a fiducial pattern provided on a substrate and use the location of the fiducial pattern to align the substrate before exposure. The fiducial pattern can include a plurality of fiducial markings arranged in a specified pattern. A model matching technique can be applied to match the respective individual fiducial markings. A shaping technique can then be used to identify the fiducial pattern based on the matched fiducial markings.

The invention belongs to the field of accelerometers, and particularly relates to a nanometer optical accelerometer and a preparation method thereof.The preparation method comprises the steps that silicon nitride films are deposited on the two faces of a silicon wafer, and a target pattern is formed on the top silicon nitride film on one face through the photoetching technology; etching the silicon nitride film at the target pattern by adopting an etching method to form a hole of the target pattern, then etching the silicon wafer by adopting the etching method, and releasing the silicon nitride film to obtain a suspended surface with a mass block; a suspended surface with a mass block is used as a top chip of the nano accelerometer; a quartz plate of which the two surfaces are respectively plated with a high-reflective film and an antireflection film and the middle is provided with a groove is used as a bottom chip, and the top chip and the bottom chip are integrated to prepare the nano optical accelerometer; only one photoetching process is needed, the micro-nano machining process is simple and compatible with the CMOS process, the cost is lower, and the yield of device preparation is improved.