2677 results about "Photolithography" patented technology

Disclosed are methods and apparatus for qualifying a photolithographic reticle. A reticle inspection tool is used to acquire images at different imaging configurations from each of a plurality of pattern areas of a test reticle. A reticle near field for each of the pattern areas of the test reticle is recovered based on the acquired images from each pattern area of the test reticle. A lithography model is applied to the reticle near field for the test reticle to simulate a plurality of test wafer images, and the simulated test wafer images are analyzed to determine whether the test reticle will likely result in an unstable or defective wafer.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide thick-bottom oxide layer groove MOS structure and a preparation method thereof, the silicon carbide thick-bottom oxide layer groove MOS structure comprises a plurality of parallel MOS cells, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the lightly doped N layer is arranged in the middle of the N drift layer, the arc-shaped contour design with the inclined top is introduced to the two sides, the injection area is accurately controlled through the photoetching technology, the phenomenon that the edge electric field concentration of the N drift layer is effectively dispersed is effectively dispersed, in this way, electric field distribution is more uniform, breakdown voltage is improved, and local electric field concentration is reduced; moreover, the contact between the laterally symmetrical P-layer and the N substrate layer enhances the charge balance capability, and reduces the leakage current.

The invention discloses an implementation method of a multi-chip high-density connection photoetching technology, an implementation method of a photoetching technology for multi-chip interconnection, a chip-level chip interconnection method, a manufacturing method of a mask plate line and photoetching equipment. The implementation method of the multi-chip high-density connection photoetching technology comprises the following steps: selecting a first mask plate to align and expose with a first original pattern unit in a first M * N chipset through a second alignment mark, and transferring a pattern of the first mask plate to an exposure area covering the first original pattern unit; longitudinally moving the substrate by M times of the longitudinal size of the original pattern or transversely moving the substrate by N times of the transverse size of the original pattern to execute alignment exposure, and completing exposure of corresponding areas of other M * N chip groups; and other masks are selected to repeatedly perform exposure on other corresponding pattern units of the first M * N chip set, and longitudinal movement or transverse movement is repeatedly performed to complete exposure of corresponding areas of the corresponding pattern units in other M * N chip sets. According to the scheme, high-density interconnection of multiple chips is realized.

The invention belongs to the technical field of semiconductors, and particularly discloses a photoetching hot spot detection method and system based on a graph neural network. The method comprises the following steps: decomposing each polygonal metal in a layout into rectangles by scanning in the horizontal direction, and taking the rectangles as nodes of the layout; adding an internal edge and an external edge between the rectangles according to a specific rule; the diagonal vertex coordinates of the rectangles are used as node features, the minimum distance between the rectangles represents edge features, and graph representation of the layout is completed; inputting the graph representation of the layout into a message passing layer of a GNN model to perform graph feature extraction, and performing global maximum pooling and global average pooling on each dimension of all node features to obtain global graph representation; and classifying the global graph representation into hotspots and non-hotspots. According to the invention, the accuracy and calculation efficiency of layout hot spot detection can be improved.

The invention provides a manufacturing and processing photoetching method and system of a display panel, and relates to the technical field of photoetching processing. According to the method, the display panel substrate is subjected to cleaning, prime coating and partition division to form an imageable micro-mark covering all exposure partitions, and the thickness and the uniformity are measured after lower-layer supporting glue and upper-layer imaging glue are sequentially formed; carrying out in-situ acquisition and modeling by taking the micro-mark as an imaging object, and generating an exposure correction instruction and an overlapping energy table; performing partition exposure and real-time correction by using a digital micromirror, and completing development to obtain an anti-etching window with a steep side wall; and setting an etching window according to the exposure record and the window quality data, and executing low-damage etching and defect recovery to form stability evaluation data. According to the method, comprehensive improvement of high-precision exposure, pattern consistency and electrical stability is realized.

The invention relates to the technical field of radio frequency integrated circuits and advanced semiconductor packaging, in particular to a multilayer spiral inductor structure based on an RDL process and a preparation method. The preparation method comprises the steps of seed layer deposition, gradient line width coil formation through photoetching and electroplating, alternate dielectric layer deposition, through hole etching to form vertical interconnection copper columns, air bridge forming through a photoresist sacrificial layer process and silicon nitride passivation packaging. Through fan-shaped topological layout, dielectric material collaborative optimization and three-dimensional interconnection structure design, the self-resonant frequency bandwidth is effectively improved, conductor and dielectric loss is reduced, and miniaturization integration and high reliability of high-frequency inductance elements are achieved.

The invention discloses a multilayer three-dimensional stacked circuit board and a preparation method thereof, and the method specifically comprises the steps: obtaining a substrate with a single conductive surface, and carrying out the spraying of a stress buffer layer on the conductive surface of the substrate; covering a layer of insulating material on the stress buffer layer, and forming a pattern insulating layer through photoetching; performing pulse electroplating processing on the exposed pattern of the pattern insulating layer to obtain a first circuit board; silk-screening a flexible connection layer on the pattern bonding pad layer of the first circuit board, and carrying out three-dimensional stacking processing on the flexible connection layer to obtain a second circuit board; and assembling a circuit protection layer on the second circuit board, and processing a stress release groove between the second circuit board and the circuit protection layer to obtain the multi-layer three-dimensional stacked circuit board. Through the design of the stress buffer layer and the stress release groove, interlayer stress can be reduced, circuit board breakage or cracking caused by overlarge interlayer stress is avoided, and the technical problem that large interlayer stress is generated in the circuit board preparation process in the prior art is solved.

The invention relates to an experimental method for manufacturing a through hole by using gray exposure, and aims to realize a through hole structure with a specific inclination angle and depth-to-width ratio through collaborative design of photoetching and etching processes. The method comprises the following steps: determining a through hole angle and a depth-to-width ratio, selecting an etching condition, designing a gray mask structure based on an etching rate selection ratio, implementing gray exposure to obtain a mask pattern, etching, removing residual photoresist and finally forming a target through hole. And by regulating and controlling the selection ratio k of the mask to the substrate material, the inclination angle beta of the through hole and the depth H, designing the gray-scale mask morphology conforming to the target structure. The gray mask can be constructed by adopting gray photoresist or an optical modulation mask, and the inclination morphology parameter, the etching time and the etching rate of the gray mask meet a specific relation, so that high-precision structure control is realized. The method is suitable for the fields of MEMS, micro-optical devices and the like with high requirements on the morphology precision of the through hole, and has the effects of good structure consistency and high process repeatability.

A method for detecting printing defects in a photolithography mask that will print on a wafer when using the photolithography mask in a specific photolithography system to print semiconductor structures on the wafer, the method comprising: acquiring a first aerial image of the photolithography mask using a mask inspection system; generating a second aerial image of the photolithography mask by applying a machine learning model (26) to the first aerial image, wherein the machine learning model is trained to map a first aerial image acquired by a mask inspection system to a second aerial image that emulates the application of the specific photolithography system to the photolithography mask; and detecting printing defects in the photolithography mask by comparing the second aerial image to a reference image.

The invention relates to the technical field of piezoelectric single-crystal filters, in particular to a filter based on a heterogeneous integrated piezoelectric single-crystal thin film and a preparation method, the filter comprises a Si substrate, a dry film, the piezoelectric single-crystal thin film, a SiO2 layer and a Si wafer are sequentially arranged on the Si substrate, metal balls are arranged on the Si wafer, the metal balls are connected with electrodes, and the electrodes are connected with the piezoelectric single-crystal thin film. And the electrode passes through the Si wafer and the SiO2 layer and is connected with the piezoelectric single crystal film. When the filter is prepared, bonding packaging can be performed after a cavity area is etched on a dry film, a resonance area is directly defined through a photoetching process, the influence of etching on the strength of the piezoelectric single crystal film is avoided, a silicon wafer bonding technology can be combined, double-sided packaging can be realized, and batch production is supported; in the process, only the electrode patterning step needs to be adjusted according to the type of the filter, and then the existing MEMS process integration is utilized, so that the preparation of the FBAR and the XBAR on the same production line is realized, the process compatibility is good, and the problems that the existing preparation method is poor in compatibility and is difficult to realize large-scale production are solved.

The invention discloses a layout generation method for load effect compensation and a related device, which are applied to the technical field of photoetching and comprise the following steps: acquiring photomask data; carrying out grid division on the mask graph according to the photomask data, and determining layout density in each grid; comparing the layout density of each grid with a target density, and determining a density difference value corresponding to each grid; determining a virtual graph corresponding to each grid according to the density difference value; and adding a corresponding virtual graph in a layout area corresponding to the grid to form a compensated mask plate graph. By performing grid division on the mask plate graph, calculating the specific layout density in each grid and adding the corresponding virtual graph to the layout area corresponding to the grid according to the difference value between the layout density and the target density, the graph density of the layout area in each grid can be effectively compensated, so that the load effect of each area in the layout is balanced, and the performance of the mask plate is improved. And the etching uniformity is improved.

The invention belongs to the technical field of semiconductors, and relates to a method for electroplating metal on the back surface of a wafer, which comprises the following steps of: forming at least two positioning holes on the edge of the wafer, and forming an electroplating metal layer on the back surface of the wafer through the positioning holes, so that a groove pattern formed between the electroplating metal layer and the wafer is the same as a pattern of a cutting channel on the front surface of the wafer; therefore, the use of a double-sided photoetching machine can be avoided, the equipment cost is obviously reduced, the process flow is simple, the industrial production is easy, the fragment rate is obviously reduced, the production efficiency is obviously improved, and the application prospect is wide.

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the following steps: removing the second pseudo gate structure to expose the second active structure and the gate isolation layer; coating photoresist on the second active structure and the gate isolation layer in the first semiconductor unit, and at least removing the gate isolation layer in the second semiconductor unit through a photoetching process; sequentially removing the first pseudo gate structure and the photoresist to expose the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit and the first active structure and the second active structure in the second semiconductor unit; and forming a first gate structure and a second gate structure based on the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, and simultaneously forming a third gate structure and a fourth gate structure based on the first active structure and the second active structure in the second semiconductor unit.

The embodiment of the invention discloses a photoetching mask updating method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring a target chip layout, constructing a mask pattern and a level set function, and performing photoetching simulation on the mask pattern to obtain a wafer pattern; determining target loss according to the difference between the target chip layout and the wafer pattern, obtaining a first optimization item through a conjugate gradient optimizer, and obtaining a second optimization item through an adaptive moment estimation optimizer; performing attention processing on the target chip layout to obtain a target attention map, and adjusting the second optimization item based on the target attention map; updating the level set function based on the first optimization item and the adjusted second optimization item, and updating the mask pattern based on the updated level set function; according to the embodiment of the invention, while the complexity of the mask pattern is reduced, the pattern error of the mask pattern is effectively reduced, so that the correction precision of the mask pattern is improved, and the method can be widely applied to scenes such as cloud technology and chip manufacturing.

The invention provides an epitaxial wafer edge morphology compensation type wafer double-sided polishing device and method, and belongs to the technical field of semiconductor wafer ultra-precision machining. The polishing main machine comprises an upper fixed disc, a lower fixed disc and a wafer driving mechanism; the pressure loading system is used for applying adjustable pressure to the fixed disc; the polishing solution supply system is used for conveying a flow-adjustable polishing solution to the processing interface; the central control unit is in communication connection with the two systems and executes edge morphology compensation control logic, specifically, the machining pressure is adjusted in a segmented mode, and the flow of the polishing solution and the pressure are subjected to coupling change. According to the method, the atomic level flatness of the wafer surface is ensured, the edge morphology is accurately controlled, the edge thickening of the epitaxial layer is perfectly counteracted, and the photoetching yield of high-end chip manufacturing is remarkably improved.

The present disclosure provides an alignment method and application of a cyanobiphenyl liquid crystal composite doped with an organic donor material. The organic small molecule is doped in the host cyanobiphenyl liquid crystal, and the small molecule donor / cyanobiphenyl liquid crystal mixture is directionally induced to assemble by virtue of the large surface energy difference between the superhydrophobic structured substrate and the superhydrophilic flat substrate. The liquid crystal molecules form a uniform arrangement under the action of the liquid bridge, driving the self-assembly of the small molecule donor to be embedded in the cyanobiphenyl liquid crystal, forming a structure of electron donor-donor, enhancing the conductivity of the liquid crystal composite device, studying the influence of the surface tension of the solvent on the performance of the composite, and giving a direction for the selection of the solvent. Compared with the methods of inducing the alignment of liquid crystal molecules and donor small molecules by using electric fields, magnetic fields, photolithography, capillary methods, etc., this method is simpler and more feasible, easy to transfer, the circuit pattern is easy to design, and has good stability.

The invention relates to the technical field of semiconductors, in particular to a columnar array enhanced photoelectric detector and a preparation method thereof, and the method comprises the following steps: depositing a continuous GaN layer on a substrate through an epitaxial growth method; forming a columnar array structure pattern and an electrode region on the GaN layer through a photoetching process, and removing a part of the GaN layer through an etching process to form an exposed columnar GaN array; depositing a metal electrode layer on two sides of the GaN array, and forming ohmic contact or Schottky contact with the GaN layer to obtain a photoelectric detector; the photoelectric detector is connected with a peripheral circuit to form a complete columnar array enhanced photoelectric detector system, the GaN layer of the columnar array structure is adopted, multiple times of reflection and interference on incident light are achieved, and therefore the detection efficiency and the response speed of the photoelectric detector are improved.

A beam laser diode takes a silicon-based nitride epitaxial wafer as a carrier and comprises a silicon substrate layer, an aluminum nitride layer, a u-type gallium nitride layer, an n-type gallium nitride layer, a quantum well layer, a p-type gallium nitride layer and a SiO2 layer which are sequentially arranged from bottom to top, the p-type electrode is arranged on the p-type gallium nitride layer, and the n-type electrode is arranged on the edge of the n-type gallium nitride layer. A nitride material on a silicon substrate is used for preparing a micro-beam stress sensitive area LD by utilizing photoetching and ICP (Inductively Coupled Plasma) etching processes for emitting light, and after electrification, the laser LD is obtained in the stress sensitive area of the beam. Under the power-on condition, before and after acceleration loading, due to the fact that quantum limits the stark effect, the frequency wavelength of laser changes, and the magnitude of the acceleration can be sensed through difference frequency.

The invention discloses stepping type repeated nanoimprinting equipment, a control method and a control system, and relates to the technical field of semiconductor preparation. An imprinting substrate of the nanoimprinting device comprises a plurality of areas to be imprinted which are arranged in an array mode, the nanoimprinting device comprises a displacement module, a glue dripping module and an imprinting module, the glue dripping module and the imprinting module are arranged in the first horizontal direction in a spaced mode, and the top of the displacement module is used for containing the imprinting substrate. The coining module comprises a coining template matched with the to-be-coined area, the coining template is a photoetching template, and the displacement module is controlled to reciprocate between the glue dripping module and the coining module along a first horizontal direction or move along a second horizontal direction; each reciprocating motion is used for realizing glue dripping and imprinting of an area to be imprinted, and the displacement rate of the displacement module in the first horizontal direction is calculated according to a formula (1). According to the control method disclosed by the invention, the distribution uniformity of the dripping glue and the compatibility of the nano-imprinting equipment and the traditional projection type photoetching process can be improved at the same time.

The invention relates to the technical field of vacuum measurement, in particular to a multi-sealing-cavity MEMS capacitor thin film vacuum gauge, and is characterized in that a silicon substrate is arranged above substrate glass and is bonded with the substrate glass; a pressure sensing film is obtained in the middle of the silicon substrate in a photoetching and dry etching mode; a fixed metal electrode is obtained in the middle of the substrate glass in a photoetching and sputter coating mode; a capacitance gap is formed between the fixed metal electrode and the pressure sensing film; photoetching and corroding the silicon substrate, forming a working sealing cavity above the pressure sensing film, and respectively forming a first cavity and a second cavity above two sides of the pressure sensing film; getter blocks are arranged in the first chamber and the second chamber; and the sealing glass is arranged above the silicon substrate. On the premise that the size of the vacuum gauge is not obviously increased, the multiple chambers are arranged to form the sealing cavity, the air suction capacity is improved, high vacuum obtaining and long-term maintaining performance of the sealing cavity of the vacuum gauge are ensured, and the long-term stability of the vacuum gauge is greatly improved.

The invention relates to a method for manufacturing a MEMS micromirror unit (100) for use in projection exposure systems (1) for photolithography, and to a MEMS micromirror unit (100) manufactured according to this method. The invention also relates to a system for semiconductor technology with a corresponding MEMS micromirror unit (100), and to an electronic component manufactured with such a system. The MEMS micromirror unit (100) comprises a MEMS mirror array assembly (110) with a MEMS mirror array structure (111), a joining structure (115), and an interface element (120) for attaching the MEMS micromirror unit (100) to a higher-level assembly, with a joining structure (125) that interacts with it in a form-fitting manner, and at least one stop surface (121, 121'). The manufacturing process comprises the following steps: a) Measuring the relative position and location of the MEMS mirror array structure (111) to the joining structure (115); b) Adjusting the relative position and / or location of the joining structure (125) of the interface element (120) and the at least one stop surface (121, 121') such that the relative position and location of the MEMS mirror array structure (111) and the at least one stop surface (121, 121') after joining the MEMS mirror array assembly (110) and interface element (120) via the joining structures (115, 125) corresponds to a predetermined position and location.

The invention discloses a logic chip mask defect detection method, and relates to the technical field of integrated circuit manufacturing, and the method comprises the following steps: S1, constructing a scattering response model of sub-wavelength inorganic particles on the surface of a mask, and constructing a scattering response model of sub-wavelength inorganic particles on the surface of the mask under a set multi-angle polarized light incidence condition; non-linear disturbance influence of inorganic particles with different particle sizes on the reflected light phase in each incident polarization state is simulated, and a scattering response template containing standard phase disturbance characteristics is generated; and S2, based on a scattering response template, carrying out pixel-by-pixel matching analysis on the acquired multi-angle polarization phase diagram on the surface of the mask, identifying a local area matched with the template, and marking the local area as a suspected scattering interference area. According to the method, through construction of the scattering response template and multi-angle polarization consistency analysis, accurate distinguishing of artifacts and real defects is achieved, the recognition precision and stability under complex interference are improved in combination with structure retention type phase reconstruction and dynamic threshold recognition, and mask quality control and photoetching yield improvement are facilitated.

The invention relates to a computer implemented method for generating an aerial image of a photolithography mask in an image space, the method comprising: obtaining a representation of a design of the photolithography mask; applying a trained conditional diffusion model that is configured to sequentially revert a stochastic process to an initial sample in order to generate an aerial image of the photolithography mask, wherein the trained conditional diffusion model is conditioned on the representation of the design of the photolithography mask. The invention also relates to computer implemented methods for defect localization, alignment, repair shape generation, training data generation and corresponding systems.

The invention relates to a preparation method of a single-crystal piezoelectric film bulk acoustic resonator, and relates to the field of semiconductor device production processes, and the preparation method comprises the following steps: S1, preparing a single-crystal piezoelectric film and an electrode layer on a first substrate; s2, patterning the single crystal piezoelectric film and the electrode layer; s3, temporarily bonding the supporting slide glass with the first substrate through the adhesion layer; s4, removing the first substrate; s5, etching a photoetching through hole in the thin film body; s6, depositing metal to form a connecting part and a lower electrode; s7, processing a cavity structure on the second substrate; s8, preparing a transition layer on the surface of the second substrate; s9, removing the first part; s10, preparing a bonding layer on the second substrate; s11, processing a communication hole in the bonding layer and removing the second part; s12, bonding the lower electrode and the second substrate; and S13, removing the supporting slide glass and the adhesion layer. The method has the advantages that the bonding material uniformly covers the surface of the second substrate and the cavity structure, weak points are prevented from being formed at the cavity structure, and the reliability and stability of the bonding process are remarkably improved.

The invention discloses a preparation method of an ABM ceramic substrate with a metal through hole, and particularly relates to the technical field of ceramic substrates, a Si3N4 ceramic substrate is prepared through tape casting and hot pressed sintering, a conical stepped through hole is processed by using ultrafast femtosecond laser, the aperture of the through hole is 100-300 [mu] m, and the smoothness of the wall of the through hole is Rat; 1 [mu] m; performing oxygen plasma activation on the inner wall of the through hole to generate a Si-O active group; sputtering a nano titanium transition layer to enhance metal-ceramic interface bonding; the through holes are filled layer by layer through pulse electrochemical deposition, the current density is controlled, and a compact non-porous structure is achieved; in-Sn-Ag low-temperature active brazing filler metal is used, and a surface copper layer is bonded under the assistance of plasma; a fine circuit is formed through photoetching and micro-electroplating, the line width and the spacing of the circuit are the same, and the line width and the spacing of the circuit are both smaller than 20 microns; etching a micro-channel network on the back surface of the substrate by using ultraviolet laser, and filling heat-conducting silicone grease; and finally, carrying out vacuum annealing for 2 hours in an environment with the temperature of 250 DEG C.

The invention discloses an isomorphic four-core hollow-core anti-resonance optical fiber for an ultraviolet band photoetching process, which belongs to the technical field of optical fiber communication, and comprises an outer cladding and four isomorphic hollow-core light guide units which are arranged in the outer cladding and are distributed at equal intervals in a rectangular array manner, anti-resonance structures are symmetrically arranged in each isomorphic hollow-core light guide unit in the vertical direction and the horizontal direction, and the anti-resonance structures enclose to form an air fiber core; the anti-resonance structure is formed by nesting a plurality of layers of circular and elliptical anti-resonance tubes. And the four isomorphic hollow-core light guide units respectively work in the wavelength ranges of 280 to 380 nm, 220 to 280 nm, 160 to 220 nm and 100 to 160 nm. The isomorphic four-core hollow-core anti-resonance optical fiber structure provided by the invention has a multi-channel transmission capability, and is suitable for multi-beam parallel transmission in a high-resolution ultraviolet lithography system.

The invention discloses a Micro-LED (Light Emitting Diode) device self-alignment groove filling and passivating method, which comprises the following steps that a Micro-LED device is provided, and the Micro-LED device comprises array units and grooves between the array units; preparing a dielectric layer on the Micro-LED device, wherein the dielectric layer fills the groove and covers all the array units; curing the dielectric layer; and thinning the whole surface of the dielectric layer by using a mask-free dry etching back etching method until the upper surfaces of all the array units are exposed, and forming a patterned passivation layer at the groove. The whole surface of the dielectric layer is thinned by using a mask-free dry etching back etching method, mask preparation and photoetching are not needed, the height of the dielectric layer can be accurately regulated and controlled through an etching process, and the process is simple; meanwhile, due to the fact that the register step and the developing solution corrosion step are avoided, the technological method can eliminate the problems of interface gaps and table top residues caused by register errors, the graphical passivation layer which is tightly connected can be formed without being restrained by the shape and the size, the etching resistance of the passivation structure is improved, and the device manufacturing yield is improved.

The invention relates to a photoetching ordered microcosmic fixed abrasive polishing pad and a preparation method thereof. Compared with the prior art, the method has the advantages that the to-be-photoetched surface of the substrate is photoetched according to the photoetched pattern, so that the plurality of microscopic grinding columns are orderly distributed and formed on the grinding material base according to the preset distribution and arrangement mode, the distribution shape, direction and position of the microscopic grinding columns on the grinding material base are kept unchanged, and regular distribution and uniform distribution can be presented; the distribution and the size of the micro grinding columns can be adjusted according to the photoetching pattern to meet different polishing requirements, then the micro grinding columns of the substrate are compositely filled with the filling body to keep the stability of the micro grinding columns, and the polishing pad can be suitable for the micro level to meet the requirement of the manufacturing procedure below 5nm, so that the production efficiency is improved, and the production cost is reduced. The microcosmic grinding columns are formed through photoetching to replace traditional grinding particles, the chemical stability of the polishing pad during polishing is improved, the removal rate is increased, the surface roughness is reduced, and the polishing effect of the polishing pad on a polishing product is improved.

The invention discloses an electroplating process method for preparing a deep-etching thick metal mask, and belongs to the technical field of micro electro mechanical system electroplating processes. Comprising the following steps: firstly, carrying out photoetching and patterning on the surface of a wafer by using positive photoresist; then, carrying out seed layer sputtering on the wafer subjected to pattern photoetching, and forming a to-be-electroplated region with a preset pattern through a stripping process; then, photoetching is carried out on the to-be-electroplated area through negative photoresist, and a thick photoresist layer with the thickness larger than that of a preset metal coating is formed; and finally, the electroplating area is electroplated, and the metal coating with the preset thickness is obtained. According to the method, the negative photoresist process is adopted, so that the transverse growth of the metal coating is effectively inhibited, the perpendicularity of the side wall of the metal coating is improved, and meanwhile, the damage to the surface of the wafer when the seed layer in the non-electroplating area is removed is avoided. The problems that mushroom-shaped protrusions are easily formed on the edge of a plating layer, crystal grains are coarsened and the like in the electroplating process of an existing electroplating method are solved.

A method for preparing a hybrid filter on a chip with IPD and FBAR, includes: preparing a leakage isolation layer on a supporting substrate by deposition; obtaining an inductor layer on the leakage isolation layer, leaving a window at a bottom of a groove surrounding a cross section of a TGV inductor stack on a mask, and patterning an inductor metal simultaneously; forming a first insulating layer on the inductor metal, and forming lead through holes by photolithography; repeating steps and alternately to obtain a three-layer stacked TGV inductor; depositing a second insulating layer on the TGV inductor; depositing two capacitor layers on the second insulating layer, and depositing a third insulating layer between the two capacitor layers to form an MIM capacitor; and preparing a BAW resonator on the MIM capacitor, and connecting the TGV inductor, the MIM capacitor and the BAW resonator through the lead through holes.