8643 results about "Photolithography" patented technology

In a method of determining the focus of a lithographic apparatus used in a lithographic process on a substrate, the lithographic process is used to form a structure on the substrate, the structure having at least one feature which has an asymmetry in the printed profile which varies as a function of the focus of the lithographic apparatus on the substrate. A first image of the periodic structure is formed and detected while illuminating the structure with a first beam of radiation. The first image is formed using a first part of non-zero order diffracted radiation. A second image of the periodic structure is foamed and detected while illuminating the structure with a second beam of radiation. The second image is formed using a second part of the non-zero order diffracted radiation which is symmetrically opposite to the first part in a diffraction spectrum. The ratio of the intensities of the measured first and second portions of the spectra is determined and used to determine the asymmetry in the profile of the periodic structure and/or to provide an indication of the focus on the substrate. In the same instrument, an intensity variation across the detected portion is determined as a measure of process-induced variation across the structure. A region of the structure with unwanted process variation can be identified and excluded from a measurement of the structure.

Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

A liquid immersion photolithography system includes an exposure system that exposes a substrate with electromagnetic radiation and includes a projection optical system that focuses the electromagnetic radiation on the substrate. A liquid supply system provides liquid flow between the projection optical system and the substrate. An optional plurality of micronozzles are arranged around the periphery of one side of the projection optical system so as to provide a substantially uniform velocity distribution of the liquid flow in an area where the substrate is being exposed.

Optical Projection System and Method for Photolithography. A lithographic immersion projection system and method for projecting an image at high resolution over a wide field of view. The projection system and method include a final lens which decreases the marginal ray angle of the optical path before light passes into the immersion liquid to impinge on the image plane.

A heat treatment jig for supporting silicon semiconductor substrates by contacting, being loaded onto a heat treatment boat in a vertical heat treatment furnace, comprises; the configuration of a ring or a disc structure with the wall thickness between 1.5 and 6.0 mm; the deflection displacement of 100 μm or less at contact region in loaded condition; the outer diameter which is 65% or more of the diameter of said substrate; and the surface roughness (Ra) of between 1.0 and 100 μm at the contact region. The use of said jig enables to effectively retard the slip generation and to avoid the growth hindrance of thermally oxidized film at the back surface of said substrate, diminishing the surface steps causing the defocus in photolithography step in device fabrication process, thereby enabling to maintain high quality of silicon semiconductor substrates and to substantially enhance the device yield.

In a mask pattern forming method, a resist film is formed over a thin film, the resist film is processed into resist patterns having a predetermined pitch by photolithography, slimming of the resist patterns is performed, and an oxide film is formed on the thin film and the resist patterns after an end of the slimming step in a film deposition apparatus by supplying a source gas and an oxygen radical or an oxygen-containing gas. In the mask pattern forming method, the slimming and the oxide film forming are continuously performed in the film deposition apparatus.

Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed patterns of crossing elongate features with pillars at the intersections. Spacers are simultaneously applied to sidewalls of both sets of crossing lines to produce a pitch-doubled grid pattern. The pillars facilitate rows of spacers bridging columns of spacers.

A system and a method for creating a focus-exposure model of a lithography process are disclosed. The system and the method utilize calibration data along multiple dimensions of parameter variations, in particular within an exposure-defocus process window space. The system and the method provide a unified set of model parameter values that result in better accuracy and robustness of simulations at nominal process conditions, as well as the ability to predict lithographic performance at any point continuously throughout a complete process window area without a need for recalibration at different settings. With a smaller number of measurements required than the prior-art multiple-model calibration, the focus-exposure model provides more predictive and more robust model parameter values that can be used at any location in the process window.

A patterning method comprises a step for forming a first film on a substrate, a step for forming a multilayer film including a resist film on the first film, a step for patterning the resist film by photolithography to form a patterned resist film having a predetermined pattern, a step for forming an silicon oxide film different from the first film on the patterned resist film and the first film by supplying a first gas containing an organic silicon and a second gas containing an activated oxygen species alternately to the substrate, a step for etching the silicon oxide film to form a sidewall spacer on the sidewall of the patterned resist film, a step for removing the patterned resist film, and a step for processing the first film by using the sidewall spacer as a mask.

The present invention relates to a cross-linker for photoresist compositions which is suitable for a photolithography process using KrF (248 mn), ArF (193 mn), E-beam, ion beam or EUV light sources. Preferred cross-linkers, according to the present invention, comprise a copolymer of (i) a compound represented by following Chemical Formula 1 and/or (ii) one or more compound(s) selected from the group consisting of acrylic acid, methacrylic acid and maleic anhydride. ##STR1## wherein, R.sub.1 and R.sub.2 individually represent straight or branched C.sub.1-10 alkyl, straight or branched C.sub.1-10 ester, straight or branched C.sub.1-10 ketone, straight or branched C.sub.1-10 carboxylic acid, straight or branched C.sub.1-10 acetal, straight or branched C.sub.1-10 alkyl including at least one hydroxyl group, straight or branched C.sub.1-10 ester including at least one hydroxyl group, straight or branched C.sub.1-10 ketone including at least one hydroxyl group, straight or branched C.sub.1-10 carboxylic acid including at least one hydroxyl group, and straight or branched C.sub.1-10 acetal including at least one hydroxyl group; and R.sub.3 represents hydrogen or methyl.

The invention described herein is directed towards spin-on carbon materials comprising polyamic acid compositions and a crosslinker in a solvent system. The materials are useful in trilayer photolithography processes. Films made with the inventive compositions are not soluble in solvents commonly used in lithographic materials, such as, but not limited to PGME, PGMEA, and cyclohexanone. However, the films can be dissolved in developers commonly used in photolithography. In one embodiment, the films can be heated at high temperatures to improve the thermal stability for high temperature processing. Regardless of the embodiment, the material can be applied to a flat/planar or patterned surface. Advantageously, the material exhibits a wiggling resistance during pattern transfer to silicon substrate using fluorocarbon etch.

Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form sumperimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.

To provide a semiconductor device having a circuit with high operating performance and high reliability, and improve the reliability of the semiconductor device, thereby improving the reliability of an electronic device having the same. The aforementioned object is achieved by combining a step of crystallizing a semiconductor layer by irradiation with continuous wave laser beams or pulsed laser beams with a repetition rate of 10 MHz or more, while scanning in one direction; a step of photolithography with the use of a photomask or a leticle including an auxiliary pattern which is formed of a diffraction grating pattern or a semi-transmissive film having a function of reducing the light intensity; and a step of performing oxidation, nitridation, or surface-modification to the surface of the semiconductor film, an insulating film, or a conductive film, with high-density plasma with a low electron temperature.

Embodiments of the present invention pertain to methods of forming patterned features on a substrate having an increased density (i.e. reduced pitch) as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask while also allowing both the width of the patterned features and spacing (trench width) between the patterned features to vary within an integrated circuit.

Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

A semiconductor substrate is formed into a regular hexagon or a shape similar to the regular hexagon. The semiconductor substrate is bonded to and separated from a large-area substrate. Moreover, layout is designed so that a boundary of bonded semiconductors is located in a region which is removed by etching when patterning is performed by photolithography or the like.

A method of designing an integrated circuit is provided in which the design layout is optimized using a process model until the design constraints are satisfied by the image contours simulated by the process model. The process model used in the design phase need not be as accurate as the lithographic model used in preparing the lithographic mask layout during data prep. The resulting image contours are then included with the modified, optimized design layout to the data prep process, in which the mask layout is optimized using the lithographic process model, for example, including RET and OPC. The mask layout optimization matches the images simulated by the lithographic process model with the image contours generated during the design phase, which ensures that the design and manufacturability constraints specified by the designer are satisfied by the optimized mask layout.

An all-refelctive optical system for a projection photolithography camera has a source of EUV radiation, a wafer and a mask to be imaged on the wafer. The optical system includes a first concave mirror, a second mirror, a third convex mirror, a fourth concave mirror, a fifth convex mirror and a sixth concave mirror. The system is configured such that five of the six mirrors receives a chief ray at an incidence angle less than substantially 12 DEG , and each of the six mirrors receives a chief ray at an incidence angle of less than substantially 15 DEG . Four of the six reflecting surfaces have an aspheric departure of less than substantially 7 mu m. Five of the six reflecting surfaces have an aspheric departure of less than substantially 14 mu m. Each of the six refelecting surfaces has an aspheric departure of less than 16.0 mu m.

A method of forming fine patterns in a semiconductor device includes forming narrow-width patterns in a first region and wide-width patterns in a second region, where the widths of the narrow-width patterns are smaller than the resolution limitations in a photolithography process used to make the semiconductor device. The first and second regions may comprise cell array regions, with memory cells in the first region and peripheral circuits for operating the memory cells in the second region. The semiconductor device can be, for example, a NAND FLASH memory device. The semiconductor memory device can be variously classified according to the type of memory cells to be integrated in the cell array region, e.g., a DRAM, an SRAM, a PRAM, a RRAM, an MRAM, and a FRAM. In other embodiments, a MEMS device, an optoelectronic device, or a processor, such as CPU or DSP, may be provided on the semiconductor substrate.