1466 results about "Photolithography" patented technology

Disclosed are methods and apparatus for qualifying a photolithographic reticle. A reticle inspection tool is used to acquire images at different imaging configurations from each of a plurality of pattern areas of a test reticle. A reticle near field for each of the pattern areas of the test reticle is recovered based on the acquired images from each pattern area of the test reticle. A lithography model is applied to the reticle near field for the test reticle to simulate a plurality of test wafer images, and the simulated test wafer images are analyzed to determine whether the test reticle will likely result in an unstable or defective wafer.

The invention provides a manufacturing and processing photoetching method and system of a display panel, and relates to the technical field of photoetching processing. According to the method, the display panel substrate is subjected to cleaning, prime coating and partition division to form an imageable micro-mark covering all exposure partitions, and the thickness and the uniformity are measured after lower-layer supporting glue and upper-layer imaging glue are sequentially formed; carrying out in-situ acquisition and modeling by taking the micro-mark as an imaging object, and generating an exposure correction instruction and an overlapping energy table; performing partition exposure and real-time correction by using a digital micromirror, and completing development to obtain an anti-etching window with a steep side wall; and setting an etching window according to the exposure record and the window quality data, and executing low-damage etching and defect recovery to form stability evaluation data. According to the method, comprehensive improvement of high-precision exposure, pattern consistency and electrical stability is realized.

A method for detecting printing defects in a photolithography mask that will print on a wafer when using the photolithography mask in a specific photolithography system to print semiconductor structures on the wafer, the method comprising: acquiring a first aerial image of the photolithography mask using a mask inspection system; generating a second aerial image of the photolithography mask by applying a machine learning model (26) to the first aerial image, wherein the machine learning model is trained to map a first aerial image acquired by a mask inspection system to a second aerial image that emulates the application of the specific photolithography system to the photolithography mask; and detecting printing defects in the photolithography mask by comparing the second aerial image to a reference image.

The invention discloses a layout generation method for load effect compensation and a related device, which are applied to the technical field of photoetching and comprise the following steps: acquiring photomask data; carrying out grid division on the mask graph according to the photomask data, and determining layout density in each grid; comparing the layout density of each grid with a target density, and determining a density difference value corresponding to each grid; determining a virtual graph corresponding to each grid according to the density difference value; and adding a corresponding virtual graph in a layout area corresponding to the grid to form a compensated mask plate graph. By performing grid division on the mask plate graph, calculating the specific layout density in each grid and adding the corresponding virtual graph to the layout area corresponding to the grid according to the difference value between the layout density and the target density, the graph density of the layout area in each grid can be effectively compensated, so that the load effect of each area in the layout is balanced, and the performance of the mask plate is improved. And the etching uniformity is improved.

The embodiment of the invention discloses a photoetching mask updating method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring a target chip layout, constructing a mask pattern and a level set function, and performing photoetching simulation on the mask pattern to obtain a wafer pattern; determining target loss according to the difference between the target chip layout and the wafer pattern, obtaining a first optimization item through a conjugate gradient optimizer, and obtaining a second optimization item through an adaptive moment estimation optimizer; performing attention processing on the target chip layout to obtain a target attention map, and adjusting the second optimization item based on the target attention map; updating the level set function based on the first optimization item and the adjusted second optimization item, and updating the mask pattern based on the updated level set function; according to the embodiment of the invention, while the complexity of the mask pattern is reduced, the pattern error of the mask pattern is effectively reduced, so that the correction precision of the mask pattern is improved, and the method can be widely applied to scenes such as cloud technology and chip manufacturing.

The invention provides an epitaxial wafer edge morphology compensation type wafer double-sided polishing device and method, and belongs to the technical field of semiconductor wafer ultra-precision machining. The polishing main machine comprises an upper fixed disc, a lower fixed disc and a wafer driving mechanism; the pressure loading system is used for applying adjustable pressure to the fixed disc; the polishing solution supply system is used for conveying a flow-adjustable polishing solution to the processing interface; the central control unit is in communication connection with the two systems and executes edge morphology compensation control logic, specifically, the machining pressure is adjusted in a segmented mode, and the flow of the polishing solution and the pressure are subjected to coupling change. According to the method, the atomic level flatness of the wafer surface is ensured, the edge morphology is accurately controlled, the edge thickening of the epitaxial layer is perfectly counteracted, and the photoetching yield of high-end chip manufacturing is remarkably improved.

The invention discloses a logic chip mask defect detection method, and relates to the technical field of integrated circuit manufacturing, and the method comprises the following steps: S1, constructing a scattering response model of sub-wavelength inorganic particles on the surface of a mask, and constructing a scattering response model of sub-wavelength inorganic particles on the surface of the mask under a set multi-angle polarized light incidence condition; non-linear disturbance influence of inorganic particles with different particle sizes on the reflected light phase in each incident polarization state is simulated, and a scattering response template containing standard phase disturbance characteristics is generated; and S2, based on a scattering response template, carrying out pixel-by-pixel matching analysis on the acquired multi-angle polarization phase diagram on the surface of the mask, identifying a local area matched with the template, and marking the local area as a suspected scattering interference area. According to the method, through construction of the scattering response template and multi-angle polarization consistency analysis, accurate distinguishing of artifacts and real defects is achieved, the recognition precision and stability under complex interference are improved in combination with structure retention type phase reconstruction and dynamic threshold recognition, and mask quality control and photoetching yield improvement are facilitated.

The invention relates to a photoetching ordered microcosmic fixed abrasive polishing pad and a preparation method thereof. Compared with the prior art, the method has the advantages that the to-be-photoetched surface of the substrate is photoetched according to the photoetched pattern, so that the plurality of microscopic grinding columns are orderly distributed and formed on the grinding material base according to the preset distribution and arrangement mode, the distribution shape, direction and position of the microscopic grinding columns on the grinding material base are kept unchanged, and regular distribution and uniform distribution can be presented; the distribution and the size of the micro grinding columns can be adjusted according to the photoetching pattern to meet different polishing requirements, then the micro grinding columns of the substrate are compositely filled with the filling body to keep the stability of the micro grinding columns, and the polishing pad can be suitable for the micro level to meet the requirement of the manufacturing procedure below 5nm, so that the production efficiency is improved, and the production cost is reduced. The microcosmic grinding columns are formed through photoetching to replace traditional grinding particles, the chemical stability of the polishing pad during polishing is improved, the removal rate is increased, the surface roughness is reduced, and the polishing effect of the polishing pad on a polishing product is improved.

The invention discloses an electroplating process method for preparing a deep-etching thick metal mask, and belongs to the technical field of micro electro mechanical system electroplating processes. Comprising the following steps: firstly, carrying out photoetching and patterning on the surface of a wafer by using positive photoresist; then, carrying out seed layer sputtering on the wafer subjected to pattern photoetching, and forming a to-be-electroplated region with a preset pattern through a stripping process; then, photoetching is carried out on the to-be-electroplated area through negative photoresist, and a thick photoresist layer with the thickness larger than that of a preset metal coating is formed; and finally, the electroplating area is electroplated, and the metal coating with the preset thickness is obtained. According to the method, the negative photoresist process is adopted, so that the transverse growth of the metal coating is effectively inhibited, the perpendicularity of the side wall of the metal coating is improved, and meanwhile, the damage to the surface of the wafer when the seed layer in the non-electroplating area is removed is avoided. The problems that mushroom-shaped protrusions are easily formed on the edge of a plating layer, crystal grains are coarsened and the like in the electroplating process of an existing electroplating method are solved.

The invention relates to the technical field of semiconductor manufacturing, photoetching alignment and feature recognition, and particularly discloses a photoetching alignment compensation system and method based on feature targeting. An exposed pattern on the surface of a wafer is used as a unique target reference, a built-in visual imaging structure coaxial with a photoetching light path is adopted, a sub-pixel-level feature extraction and dynamic reference real-time updating mechanism is combined, the dynamic deformation of the wafer is calculated, high-frequency compensation of a workpiece table is achieved, and nanoscale overlay precision is achieved. The core improvement of the invention lies in that a light path coaxial visual integrated structure is designed to solve the problem of external imaging parallax; a feature point self-adaptive weighted matching algorithm is provided, and the deformation compensation precision is improved; and constructing a reference map real-time micro-updating mechanism, and eliminating progressive deformation drift of the wafer. The system does not need to manufacture a special physical alignment mark, continuously verify a feature matching state in the whole exposure process and quickly trigger safety protection when the matching degree is abnormal, is suitable for a photoetching alignment process for manufacturing advanced process chips of 3nm and below, has an alignment error of less than or equal to 1.1 nm under a 12-inch wafer standard test condition, reduces the dependence on an ultra-precise workpiece table, and has a good application prospect. The system has the advantages of autonomous controllability, high interference resistance and controllable cost.

The invention discloses a scanning type exposure method and system adopting a parallel digital micromirror array, and relates to the technical field of photoetching exposure and maskless direct writing of mask.The scanning type exposure method comprises the steps that parallel digital micromirror initial mapping is established through a reference target exposure detection registration method; generating a block distortion field parameter table according to the initial mapping of the parallel digital micromirror, determining a micro-mark insertion position based on the block distortion field parameter table, and generating an expected coordinate; performing micro-mark exposure on the expected coordinate position, acquiring imaging data of the inserted micro-mark position, extracting an actual measurement coordinate from the imaging data of the micro-mark position, calculating a residual error by taking the expected coordinate and the actual measurement coordinate as an input difference, and writing the residual error into a residual error set; incremental fitting is carried out according to the residual set, the block distortion field parameter table is updated, and the exposure controller controls the parallel digital micromirror array to remap the pattern according to the updated block distortion field parameter table and triggers exposure. The method provided by the invention has better effects in coordinate mapping consistency and block parameter manageability.

The invention provides a wafer-level cluster coplanar waveguide electrode array, a preparation method and a test system. The coplanar waveguide electrode array comprises an insulating substrate and a plurality of coplanar waveguide electrodes which are arranged in a periodic array; each coplanar waveguide electrode comprises a central transmission section, a probe pad and a gradual transition section; through the design of the central transmission section and the gradual transition section of the coplanar waveguide configuration, the whole-course impedance matching from an external probe to a nano gap is ensured, so that nanosecond and even picosecond-level ultrafast electric pulses can be transmitted to the cluster function unit with extremely low loss and distortion; through overlay and multi-step photoetching and in combination with a negative feedback electromigration technology, a nano gap is manufactured with high success rate, and a cluster function unit is integrated; besides, a test system integrating a coplanar waveguide electrode array and a high-end test instrument is used for exciting and capturing the ultrafast response of a cluster functional unit, and the single write-in time of a cluster device is directly pushed to a subnanosecond level (lt;

The present invention is a resist composition containing a hypervalent iodine compound, a carboxy-group-containing polymer, and a solvent, where the carboxy-group-containing polymer includes a repeating unit of a carboxylic acid derivative, represented by the following formula (1), and the polymer has a dispersity Mw / Mn of 1.30 or less, where Mw is a weight-average molecular weight and Mn is a number-average molecular weight measured by gel permeation chromatography. This can provide: a non-chemically amplified resist composition excellent in sensitivity and limiting resolution in photolithography using a high-energy beam; a laminate including the resist composition; a patterning process using the resist composition; and a method for manufacturing the resist composition.

The invention discloses a double-feedback control debugging method of an ultra-precision servo system, and relates to the technical field of semiconductor manufacturing equipment. In order to solve the defects that in the prior art, coupling interference is serious in the debugging process, frequency domain performance optimization is insufficient, filter configuration does not have adaptivity, and an efficient anti-interference debugging mechanism under multi-source disturbance is lacked, the technical scheme provided by the invention comprises the steps that a double-feedback servo system comprising a speed ring and a position ring is constructed; debugging a speed feedback loop, optimizing controller gain parameters based on frequency domain analysis, and outputting speed loop response characteristics; a position feedback loop is debugged, and position loop controller parameters are configured in combination with speed loop response and acceleration sensor signals; the notch filter is automatically adjusted according to the dynamic vibration characteristics; and frequency domain self-adaptive debugging of the double-feedback controller is completed. The method is suitable for servo control debugging work of high-precision motion systems such as a wafer carrying table in semiconductor manufacturing equipment, and is especially suitable for nanoscale positioning scenes such as a photoetching machine and measuring equipment.

The invention discloses a mask pattern repairing method, device and product, and relates to the technical field of semiconductor integrated circuits. The mask plate graph repairing method comprises the following steps: carrying out photoetching simulation on a mask plate graph by adopting a photoetching model to obtain a prediction graph corresponding to the mask plate graph; performing photoetching rule inspection on the prediction graph to obtain the position and the type of a defect point violating a photoetching rule in the prediction graph; according to the position of the defect point, determining a to-be-repaired area of the defect point on the mask plate graph; identifying a pattern edge in the to-be-repaired area, and calculating the influence degree of the position change of the pattern edge on the geometric deviation between the predicted pattern and the design layout by adopting the photoetching model; determining an adjustment parameter of the graph edge according to the type and the influence degree of the defect point; and adjusting the pattern edge according to the adjustment parameter to obtain a repaired mask plate pattern. According to the method, the defects in the mask plate graph can be repaired more efficiently.

According to the image sensor manufacturing method based on the guided self-assembly technology, the guided self-assembly technology is applied to a deep groove patterning process on the back face of a wafer and is combined with a photoetching technology, so that compared with a traditional deep groove patterning process utilizing a PTD or NTD photoetching technology, the deep groove patterning process has the advantages that the deep groove patterning process is simplified; according to the invention, the resolution limit of the photoetching technology can be broken through, the pixel pitch can be reduced, the cost advantage and the pixel density can be improved, the pixel resolution can be greatly improved, the edge roughness of the deep trench isolation pattern of the pixel can be improved, and the signal crosstalk between the adjacent pixels can be reduced.

The invention provides a photoetching overlay pattern generation method and system for semiconductor manufacturing, and relates to the technical field of semiconductor photoetching. According to the method, an overlay performance target, measurement tool parameters and process parameters are unified as nominal conditions, layout dimensions and manufacturing constraints are unified as a constraint library, and a process chain joint model covering exposure, development, etching and measurement links is established; simulation and multi-target iterative optimization are carried out on the parameterized overlay mark under nominal conditions and disturbance conditions, an optimal mark with high measurement sensitivity, low measurement uncertainty and small system deviation is obtained, and association with design input is realized to support production chip casting and measurement.

The invention relates to the related technical field of semiconductors, in particular to a chip processing production line monitoring method and system, and the method comprises the steps: collecting photoetching process monitoring data; setting a feature matrix; determining a focusing window boundary; configuring a focal length offset compensation amount based on the feature matrix in combination with a focusing window boundary and photolithographic process monitoring data; and determining a deviation amplitude score by using an edge placement error model to perform graded reminding. The technical problems that window boundary definition monitored by a chip processing production line depends on experience to set a fixed standard, focal length offset cannot be effectively compensated, and the risk that edge placement errors exceed the standard exists are solved, and coupling analysis of an optical proximity effect and a process window is carried out in a mask layer, a lens layer and a photoresist layer and a feature matrix is constructed, so that the edge placement error is accurately determined. And the compensation parameters and the error trend are dynamically matched, the focal length offset compensation precision is improved, an edge placement error model is used for determining a deviation amplitude score and carrying out graded reminding, and the technical effect of abnormity processing timeliness is enhanced.

A single integrated circuit is provided, comprising a memory region and a non-memory region. The memory region comprises a first conductive structure, a memory element disposed upon the first conductive structure, and a first via disposed upon the memory element. The non-memory region comprises a second conductive structure, and a second via disposed upon the second conductive structure. The first conductive structure and the second conductive structure are formed by a first photolithography process comprising a first photomask, and the first conductive structure is configured to be a first bottom electrode in the memory region. The first via and the second via are formed by a third photolithography process comprising a third photomask. The first photomask and the third photomask comprise a same pattern.

The invention belongs to the technical field of flexible electronic materials, and particularly relates to an adsorption layer for promoting patterning and separation of liquid metal, a preparation method of the adsorption layer and a recoverable flexible liquid metal sensing device. The metal organic framework material-polymer is used as an adsorption layer for promoting patterning and separation of the liquid metal, and the characteristics that the liquid metal is adsorbed on the surface of the polymer and repelled on the surface of the metal organic framework material are achieved by adjusting surface functional groups and roughness. And meanwhile, high-precision patterning is carried out on the polymer through a 3D printing or photoetching technology, and a high-precision liquid metal pattern is obtained under selective adsorption of the liquid metal. Besides, according to the dissolution characteristics of the metal-organic framework material and the polymer, a two-step recovery method for dissolving the polymer, separating the liquid metal from the polymer and then dissolving and separating the metal-organic framework material is designed, and the scheme of the invention is beneficial to the integration and sustainable development of the liquid metal-based electronic device.

The invention belongs to the field of integrated circuit design, and particularly relates to an integrated circuit photoetching hot spot detection method, a storage medium and equipment. The method comprises the following steps: constructing a layout classification model for identifying whether an input layout contains photoetching hot spots or not; the layout classification model sequentially comprises a front feature extraction module, a plurality of rear feature extraction modules, a feature fusion module and a full connection layer. The front feature extraction module is composed of common convolution, degrouping convolution, interactive convolution and an attention layer. The post-feature extraction module is composed of an enhanced interaction layer and an attention layer. Performing data enhancement on the hot-spot layout and sampling the non-hot-spot layout to form a balanced data set; and training the layout classification model by using the BCE loss introduced with label smoothing as a loss function. And inputting the slice image of the original layout into the trained layout classification model to realize photoetching hot spot detection. According to the invention, the problem that the detection precision and the false alarm rate are unbalanced in the existing scheme is solved.

The invention relates to a method (30) for registering structures in at least one image (26, 26', 26'', 26''') of a photolithography mask (14) obtained by an optical system (10, 10') with a resolution limit, wherein the optical system (10, 10') comprises an illumination optics unit (11) with an optical element (22) arranged in an illumination beam path (21) of the illumination optics unit (11), wherein the illumination optics unit (11) is configured to illuminate the photolithography mask (14) with spatially modulated illumination, and an imaging beam path (19), wherein the method (30) comprises: providing at least one image (26, 26', 26'', 26''') of a photolithography mask (14) that is captured by the optical system (10, 10') with spatially modulated illumination;Registering structures in the at least one provided image (26) with corresponding structures in a reference image (48) of the photolithography mask (14).;

The invention provides an automatic focusing device, an automatic focusing method and wafer quantity detection equipment, and belongs to the field of semiconductor optics, and the device comprises a light source, an illumination dimming mirror group, a beam splitting element, a reflector, an objective lens, a distance measurement dimming mirror group, a focal plane measurement unit, a dispersion compensation mirror group and a focusing compensation mirror group; the focal plane measuring unit can measure the focal planes of a plurality of process layers of the wafer and determine the focal length from the target focal plane to the objective lens, thereby realizing automatic focusing. According to the scheme, the dispersion compensation and objective lens measurement combined design is adopted, high precision and a large measurement range are achieved through dispersion curve control, specific quantity detection scanning can be conducted on a specific process layer of a wafer through the focusing compensation lens set, and the measurement precision is improved. And the method is convenient to popularize and apply in equivalent detection scenes of wafer nanoscale key dimensions, defects, overlay alignment and the like and in the photoetching processing field.

The invention discloses a photoetching model modeling method and a computer program product, and relates to the technical field of semiconductors. The photoetching model modeling method comprises the following steps: integrating links of model parameter search, correction parameter search, model calibration and the like of an optical parameter group and a grid parameter group into a standardized modeling process capable of being automatically executed, so that repeated manual parameter setting is not needed, and the manual operation cost is reduced. In the standardized modeling process, firstly, model parameter search with high importance is executed, then, under the constraint of a target optical parameter group and a target grid parameter group, different correction parameter groups are traversed, and the correction search condition is achieved by taking the pattern deviation of a photoetching model output pattern and a measurement reference file under the correction parameter groups as a target. And the target correction parameter groups are screened, and the target photoetching model obtained based on calibration of the determined parameter groups is high in simulation precision and reliability.

The invention provides an off-axis illumination photoetching mask, a preparation method thereof and a photoetching system, which can be applied to the technical field of micro-nano machining and advanced photoetching, and the photoetching mask comprises a mask substrate comprising a first surface and a second surface which are oppositely arranged; the photoetching mask pattern structure is located on the second surface of the mask substrate; the light incident part is located on the first surface of the mask substrate, and the light incident part comprises a plurality of light incident units which are periodically arranged; wherein the light incident unit is provided with a V-shaped structure in the direction perpendicular to the first surface, the V-shaped structure gradually shrinks inwards from the first surface to the second surface, and each V-shaped structure comprises two slope surfaces which are connected with each other; the light incident part further comprises a band-pass filtering film which at least covers the two slope faces of the V-shaped structure.

The invention provides an infrared detector deep mesa etching process based on three layers of masks and an infrared detector, and belongs to the field of infrared detector mesa etching. The process comprises the following steps: spin-coating a stress buffer layer on the surface of a superlattice epitaxial layer, and curing and forming; depositing a hard mask serving as an etching barrier layer; depositing an inorganic oxide; spin-coating photoresist to form a composite patterned top layer, and then forming a mesa pattern through a photoetching process; taking the mesa pattern as a mask, and transferring the mesa pattern to the hard mask through reactive ion etching; etching the stress buffer layer by adopting plasma until the surface of the superlattice epitaxial layer is exposed; the three layers of masks are used as blocking, deep etching is carried out through inductively coupled plasma, and the etching depth is 5.6-6 microns; a post-processing step; according to the process provided by the invention, high-quality and high-aspect-ratio mesa etching can be realized on the premise of not introducing extra pollution and remarkably increasing the cost, and the process is suitable for preparing a deep-mesa and high-aspect-ratio device.

The invention relates to a preparation method of quartz glass for photoetching, and belongs to the technical field of quartz glass. The preparation method comprises the following steps: S1, carrying out silicon dioxide loose body deposition by adopting VAD deposition equipment; in the deposition process, the silicon dioxide loose body does autorotation motion and revolution motion; s2, sintering the silicon dioxide loose body by adopting a sintering furnace to obtain a quartz glass ingot; s3, carrying out thermal modification treatment on the quartz glass ingot by adopting a groove sinking furnace; S4, carrying out annealing treatment on the quartz glass ingot subjected to thermal modification by adopting an annealing furnace; and S5, carrying out hydrogen permeation treatment on the annealed quartz glass by adopting a hydrogen permeation furnace to obtain the quartz glass for photoetching. According to the preparation method, the density distribution is improved through a loose body deposition procedure, the problems existing in the aspects of uniformity and defect control in a normal-pressure sintering mode are solved by regulating and controlling the dehydration and impurity removal reaction rate, and uniform distribution of hydrogen molecules is achieved through sectional type hydrogen loading.

The invention discloses a mask box storage library and photoetching exposure equipment. The mask box storage library comprises a support frame, a rectangular groove, a mask box mechanism and a supporting and taking mechanism, according to the mask box mechanism of the mask box storage warehouse, the taking and placing opening of the mask box mechanism can be opened or closed through the bin door assembly, the problem that the occupied area is large due to the fact that the mask box mechanism is driven to be opened through an external device is solved, and the mask can be horizontally moved out of the mask box mechanism; after the mask is moved out, a bracket of the supporting and taking mechanism is close to the position below the mask and is driven to move upwards, the mask is supported to be separated from the supporting disc, then the mask is grabbed for use, and the problem that dust is easily brought in after an external grabbing mechanism is inserted into the mask box mechanism and grabbed is solved; and the side edge of the mask can be exposed by supporting the mask from the bottom, and the bottom of the side edge is not shielded, so that the middle position of the grabbing part is in better contact with the mask for grabbing, and the stability of grabbing the mask is improved.

The invention discloses an FPC film strain gauge and a manufacturing method thereof. The strain gauge comprises a flexible insulating substrate, a specific-component copper-nickel alloy layer (with 55% of Cu and 45% of Ni and the thickness of 1-5m) sputtered on the flexible insulating substrate, a plurality of independent sensitive grids etched on the alloy layer and arranged along different directions, and a signal lead on the other surface of the substrate, wherein the flexible insulating substrate is connected with the specific-component copper-nickel alloy layer through a via hole with a metalized hole wall. The manufacturing method comprises the steps of drilling, three-step plasma treatment, magnetron sputtering of alloy, electroplating of copper to reinforce the hole wall, double-sided photoetching and etching and the like. Through glue-free sputtering combination and a specific alloy formula, the problems of glue layer aging and temperature drift of a traditional strain gauge are solved, and the product has the advantages of being ultrathin, flexible, high in stability, high in precision and suitable for batch production.

The invention relates to a system for semiconductor technology comprising at least one fluid channel (105) for a temperature control medium for temperature control of at least one component, e.g. a mirror (25, M4) of a projection exposure system (1) for photolithography. The system comprises at least two pressure fluctuation measuring devices (210) and a pressure surge sensor (220), arranged in series along the fluid channel (105) and connected to a control unit (230). The control unit (230) is configured to detect pressure fluctuations in the temperature control medium propagating from the pressure fluctuation measuring devices (210) towards the pressure surge sensor (220) from the signals of the pressure fluctuation measuring devices (210) and to control the pressure surge sensor (220) appropriately to generate destructive interference and reduce pressure fluctuations in the temperature control medium.