15results about How to "Increased process window" patented technology

The application provides a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a semiconductor substrate, including a conductive channel region; forming a gate structure on the surface of the semiconductor substrate; forming a mask on the surface opposite to the gate structure, and the mask corresponds to the conductive channel region; the mask is provided with a first recessed part; removing the mask and the gate structure on both sides of the conductive channel region, and the gate structure corresponding to the conductive channel region is formed with a second recessed part; doping the substrate on both sides of the gate structure to form a doped region; forming a metal silicide layer on the surface of the gate structure and the doped region; forming a dielectric layer on the surface of the metal silicide layer, and the dielectric layer is provided with a first contact hole corresponding to the doped region and a second contact hole corresponding to the second recessed part; forming a first metal contact body in the first contact hole and a second metal contact body in the second contact hole. The application can increase the process window of etching the contact hole and reduce the abnormal rate of etching through the metal silicide layer.

The application provides an advanced packaging semiconductor device manufacturing method and an advanced packaging semiconductor device. The method comprises the following steps: providing a substrate formed with a plurality of first through silicon via structures, the top of the first through silicon via structure being away from the first surface of the substrate by a first depth; performing a thinning treatment on the second surface of the substrate until the second surface is away from the top of the longest first through silicon via structure by a first distance; forming a hard mask layer on the second surface of the substrate, and patterning to define openings corresponding to the first through silicon via structures; etching the substrate to form second openings by using the hard mask layer as a mask; depositing a second dielectric layer on the sidewall and bottom of the second openings; etching the second dielectric layer and the first dielectric layer at the bottom of the second openings to expose the metal layer; and filling the second openings with a metal material to form electrically connected second through silicon via structures. The application perfectly compensates for the problem of uneven TSV depth, widens the process window, and significantly improves the product yield and reliability.

The application provides a semiconductor structure and a forming method thereof, wherein a first through silicon via structure is formed through two processes of front side processing and back side processing, and a second through silicon via structure is formed through one process of front side processing; since the first through silicon via structure is formed through two processes, the critical dimension and the depth adjustment range of the first through silicon via structure are large, so that the first through silicon via structure can be designed to have a small critical dimension, and the critical dimension is reduced; in addition, the first through silicon via structure and the second through silicon via structure are connected with back-end metal interconnections located on different planes, so that the process window of the back-end metal wiring is increased.

The application discloses a high-strength and high-toughness Al-Ca-In series aluminum alloy low-oxygen spherical powder for additive manufacturing and a preparation method thereof, relates to the technical field of additive manufacturing powder, and comprises the following components in percentage by mass: 1.5-3.0% of magnesium, 0.15-0.60% of manganese, 1.0-2.0% of calcium, 0.06-0.25% of indium, 0.08-0.18% of zirconium and 0-0.05% of titanium, and the balance of aluminum and impurities, wherein the total oxygen is not more than 0.10%; the powder surface has a nitrogen-containing diffusion barrier layer with a thickness of 2-8 nanometers and an ultrathin oxide layer with a thickness of 0.5-2.0 nanometers in sequence, and the surface enrichment and interface capture indexes are limited; and the powder is prepared by high-temperature dissolution of manganese and zirconium, low-temperature segmented calcium addition, nitrogen-containing gas atomization and low-temperature micro-oxidation. The powder inhibits the surface migration and oxidation loss of calcium and indium, improves the component stability in recycling and forming, reduces defects and performance dispersion, and is suitable for the high-strength and high-toughness manufacturing consistency of thin-wall lattice load-bearing parts.

The application belongs to the technical field of cord steel preparation, and particularly relates to a high-strength and high-plasticity cord steel and a preparation method thereof, the preparation method comprising the following steps: S1, obtaining a cord steel casting blank, heating, rolling and cooling the cord steel casting blank to obtain a cord steel wire rod, and the structure of the cord steel wire rod is a pearlite structure with an average interlamellar spacing of 95-100 nm; S2, cold drawing the cord steel wire rod to obtain a cord steel wire material, and the total surface reduction of the cold drawing is greater than or equal to 85%; and S3, heat treating the cord steel wire material to obtain the high-strength and high-plasticity cord steel, and the holding temperature of the heat treatment is 280-300 DEG C. According to the application, a pearlite matrix is obtained through alloy composition and cooling design, and severe plastic deformation is performed to construct an initial state with high defect density, low-temperature heat treatment is adopted to drive short-range diffusion of interface carbon atoms to construct a composition gradient and drive diffusion of micro-alloy elements to regulate nanometer precipitates, and the interface plasticization and precipitation reinforcement are synergized.

A semiconductor terminal structure and its formation method are disclosed. The method includes: forming a hard mask layer on the surface of an epitaxial layer, comprising a first hard mask layer and a second hard mask layer located on the surface of the first hard mask layer, wherein the hard mask layer has a plurality of first openings, the width of the plurality of first openings gradually decreasing along a first direction, or gradually decreasing and then remaining constant; forming a plurality of first doped regions in the epitaxial layer using the hard mask layer as a mask and employing a first doping process; etching the first hard mask layer using an isotropic etching process using the second hard mask layer as a mask, thereby exposing one end of the top surface of the main junction region; and forming a second doped region in the epitaxial layer using a second doping process using the first hard mask layer as a mask, wherein the second doped region and the first doped region have a partially overlapping region, and the doping concentration of the overlapping region is less than or equal to the doping concentration of the main junction region. This structure can effectively reduce the terminal's occupied area, improve the process window, and improve the terminal's breakdown voltage.

The application relates to the technical field of integrated circuits, and discloses a mask layout optimization method, equipment, a storage medium and a program product, the method comprising the following steps: acquiring an initial layout to be optimized, the initial layout comprising a plurality of target patterns, the target pattern being a hole pattern with symmetry; synchronously rotating the plurality of target patterns on the initial layout to a plurality of different angles to obtain a plurality of intermediate layouts; adding sub-resolution auxiliary patterns to the initial layout and each intermediate layout respectively to obtain a plurality of sub-resolution auxiliary pattern sets; merging the plurality of sub-resolution auxiliary pattern sets; adding the merged sub-resolution auxiliary pattern set to the initial layout; and optimizing the merged sub-resolution auxiliary pattern set according to mask manufacturability rules. The application realizes sufficient addition of auxiliary patterns and improves a process window by rotating the target pattern to a plurality of angles, adding auxiliary patterns adapted to the angles, and merging the auxiliary patterns.

A semiconductor structure and a method for forming the same, wherein the semiconductor structure comprises: a substrate; a first well region and a drift region in the substrate; a gate structure on the substrate, a source region and a drain region on both sides of the gate structure, and a first dielectric layer on the gate structure, a projection of the gate structure on a surface of the drift region being a first pattern; a first conductive layer on the first dielectric layer, and a second dielectric layer on the first dielectric layer, a projection of the first conductive layer on the surface of the drift region being a second pattern, the first pattern being within the second pattern; a trench structure in the first dielectric layer and the second dielectric layer, the trench structure being above the drift region, the trench structure comprising a first trench and a second trench below the first trench, the first trench exposing a part of a top surface of the first conductive layer, and a bottom of the second trench being higher than the surface of the drift region; and a floating plug in the trench structure. The semiconductor structure and the method for forming the same improve device performance.

This invention provides a method for regulating the eutectic reaction mechanism of DBC (Dielectric-Ceramic Composite) substrates, belonging to the field of DBC substrate fabrication technology in power electronic packaging. Addressing the problems of interfacial brittleness, intermetallic compound aggregation, low bonding strength, and poor thermal cycling reliability caused by thermal expansion coefficient mismatch and stress concentration in traditional DBC processes, this invention proposes a three-pronged approach to actively regulate the stress field: interface microstructure guidance, gradient thermal field control, and dynamic mechanical constraint. Through ten steps including substrate pretreatment, microstructure patterning, gradient thermal field construction, dynamic pressure application, in-situ stress monitoring, and segmented cooling, precise spatiotemporal control of the interface stress field is achieved, promoting the formation of a dense and uniform interface layer. Experiments show that the DBC substrate prepared by this invention exhibits over 30% improved interfacial bonding strength and over 2 times improved thermal cycling life. It also demonstrates strong process compatibility and excellent controllability, making it suitable for demanding applications such as high-end power electronic devices.

This invention discloses a method for element doping of a thin-film solar cell and its absorber layer, relating to the field of thin-film solar cell technology. By immersing the activated absorber layer in a salt solution of a predetermined dopant element and simultaneously applying an exogenous inducing variable, the predetermined element is doped. During the doping process, the diffusion of dopant ions into the grain boundaries and lattice interior of the absorber layer is promoted, ensuring that the element is not affected by the surface morphology, hydrophilicity / hydrophobicity, internal or edge structure of the absorber layer. This solves the problems of difficult-to-control element doping uniformity, poor process stability, and low effective doping activation rate in existing technologies. It achieves the goal of diffusive doping of p-type elements in the absorber layer with high doping uniformity, high doping activation rate, controllable doping process, and compatibility with existing processes.

This invention discloses a miniature light-emitting diode (LED) chip, including, for example, an epitaxial structure. The epitaxial structure includes a first-doped semiconductor layer, a second-doped semiconductor layer, and an active layer located between the first and second-doped semiconductor layers. A patterned structure is provided on the light-emitting side of the first-doped semiconductor layer away from the active layer. The long side *a* of the miniature LED chip, the thickness *b* of the miniature LED chip, and the peak-valley height difference *c* of the patterned structure satisfy the conditions: 0.01 ≤ *b / a* ≤ 6 and 0.01 ≤ *c / b* ≤ 0.3. This invention, by designing the structural dimensions and / or shape of the miniature LED chip, for example, designing the peak-valley height difference of the patterned structure to satisfy the condition 0.01 ≤ *c / b* ≤ 0.3, can reduce the power of laser stripping, increase the process window, and improve light extraction efficiency. This invention also provides a display device using the aforementioned miniature LED chip.

This invention discloses a method for producing cold-extruded carburized gear steel with anti-grain coarsening properties, belonging to the field of alloy steel manufacturing and heat treatment technology. The gear steel has the following chemical composition by mass percentage: C 0.17%~0.23%, Si 0.15%~0.40%, Mn 0.8%~1.50%, P ≤0.025%, S ≤0.035%, Cr 0.80%~1.50%, Nb 0.030%~0.080%, Al 0.020%~0.060%, Ti ≤0.005%, B ≤0.0010%, N 0.010%~0.025%, with the balance being Fe and unavoidable impurities. The production process includes converter smelting, LF refining, RH vacuum treatment, continuous casting, billet heating, and rolling. This method optimizes alloy composition and process control, making it less likely for the austenite grains of steel to coarsen after high-temperature carburizing. After carburizing, the steel can be directly quenched without normalizing treatment, resulting in a fine-grained martensite structure. This effectively simplifies the gear production process, reduces energy consumption, and minimizes deformation and oxidation decarburization, while ensuring that the gears have high surface hardness, high wear resistance, and excellent core toughness.

The utility model provides a kind of temperature-controllable vacuum drying equipment, including including process cavity and vacuum system;The process cavity is provided with the support platform for placing the product to be dried in;The vacuum system is communicated with the process cavity, for extracting vacuum to the process cavity;Heating element is provided in the cavity wall of the process cavity, and the heating element is used to adjust the inner wall temperature of the process cavity.The present application is heated in real time to the inner wall of process cavity, to promote the solvent volatilization adsorbed on the inner wall, to avoid the influence on subsequent drying crystallization process.

This invention discloses a method for optimizing the main pattern of a CT layer applied to OPC correction. The invention introduces a risk function and an activity domain to constrain the movement range of the main pattern of the CT layer. By moving the position of the main pattern, more sub-resolution assist features (SRAFs) can be added during CT layer OPC correction, increasing the overall process window (PW) of the main pattern of the CT layer and improving the yield of manufactured semiconductor devices.