96results about How to "Increased process window" patented technology

The invention provides a low-cost preparation method of high-performance titanium-doped iron phosphate, and relates to the technical field of batteries. The low-cost preparation method comprises the following steps: S1, respectively preparing a phosphoric acid solution, a hydrogen peroxide solution, a phosphorus salt solution and a ferrite solution; s2, adding titanium sulfate into the ferrite solution to obtain an iron-titanium mixed solution; s3, directly adding ammonia water and a hydrogen peroxide solution into the phosphorus salt solution to obtain a phosphorus-oxygen mixed solution; s4, the iron-titanium mixed solution is heated, the phosphorus-oxygen mixed solution is put into the iron-titanium mixed solution, and slurry A is obtained; s5, obtaining a filter cake A; s6, adding pure water and a phosphoric acid solution, and heating to obtain slurry B; s7, obtaining anhydrous iron phosphate; the synthesized iron phosphate is compact and compact in morphology, internal pore channels of primary particles are still rich, the compaction density of the lithium iron phosphate material obtained through grinding and sintering reaches 2.613 g / cc, the 0.1 C discharge capacity can still reach 156.35 mAh / g, and the 1C discharge capacity reaches 131.47 mAh / g.

The invention provides an optical proximity correction method which is applied to the technical field of semiconductors. In the invention, aiming at some special areas in the target layout, such as the condition that only one auxiliary graph can be added between adjacent main graphs, a new auxiliary graph adding mode and the auxiliary graph after shape adjustment are provided; specifically, an initial auxiliary graph with the width equal to that of a main graph is added between adjacent main graphs of a target main graph group, the graph density of the main graphs in a target layout is changed, sparse graphs also have the characteristics of dense graphs, then the added initial auxiliary graph is adjusted, and the graph density of the main graphs in the target layout is changed. And changing the initial auxiliary pattern into a target auxiliary pattern with a plurality of spacing gaps inside, so as to reduce the actual width of the target auxiliary pattern by using the spacing gaps, reduce the light intensity value of diffracted light at the target auxiliary pattern during exposure and development, improve the normalized logarithmic slope of the main pattern, reduce the edge placement error (EPE) and enlarge the process window.

The invention relates to the technical field of solar cell preparation, and discloses a laser patterned polycrystalline silicon passivation cell, a preparation method and a photovoltaic module. The preparation method comprises the following steps: preparing a passivation contact structure and an oxidation film on the surface of a silicon substrate; laser patterning processing is carried out on the surface of the silicon substrate, the passivation contact structure and the non-metallization area of the oxidation film, so that the processed non-metallization area is not subjected to alkali etching resistance, and doping atoms are pushed into the silicon substrate through laser diffusion to form a doping area; performing alkali wash etching to form an alkali wash etching region etched into the silicon substrate, and leaving a doped region on the silicon substrate exposed in the alkali wash etching region; respectively depositing a passivation antireflection film and an antireflection film on the front surface and the back surface of the silicon substrate; and preparing the metal electrode. According to the preparation method, parasitic absorption loss can be avoided, the transverse transmission capability of internal carriers can be enhanced, the light utilization rate and the photoelectric conversion efficiency of the cell are further improved, the process window is larger, and the process steps are simple.

The invention provides a welding method and a compressor. The welding method is used for welding two parts of the compressor and comprises the following steps: providing a first part and a second part; the first component and the second component are coaxially arranged, and a welding area is formed at a seam between the first component and the second component; the welding area is welded in a laser welding mode, so that the first component and the second component are fixedly connected; wherein during laser welding, an included angle is formed between the center line of the light emitting direction of a laser beam of a laser head and the direction of a connecting line between the laser head and the axis of the first component and the axis of the second component, and the included angle is larger than zero. During welding, the included angle larger than zero is formed between the light emitting direction of the laser beam and the axis direction, pointing to the two to-be-welded workpieces, of the laser head, the width of a welding seam formed during welding is larger than the depth of the welding seam, a welding process window is enlarged, the welding process difficulty is reduced, and the welding quality of the compressor is improved.

The invention discloses a solar cell, a preparation method thereof and a photovoltaic module, and relates to the technical field of solar cells. The solar cell includes: a substrate; the tunneling layer is located on the surface of the substrate; the isolation structure is located on the surface, away from the substrate, of the tunneling layer, and the isolation structure comprises silicon oxide layers and doped buffer layers which are alternately stacked in the first direction perpendicular to the substrate; the first doping layer is located on the surface of the isolation structure away from the substrate; wherein the doping concentration of the first doped layer is greater than that of the doped buffer layer. The doping ions diffused to the tunneling layer are integrally reduced, the influence of internal expansion is reduced, the open-circuit voltage and the filling factor of the solar cell are improved, the product competitiveness of the solar cell is improved, the process window of the annealing process is expanded, and the influence of the annealing process matching on the performance of the solar cell is reduced.

The invention provides a shallow trench isolation structure, a preparation method thereof and a semiconductor device, an insulating blocking layer is formed by adopting a non-ISSG process after an oxide repair layer is formed by adopting an ISSG process and before a silicon oxide film is formed, and the blocking layer made of an insulating material can block-OH and-H ions mixed in the oxide repair layer, so that the isolation performance of the semiconductor device is improved. Therefore, nonuniformity of consumption of active sites-C-H when ozone and TEOS thermal chemical reaction are carried out by more-OH ions in the shallow trench and less-OH ions on the hard mask layer is avoided, consistency of deposition rate and uniformity of a silicon oxide film inside and outside the shallow trench is improved, early sealing of the top of the shallow trench is avoided, and the yield of the shallow trench is improved. Holes and / or gaps in the shallow trench isolation structure are reduced, the hole filling capability and quality of the HARP process are improved, and the reliability and stability of a semiconductor device formed subsequently are improved. In addition, the deposition uniformity of the HARP process on ISSG OX can be improved, and the load of the subsequent CMP process is reduced; in addition, a process window of HARP can be increased, and the back etching amount of the hard mask layer is reduced.

The invention discloses a multi-laser-area additive-detection-subtractive composite manufacturing method which comprises the following steps: establishing a three-dimensional model of a part to be formed, and adding a necessary support structure model for the three-dimensional model; laser printing process parameters are set, a model formed by combining the three-dimensional model and the supporting structure body model is sliced layer by layer, and a slicing program is obtained; the slicing program is imported into multi-laser powder bed fusion forming software, and a printing program is generated; a printing program is imported into the multi-laser-area material increasing-detecting-material decreasing composite device; the multi-laser-area additive-detection-subtractive composite device prints an entity of a part to be formed on a forming substrate of the multi-laser-area additive-detection-subtractive composite device according to the slicing program; and after printing is finished, the forming substrate is taken out of the multi-laser-area additive-detection-subtractive composite device, the entity of the to-be-formed part is cut off from the forming substrate, and the entity of the to-be-formed part is obtained. The forming efficiency is improved, and the machining quality and precision are guaranteed.

The invention discloses a power regulation method of a radio frequency power supply and semiconductor process equipment. The method comprises the following steps: when a process formula is executed in a multi-station chamber, obtaining the actual load power of each station with a wafer; standard load power corresponding to the technological formula and the stations with the wafers is obtained; and adjusting the power of the radio frequency power supply according to the actual load power and the standard load power of each station with the wafer. The dynamic power of the radio frequency power supply is adjusted according to different actual states and different operation process formulas of semiconductor process equipment, so that the power output stability of each station is ensured, the film thickness consistency is improved, various process formulas can be covered, the process window is enlarged, and the production efficiency is improved. Adjusting modules do not need to be arranged at all stations respectively, the structure is simple, control calculation logic is simple, and a machine table end is easy to achieve.

The invention provides a preparation method for growing an alpha-phase tantalum film at room temperature and high quality without a buffer layer, which comprises the following steps of: loading a substrate into a sample introduction chamber, and vacuumizing to be below 6e-8Torr; the substrate is conveyed to a coating chamber, the substrate and the tantalum target material are oppositely arranged, the included angle between the normal of the substrate and the normal of the plane where the tantalum target material is located is 0 degree, the substrate sample and the tantalum target material are adjusted to be kept at a preset distance, and the coating chamber is vacuumized to be below 5e-10Torr; inert gas is pre-introduced into the vacuum environment, so that the chamber reaches and is maintained at the preset air pressure; specific power is output for sputter coating, and power output and inert gas input are stopped after sputter is completed for a preset sputter time; and the substrate plated with the alpha-phase tantalum film is conveyed back to the sample injection chamber from the film plating chamber, and nitrogen or argon is used for breaking vacuum and taking out the substrate. The invention provides a technological process for preparing a high-quality-factor resonator quantum device from the prepared tantalum film. According to the invention, the yield is improved, the device performance is improved, and the method has wide application fields including but not limited to the fields of quantum calculation and the like.

The invention discloses a color filter and a forming method thereof, and the method comprises the steps: providing a light-transmitting substrate which comprises a display region and a frame region surrounding the display region; a black matrix layer is formed on the light-transmitting substrate, the black matrix layer is internally provided with a plurality of opening units which are located in the display area and arranged periodically and open grooves located in the frame area, the open grooves surround the opening units, and the opening units and the open grooves are exposed out of the light-transmitting substrate; color layers are formed in the opening units; forming a protective layer on the black matrix layer and the color layer; a shielding layer is formed on the surface of the protective layer on the frame area, the shielding layer has a first projection on the surface of the light-transmitting substrate, the slot has a second projection on the surface of the light-transmitting substrate, the second projection and the first projection are at least partially overlapped, and the shielding layer is beneficial to improving the light-transmitting problem and enlarging a process window.

The invention discloses a crystal growth synthesis furnace which comprises a composite furnace body, a heating and temperature control system, an optical observation window assembly and a growth monitoring and control system. A furnace chamber of the composite furnace body is of a multi-layer gradient composite lining structure composed of a pressure-bearing water-cooled jacket, a carbon fiber reinforced silicon carbide composite material layer, a foam silicon carbide ceramic heat insulation layer and high-purity graphite paper. The heating and temperature control system adopts a distributed design and comprises a main heater, an upper auxiliary heating ring, a lower auxiliary heating disc and a lateral compensation heater. The optical observation window assembly is fixed to the center of the upper furnace cover and matched with the high-speed imaging unit to achieve in-situ monitoring of the growth process. According to the crystal growth synthesis furnace provided by the invention, accurate regulation and control of a three-dimensional temperature field and real-time visual monitoring of a growth interface in a silicon carbide crystal growth process are realized, and the crystal quality, the growth success rate and the process repeatability are remarkably improved.

This invention provides a method for forming interdigitated electrodes, wherein the interdigitated electrodes are metal stacks. The method includes: providing a piezoelectric substrate; forming a metal material stack and a composite mask material layer on the piezoelectric substrate; the metal material stack includes a first metal material layer and a second metal material layer; the composite mask material layer includes a first mask material layer and a second mask material layer made of different materials; patterning the composite mask material layer to obtain a composite mask layer; the composite mask layer includes a first mask layer corresponding to the first mask material layer and a second mask layer corresponding to the second mask material layer; etching the first metal material layer using the composite mask layer as a mask to obtain a first metal layer, simultaneously consuming the first mask layer; and etching the second metal material layer using the second mask layer as a mask to obtain a second metal layer. This invention solves the problem that the interdigitated electrode material needs to be coated with a thick photoresist, and the unexpected reduction in photoresist thickness during the etching process makes it difficult to control the morphology of the interdigitated electrodes.

The invention provides a method for expanding a grinding window of a metal gate layer, which comprises the following steps of: providing a substrate, forming pseudo gate structures with different lengths on a long channel device region and a short channel device region on the substrate, and forming an etching stop layer covering the pseudo gate structures; a first interlayer dielectric layer with a preset thickness is formed on the etching stop layer, and then a second interlayer dielectric layer covering the pseudo gate structures is formed on the first interlayer dielectric layer, so that only the first interlayer dielectric layer is filled in a narrower gap between part of the pseudo gate structures; a first interlayer dielectric layer and a second interlayer dielectric layer are filled in wider gaps among part of the pseudo gate structures, and the grinding rate of the second interlayer dielectric layer is slower than that of the first interlayer dielectric layer; grinding the first interlayer dielectric layer and the second interlayer dielectric layer to the pseudo gate polycrystalline silicon layer; and removing the pseudo gate polycrystalline silicon layer to form a groove, forming a metal gate layer for filling the groove, and grinding the metal gate layer to a required height. According to the invention, the dished defect degree after the second interlayer dielectric layer is ground is reduced, and the problem that a subsequent process window is too small is avoided.

The invention discloses a manufacturing method of a super junction device. The manufacturing method comprises the following steps: growing a first epitaxial layer; and injecting a first P-type impurity into a surface region of the first epitaxial layer in a first selected region, wherein the first selected region at least comprises a partial region, close to the transition region, of the terminal region. And forming a trench gate. And forming a well region and performing annealing. And forming a second groove. And growing a P-type doped second epitaxial layer in the second groove, removing the second epitaxial layer outside the second groove, and flattening the surface of the second epitaxial layer in the second groove. And completing a subsequent front process and setting a thermal process according to the requirement of controlling PN impurity mutual diffusion of the super junction structure, wherein the subsequent front process comprises the step of forming a protective epoxy film covering the inner side region of a cut-off region of the transition region and the terminal region. And completing a back process. According to the invention, mutual diffusion of PN impurities of the super junction structure can be effectively controlled, the reliability of a product can be improved, PN balance of a terminal region can be improved, BVdss of a device and consistency of the BVdss are improved, and the EAS capability is improved.

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a discrete core layer on the substrate, wherein the core layer to be removed serves as a pseudo core layer; forming a sacrificial sidewall on the sidewall of the core layer; forming a mask sidewall on the sidewall of the sacrificial sidewall; removing the sacrificial sidewall; after removing the sacrificial sidewall, removing the pseudo core layer; and patterning the substrate using the mask sidewall and the remaining core layer as masks. The embodiments of the present invention are conducive to reducing the process difficulty of removing the pseudo core layer and increasing the process window for removing the pseudo core layer.

The application discloses a 3D memory device and a manufacturing method thereof. The 3D memory device comprises a chip storage area, the chip storage area comprises: a stack structure on a semiconductor substrate; a plurality of gate line gaps penetrating through the stack structure, part of the gate line gaps divide the chip storage area into a plurality of block storage areas, the plurality of gate line gaps are arranged along a first direction, and a plurality of channel columns penetrating through the stack structure are arranged between adjacent gate line gaps, the chip storage area comprises a central area and at least one edge area arranged along the first direction, and the minimum distance between at least one gate line gap and its adjacent channel column in the at least one edge area is greater than the minimum distance between at least one gate line gap and its adjacent channel column in the central area. By increasing the minimum distance between the gate line gap and its adjacent channel column in the edge area, the influence of stress and load effect on the 3D NAND device is avoided, and the low reliability and low yield of the 3D NAND device are avoided.

The invention provides a method for forming a semi-floating gate structure, which comprises the following steps of: 1) providing a semiconductor structure which comprises a substrate, a gate stack structure, a first oxide layer and a dielectric layer; 2) forming a third polycrystalline silicon layer on the surface of the semiconductor structure; 3) etching the third polycrystalline silicon layer until the dielectric layer is exposed to form a first opening; 4) forming an SOC layer on the surface of the semiconductor structure formed in the step 3); 5) forming a SiARC layer on the surface of the SOC layer; 6) etching the SiARC layer and the SOC layer below the SiARC layer until the dielectric layer is exposed to form a second opening; (7) the SiARC layer is removed; 8) etching the dielectric layer, the first oxide layer, the second polycrystalline silicon layer, the inter-gate dielectric layer and the first polycrystalline silicon layer along the second opening; (9) the SOC layer is removed; and step 10) etching to remove the exposed dielectric layer. According to the method, the problems that residues easily exist and the substrate is easily damaged when the SiARC layer is removed in the prior art are solved.

The invention relates to a semiconductor device and a manufacturing method thereof, and the method comprises the steps: forming a first gate structure, a second gate structure and an interlayer dielectric layer on a substrate, and enabling the interlayer dielectric layer to cover the substrate at two sides of the first gate structure and the substrate at two sides of the second gate structure, the width of the section of the first gate structure in the direction perpendicular to the surface of the substrate is larger than that of the section of the second gate structure in the direction perpendicular to the surface of the substrate, and the surface of the first gate structure is higher than that of the second gate structure; forming a surface filling layer covering the first gate structure and the second gate structure on the interlayer dielectric layer; thinning the surface filling layer to expose the first gate structure; and etching the first gate structure to enable the surface of the first gate structure to be flush with the surface of the second gate structure. According to the invention, the height difference between the first gate structure and the second gate structure is reduced or eliminated, and the process window of the subsequent process is increased.

The application provides a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a semiconductor substrate, including a conductive channel region; forming a gate structure on the surface of the semiconductor substrate; forming a mask on the surface opposite to the gate structure, and the mask corresponds to the conductive channel region; the mask is provided with a first recessed part; removing the mask and the gate structure on both sides of the conductive channel region, and the gate structure corresponding to the conductive channel region is formed with a second recessed part; doping the substrate on both sides of the gate structure to form a doped region; forming a metal silicide layer on the surface of the gate structure and the doped region; forming a dielectric layer on the surface of the metal silicide layer, and the dielectric layer is provided with a first contact hole corresponding to the doped region and a second contact hole corresponding to the second recessed part; forming a first metal contact body in the first contact hole and a second metal contact body in the second contact hole. The application can increase the process window of etching the contact hole and reduce the abnormal rate of etching through the metal silicide layer.

The embodiment of the invention relates to a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises a substrate which comprises an array region and a peripheral region; the bit line structure is located in the array region, and the bit line structure comprises a bit line contact structure in contact with the substrate; the gate structure is located in the peripheral region, the gate structure comprises a first conductive layer located on the substrate, and the top surface of the bit line contact structure is not higher than the top surface of the first conductive layer in the direction parallel to the surface of the substrate. The semiconductor structure provided by the embodiment of the invention at least can improve the performance of the semiconductor structure.

The utility model discloses plastic-film-free packaging paper which comprises a kraft paper base layer, the bottom surface of the kraft paper base layer is provided with a low-temperature heat-sealing layer, the low-temperature heat-sealing layer is formed by coating a water-based heat-sealing adhesive on the kraft paper base layer, and the surface of the kraft paper base layer is sequentially coated with a pre-coating layer, a printing layer and a protective gloss oil layer. By means of the mode, the packaging paper without the plastic film is endowed with heat sealing performance through the layers, heat sealing can be rapidly conducted under the low-temperature condition, the packaging paper is easy to recycle after being used, the mechanical property of the paper is improved, and the packaging paper can be made into a coiled material to be used for online packaging.

The invention provides thin film deposition equipment and a manufacturing method of an NMOS (N-channel metal oxide semiconductor) device, and belongs to the field of semiconductors. The thin film deposition apparatus includes a housing having a sputtering chamber. The target material is arranged opposite to the substrate, the target material comprises a first sputtering material and a second sputtering material, and the atomic weight of the first sputtering material is different from that of the second sputtering material. And the radio frequency power supply is used for generating plasma to bombard the target material and sputter the target material to the surface of the substrate to form a thin film. And the external member is arranged in the sputtering chamber, the external member is provided with a sputtering layer with a certain thickness, and the sputtering layer is made of the same material as the target material. Through the sputtering layer with a certain thickness deposited on the suite, the threshold voltage of the device is relatively stable, the performance of the product is improved, the process window of the product is also enlarged, the utilization rate of a machine table is improved, and the loss of a target material is reduced.

The invention provides a preparation method of positive electrode slurry, the positive electrode slurry, a positive electrode plate, a secondary battery and an electric device. The preparation method of the positive electrode slurry comprises first stirring, second stirring and third stirring, in the first stirring, the positive electrode active material and the binder are mixed and stirred to prepare a dry mixture; in the second stirring process, the solvent and the dry mixture are kneaded, and primary slurry is prepared; in the third stirring process, a conductive agent, a solvent, a binder and the primary slurry are mixed and stirred, and the positive electrode slurry is prepared. The preparation method has universality, is suitable for slurry containing binders with different molecular weights, and is particularly suitable for high-molecular-weight binders, so that the gel resistance and sedimentation resistance of the slurry are effectively improved, the uniformity of the slurry is optimized, and the preparation cost is reduced and the production efficiency is improved.

The application provides a method for removing titanium nitride and a wafer processing system. The wafer processing system comprises at least a wafer chuck, a chemical spraying unit and a heating unit. The wafer with a titanium nitride layer to be removed on the front surface is placed on the wafer chuck, and the front surface of the wafer to be processed faces the chemical spraying unit. The chemical spraying unit sprays the chemical liquid for removing the titanium nitride layer to the front surface of the wafer to be processed through the first nozzle according to the preset spraying timing. Meanwhile, the heating unit heats the back surface of the wafer to be processed during the removal of the titanium nitride layer. The temperature difference between the wafer and the chemical liquid can be quickly shortened, the etching rate is stabilized, the operation time is shortened, and the process window is expanded.

The application provides an advanced packaging semiconductor device manufacturing method and an advanced packaging semiconductor device. The method comprises the following steps: providing a substrate formed with a plurality of first through silicon via structures, the top of the first through silicon via structure being away from the first surface of the substrate by a first depth; performing a thinning treatment on the second surface of the substrate until the second surface is away from the top of the longest first through silicon via structure by a first distance; forming a hard mask layer on the second surface of the substrate, and patterning to define openings corresponding to the first through silicon via structures; etching the substrate to form second openings by using the hard mask layer as a mask; depositing a second dielectric layer on the sidewall and bottom of the second openings; etching the second dielectric layer and the first dielectric layer at the bottom of the second openings to expose the metal layer; and filling the second openings with a metal material to form electrically connected second through silicon via structures. The application perfectly compensates for the problem of uneven TSV depth, widens the process window, and significantly improves the product yield and reliability.

The invention belongs to the technical field of semiconductors, and provides a field effect transistor with high on-state through-current capability and lower off-state electric leakage capability based on structural innovation of a Schottky source-drain MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). An n-channel normally-closed MOSFET is taken as an example, on the basis that a Schottky junction formed by a source electrode and an n-type semiconductor region is originally utilized to deplete electron carriers in the n-type semiconductor region from one side, a Schottky gate or a p-type gate is introduced to deplete the electron carriers in the n-type semiconductor region from the other side, so that the influence effect of double-side depletion is realized, and the reliability of the device is improved. Thus, in the aspect of electrical performance, the on-state through-current capability is maintained, off-state electric leakage is further reduced, and meanwhile adjustment of the starting voltage is facilitated; in the aspect of the manufacturing process, the key width dimension requirement can be relaxed, and the photoetching amp is reduced; the requirements of the etching technology and equipment are met, the process window is expanded, and the batch production yield is improved.

The application provides a semiconductor structure and a forming method thereof, wherein a first through silicon via structure is formed through two processes of front side processing and back side processing, and a second through silicon via structure is formed through one process of front side processing; since the first through silicon via structure is formed through two processes, the critical dimension and the depth adjustment range of the first through silicon via structure are large, so that the first through silicon via structure can be designed to have a small critical dimension, and the critical dimension is reduced; in addition, the first through silicon via structure and the second through silicon via structure are connected with back-end metal interconnections located on different planes, so that the process window of the back-end metal wiring is increased.

The invention belongs to the technical field of semiconductors, and provides a field effect transistor with high on-state through-current capability and lower off-state electric leakage capability based on structural innovation of a traditional pn junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Taking an n-channel normally-off pn junction MOSFET as an example, an electron conductive channel between a drain and a source only passes through an n-type semiconductor region of a semiconductor layer and does not pass through a p-type semiconductor region of the semiconductor layer, which is beneficial to improvement of on-state through-current capability; meanwhile, a Schottky gate or a p-type gate is introduced into the gate electrode, and the structural design is beneficial for reducing off-state electric leakage.

The utility model provides a thickness measuring pad and a wafer cutting channel, and the thickness measuring pad is located in the cutting channel of a wafer and is used for monitoring the film thickness of a thin film technology in a semiconductor manufacturing process. According to one embodiment, the plane shape of the thickness measuring pad on the plane where the wafer is located is a rectangle, and the angle between the rectangular edge of the thickness measuring pad and the edge of the cutting channel is larger than 0 degree and smaller than 90 degrees. According to the thickness measuring pad in the wafer cutting channel provided by the utility model, the cutting efficiency is improved by shortening the length of a cut line of the thickness measuring pad during scribing, and meanwhile, process windows for laser cutting and follow-up flywheel knife cutting can be increased.

A memory structure and a forming method thereof are provided, the memory structure comprises a substrate, the substrate comprises a plurality of first regions and second regions located between adjacent first regions, the first regions and the second regions are internally provided with a plurality of mutually discrete active regions, the first regions and the second regions are arranged along a second direction, and the active regions stretch across the first regions and the second regions, the first direction and the second direction are parallel to the surface of the substrate, and the first direction is perpendicular to the second direction; the connecting parts are located in the second region and located between the adjacent active regions; the storage gate structures are located in the first region, adjacent to the second region and located on the two sides of the second region respectively; and the source line structure is positioned on the active region of the second region and the connecting part. The source line structure is located between the active regions of the second region and is connected by the connecting part, so that the contact area of the source line structure is increased, the contact resistance is reduced, and the performance of the device structure is further improved.