32results about How to "Increased process window" patented technology

The invention discloses a crystal growth synthesis furnace which comprises a composite furnace body, a heating and temperature control system, an optical observation window assembly and a growth monitoring and control system. A furnace chamber of the composite furnace body is of a multi-layer gradient composite lining structure composed of a pressure-bearing water-cooled jacket, a carbon fiber reinforced silicon carbide composite material layer, a foam silicon carbide ceramic heat insulation layer and high-purity graphite paper. The heating and temperature control system adopts a distributed design and comprises a main heater, an upper auxiliary heating ring, a lower auxiliary heating disc and a lateral compensation heater. The optical observation window assembly is fixed to the center of the upper furnace cover and matched with the high-speed imaging unit to achieve in-situ monitoring of the growth process. According to the crystal growth synthesis furnace provided by the invention, accurate regulation and control of a three-dimensional temperature field and real-time visual monitoring of a growth interface in a silicon carbide crystal growth process are realized, and the crystal quality, the growth success rate and the process repeatability are remarkably improved.

This invention provides a method for forming interdigitated electrodes, wherein the interdigitated electrodes are metal stacks. The method includes: providing a piezoelectric substrate; forming a metal material stack and a composite mask material layer on the piezoelectric substrate; the metal material stack includes a first metal material layer and a second metal material layer; the composite mask material layer includes a first mask material layer and a second mask material layer made of different materials; patterning the composite mask material layer to obtain a composite mask layer; the composite mask layer includes a first mask layer corresponding to the first mask material layer and a second mask layer corresponding to the second mask material layer; etching the first metal material layer using the composite mask layer as a mask to obtain a first metal layer, simultaneously consuming the first mask layer; and etching the second metal material layer using the second mask layer as a mask to obtain a second metal layer. This invention solves the problem that the interdigitated electrode material needs to be coated with a thick photoresist, and the unexpected reduction in photoresist thickness during the etching process makes it difficult to control the morphology of the interdigitated electrodes.

The application discloses a 3D memory device and a manufacturing method thereof. The 3D memory device comprises a chip storage area, the chip storage area comprises: a stack structure on a semiconductor substrate; a plurality of gate line gaps penetrating through the stack structure, part of the gate line gaps divide the chip storage area into a plurality of block storage areas, the plurality of gate line gaps are arranged along a first direction, and a plurality of channel columns penetrating through the stack structure are arranged between adjacent gate line gaps, the chip storage area comprises a central area and at least one edge area arranged along the first direction, and the minimum distance between at least one gate line gap and its adjacent channel column in the at least one edge area is greater than the minimum distance between at least one gate line gap and its adjacent channel column in the central area. By increasing the minimum distance between the gate line gap and its adjacent channel column in the edge area, the influence of stress and load effect on the 3D NAND device is avoided, and the low reliability and low yield of the 3D NAND device are avoided.

The application provides a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a semiconductor substrate, including a conductive channel region; forming a gate structure on the surface of the semiconductor substrate; forming a mask on the surface opposite to the gate structure, and the mask corresponds to the conductive channel region; the mask is provided with a first recessed part; removing the mask and the gate structure on both sides of the conductive channel region, and the gate structure corresponding to the conductive channel region is formed with a second recessed part; doping the substrate on both sides of the gate structure to form a doped region; forming a metal silicide layer on the surface of the gate structure and the doped region; forming a dielectric layer on the surface of the metal silicide layer, and the dielectric layer is provided with a first contact hole corresponding to the doped region and a second contact hole corresponding to the second recessed part; forming a first metal contact body in the first contact hole and a second metal contact body in the second contact hole. The application can increase the process window of etching the contact hole and reduce the abnormal rate of etching through the metal silicide layer.

The application provides an advanced packaging semiconductor device manufacturing method and an advanced packaging semiconductor device. The method comprises the following steps: providing a substrate formed with a plurality of first through silicon via structures, the top of the first through silicon via structure being away from the first surface of the substrate by a first depth; performing a thinning treatment on the second surface of the substrate until the second surface is away from the top of the longest first through silicon via structure by a first distance; forming a hard mask layer on the second surface of the substrate, and patterning to define openings corresponding to the first through silicon via structures; etching the substrate to form second openings by using the hard mask layer as a mask; depositing a second dielectric layer on the sidewall and bottom of the second openings; etching the second dielectric layer and the first dielectric layer at the bottom of the second openings to expose the metal layer; and filling the second openings with a metal material to form electrically connected second through silicon via structures. The application perfectly compensates for the problem of uneven TSV depth, widens the process window, and significantly improves the product yield and reliability.

The application provides a semiconductor structure and a forming method thereof, wherein a first through silicon via structure is formed through two processes of front side processing and back side processing, and a second through silicon via structure is formed through one process of front side processing; since the first through silicon via structure is formed through two processes, the critical dimension and the depth adjustment range of the first through silicon via structure are large, so that the first through silicon via structure can be designed to have a small critical dimension, and the critical dimension is reduced; in addition, the first through silicon via structure and the second through silicon via structure are connected with back-end metal interconnections located on different planes, so that the process window of the back-end metal wiring is increased.

The application discloses a high-strength and high-toughness Al-Ca-In series aluminum alloy low-oxygen spherical powder for additive manufacturing and a preparation method thereof, relates to the technical field of additive manufacturing powder, and comprises the following components in percentage by mass: 1.5-3.0% of magnesium, 0.15-0.60% of manganese, 1.0-2.0% of calcium, 0.06-0.25% of indium, 0.08-0.18% of zirconium and 0-0.05% of titanium, and the balance of aluminum and impurities, wherein the total oxygen is not more than 0.10%; the powder surface has a nitrogen-containing diffusion barrier layer with a thickness of 2-8 nanometers and an ultrathin oxide layer with a thickness of 0.5-2.0 nanometers in sequence, and the surface enrichment and interface capture indexes are limited; and the powder is prepared by high-temperature dissolution of manganese and zirconium, low-temperature segmented calcium addition, nitrogen-containing gas atomization and low-temperature micro-oxidation. The powder inhibits the surface migration and oxidation loss of calcium and indium, improves the component stability in recycling and forming, reduces defects and performance dispersion, and is suitable for the high-strength and high-toughness manufacturing consistency of thin-wall lattice load-bearing parts.

The utility model relates to the technical field of vacuum coating equipment, in particular to a multifunctional adjustable target distance rotating stand for magnetron sputtering equipment, which comprises a target distance rotating stand and a target distance adjusting mechanism arranged on the target distance rotating stand, and the target distance adjusting mechanism comprises a transmission gear set and a plurality of target distance telescopic pieces. The transmission gear set comprises a control gear and a power gear which are meshed with each other, each target distance telescopic piece is in transmission connection with the control gear and used for clamping a part to be coated, the power gear is driven by a motor, and when the power gear drives the control gear to rotate, the target distance telescopic pieces are close to or away from the target distance rotating frame. According to the utility model, the target distance can be accurately adjusted in the coating process, so that the coating uniformity, the process flexibility and the film layer quality are improved.

The invention relates to the technical field of cosmetics and preparations thereof, and discloses a heat-resistant liquid crystal emulsion system based on acetylated sodium hyaluronate as well as a preparation method and application thereof, the heat-resistant liquid crystal emulsion system comprises the following components in parts by weight: 1-6 parts of a liquid crystal emulsifier, 0.01-0.2 part of acetylated sodium hyaluronate, 5-60 parts of grease, 0.1-1 part of a thickening agent, 0.1-1 part of a preservative and the balance of water, totaling 100 parts. The preparation method comprises the following steps: respectively preheating the oil phase and the water phase according to the ratio, emulsifying under high-speed homogenization, and stirring and cooling at a controlled temperature. The core of the invention is that acetylated sodium hyaluronate is introduced into a liquid crystal system as a structural stabilizer, and the thermal stability of a liquid crystal structure is remarkably improved through the anchoring effect of the acetylated sodium hyaluronate and a liquid crystal layer; after the emulsion is stored at 40 DEG C for a long time, the liquid crystal texture is kept complete, and the emulsion has excellent long-acting moisturizing performance and can be used as an ideal carrier of high-end cosmetics and external medicine preparations.

A method for forming a semiconductor structure includes: providing a substrate; forming a first material layer on the substrate; performing ion implantation on the first material layer to form ion doped regions in the first material layer, a size of the ion doped regions in a first direction is a first size, the first direction is parallel to a surface of the substrate, a size of the ion doped regions in a direction perpendicular to the first direction is a second size, the first size is greater than or equal to the second size; forming a plurality of first mask structures on the first material layer, each first mask structure is located on at least part of a surface of each ion doped region; etching the first material layer to form a plurality of second core structures by taking the first mask structures as masks, each second core structure includes an ion doped region and a sacrifice structure adjacent to the ion doped region; forming a second side wall structure on a sidewall of each second core structure; and removing the sacrifice structure. The method for forming the semiconductor structure improves flexibility of a structure pattern, and improves a process window and compatibility.

The application belongs to the technical field of cord steel preparation, and particularly relates to a high-strength and high-plasticity cord steel and a preparation method thereof, the preparation method comprising the following steps: S1, obtaining a cord steel casting blank, heating, rolling and cooling the cord steel casting blank to obtain a cord steel wire rod, and the structure of the cord steel wire rod is a pearlite structure with an average interlamellar spacing of 95-100 nm; S2, cold drawing the cord steel wire rod to obtain a cord steel wire material, and the total surface reduction of the cold drawing is greater than or equal to 85%; and S3, heat treating the cord steel wire material to obtain the high-strength and high-plasticity cord steel, and the holding temperature of the heat treatment is 280-300 DEG C. According to the application, a pearlite matrix is obtained through alloy composition and cooling design, and severe plastic deformation is performed to construct an initial state with high defect density, low-temperature heat treatment is adopted to drive short-range diffusion of interface carbon atoms to construct a composition gradient and drive diffusion of micro-alloy elements to regulate nanometer precipitates, and the interface plasticization and precipitation reinforcement are synergized.

This application relates to the field of metal powder preparation technology, and in particular to a method for preparing silver powder for ultrafine line printing, comprising the following steps: preparing a silver ammonia solution and adding a dispersant, stirring to dissolve, adding a reducing agent solution, and aging to obtain nano-silver sol; forming a mixture of an initiator and deionized water, preparing aqueous solutions of acrylic acid and acrylamide separately, and adding them to the mixture for reaction, cooling and filtering to obtain an acrylic acid-acrylamide copolymer; weighing silver nitrate and deionized water, stirring to obtain solution A; weighing a reducing agent and deionized water, adjusting the pH to 1-2, and then adding the nano-silver sol and acrylic acid-acrylamide copolymer to obtain solution B; rapidly adding solution A to solution B, adding a surface modifier after the reaction is complete, aging, centrifuging, washing, and drying. The silver powder prepared by this application has the advantages of small average particle size, good overall uniformity, and small surface area, making it suitable for the field of ultrafine line printing.

A semiconductor terminal structure and its formation method are disclosed. The method includes: forming a hard mask layer on the surface of an epitaxial layer, comprising a first hard mask layer and a second hard mask layer located on the surface of the first hard mask layer, wherein the hard mask layer has a plurality of first openings, the width of the plurality of first openings gradually decreasing along a first direction, or gradually decreasing and then remaining constant; forming a plurality of first doped regions in the epitaxial layer using the hard mask layer as a mask and employing a first doping process; etching the first hard mask layer using an isotropic etching process using the second hard mask layer as a mask, thereby exposing one end of the top surface of the main junction region; and forming a second doped region in the epitaxial layer using a second doping process using the first hard mask layer as a mask, wherein the second doped region and the first doped region have a partially overlapping region, and the doping concentration of the overlapping region is less than or equal to the doping concentration of the main junction region. This structure can effectively reduce the terminal's occupied area, improve the process window, and improve the terminal's breakdown voltage.

The application relates to the technical field of integrated circuits, and discloses a mask layout optimization method, equipment, a storage medium and a program product, the method comprising the following steps: acquiring an initial layout to be optimized, the initial layout comprising a plurality of target patterns, the target pattern being a hole pattern with symmetry; synchronously rotating the plurality of target patterns on the initial layout to a plurality of different angles to obtain a plurality of intermediate layouts; adding sub-resolution auxiliary patterns to the initial layout and each intermediate layout respectively to obtain a plurality of sub-resolution auxiliary pattern sets; merging the plurality of sub-resolution auxiliary pattern sets; adding the merged sub-resolution auxiliary pattern set to the initial layout; and optimizing the merged sub-resolution auxiliary pattern set according to mask manufacturability rules. The application realizes sufficient addition of auxiliary patterns and improves a process window by rotating the target pattern to a plurality of angles, adding auxiliary patterns adapted to the angles, and merging the auxiliary patterns.

A semiconductor structure and a method for forming the same, wherein the semiconductor structure comprises: a substrate; a first well region and a drift region in the substrate; a gate structure on the substrate, a source region and a drain region on both sides of the gate structure, and a first dielectric layer on the gate structure, a projection of the gate structure on a surface of the drift region being a first pattern; a first conductive layer on the first dielectric layer, and a second dielectric layer on the first dielectric layer, a projection of the first conductive layer on the surface of the drift region being a second pattern, the first pattern being within the second pattern; a trench structure in the first dielectric layer and the second dielectric layer, the trench structure being above the drift region, the trench structure comprising a first trench and a second trench below the first trench, the first trench exposing a part of a top surface of the first conductive layer, and a bottom of the second trench being higher than the surface of the drift region; and a floating plug in the trench structure. The semiconductor structure and the method for forming the same improve device performance.

This invention provides a method for regulating the eutectic reaction mechanism of DBC (Dielectric-Ceramic Composite) substrates, belonging to the field of DBC substrate fabrication technology in power electronic packaging. Addressing the problems of interfacial brittleness, intermetallic compound aggregation, low bonding strength, and poor thermal cycling reliability caused by thermal expansion coefficient mismatch and stress concentration in traditional DBC processes, this invention proposes a three-pronged approach to actively regulate the stress field: interface microstructure guidance, gradient thermal field control, and dynamic mechanical constraint. Through ten steps including substrate pretreatment, microstructure patterning, gradient thermal field construction, dynamic pressure application, in-situ stress monitoring, and segmented cooling, precise spatiotemporal control of the interface stress field is achieved, promoting the formation of a dense and uniform interface layer. Experiments show that the DBC substrate prepared by this invention exhibits over 30% improved interfacial bonding strength and over 2 times improved thermal cycling life. It also demonstrates strong process compatibility and excellent controllability, making it suitable for demanding applications such as high-end power electronic devices.

This invention discloses a silicon carbide superjunction terminal with an L-type buffer and stepped pillars, and its fabrication method. The superjunction terminal includes a drain, an N-type substrate, and an N-type buffer layer stacked sequentially from bottom to top. The N-type buffer layer is divided into a cellular active region, a transition region, and a terminal region from the inside out. The cellular active region includes active region P-type pillars and active region N-type pillars; the transition region and terminal region include transition region P-type pillars and transition region N-type pillars. The depth of multiple transition region P-type pillars decreases stepwise. An N-lightly doped charge adjustment layer is filled between the lower surface of each transition region P-type pillar and the N-type buffer layer, as well as between adjacent transition region P-type pillars and transition region N-type pillars. A P+ type doped connection layer covers the upper surface of the transition region. A trench-type P-type field-limiting ring is formed on the upper surface of the terminal region. This invention achieves a synergistic balance between suppressing deep right-angle electric field distortion, solving dynamic hole accumulation, improving chip area utilization, and avoiding surface field plate risks.

The invention discloses a high-weather-resistance wide-temperature-range bottom filling adhesive for semiconductor packaging and a preparation method thereof, and relates to the technical field of filling adhesives for semiconductor packaging, and the preparation method comprises the following steps: synthesizing glycidyl sulfonate by taking bio-based glycidyl and sulfonyl chloride as raw materials, and synthesizing halogen-free DGEBA resin by taking bisphenol and glycidyl sulfonate as raw materials; the preparation method comprises the following steps: synthesizing phosphorylated modified resin by taking halogen-free DGEBA resin and phosphoryl chloride as raw materials; the preparation method comprises the following steps: uniformly stirring and melting halogen-free DGEBA resin and phosphorylated modified resin, adding a cross-linking agent, and uniformly stirring to obtain a resin matrix; the preparation method comprises the following steps: sequentially adding the siloxane latent accelerator and the composite filler into the resin matrix, stirring in vacuum, defoaming, adding the initiator, uniformly stirring, injecting into a mold, heating, curing, and cooling to room temperature to obtain the filling adhesive for semiconductor packaging, the composite filler is prepared from KH550 modified FeNi alloy particles.

This invention discloses a method for element doping of a thin-film solar cell and its absorber layer, relating to the field of thin-film solar cell technology. By immersing the activated absorber layer in a salt solution of a predetermined dopant element and simultaneously applying an exogenous inducing variable, the predetermined element is doped. During the doping process, the diffusion of dopant ions into the grain boundaries and lattice interior of the absorber layer is promoted, ensuring that the element is not affected by the surface morphology, hydrophilicity / hydrophobicity, internal or edge structure of the absorber layer. This solves the problems of difficult-to-control element doping uniformity, poor process stability, and low effective doping activation rate in existing technologies. It achieves the goal of diffusive doping of p-type elements in the absorber layer with high doping uniformity, high doping activation rate, controllable doping process, and compatibility with existing processes.

This invention discloses a miniature light-emitting diode (LED) chip, including, for example, an epitaxial structure. The epitaxial structure includes a first-doped semiconductor layer, a second-doped semiconductor layer, and an active layer located between the first and second-doped semiconductor layers. A patterned structure is provided on the light-emitting side of the first-doped semiconductor layer away from the active layer. The long side *a* of the miniature LED chip, the thickness *b* of the miniature LED chip, and the peak-valley height difference *c* of the patterned structure satisfy the conditions: 0.01 ≤ *b / a* ≤ 6 and 0.01 ≤ *c / b* ≤ 0.3. This invention, by designing the structural dimensions and / or shape of the miniature LED chip, for example, designing the peak-valley height difference of the patterned structure to satisfy the condition 0.01 ≤ *c / b* ≤ 0.3, can reduce the power of laser stripping, increase the process window, and improve light extraction efficiency. This invention also provides a display device using the aforementioned miniature LED chip.

The invention provides a dynamic random access memory and a preparation method thereof, and the dynamic random access memory comprises a substrate which is provided with an array region and a peripheral region; the active regions are arranged in the array region in an array manner; the word line structure is arranged in the substrate and penetrates through the active region; the bit line structure is arranged in the array region and comprises a bit line electrode structure arranged on the active region; the bit line side wall comprises a first side wall arranged between the second side wall and the bit line electrode structure, and a bit line protection layer arranged on the side surface of the bit line side wall; the isolation structures and the node contact plugs are arranged between the bit line structures at intervals, and the node contact plugs are connected with the active regions; a landing pad partially disposed on the node contact plug and partially disposed on the bit line structure; the storage node is arranged on the landing pad; the peripheral area comprises a peripheral covering layer covering the circuit structure; wherein the upper surface of the second side wall located below the landing pad is lower than the upper surfaces of the first side wall and the bit line protection layer, and the bit line protection layer is arranged between the upper surface of the second side wall and the landing pad.

This invention discloses a method for producing cold-extruded carburized gear steel with anti-grain coarsening properties, belonging to the field of alloy steel manufacturing and heat treatment technology. The gear steel has the following chemical composition by mass percentage: C 0.17%~0.23%, Si 0.15%~0.40%, Mn 0.8%~1.50%, P ≤0.025%, S ≤0.035%, Cr 0.80%~1.50%, Nb 0.030%~0.080%, Al 0.020%~0.060%, Ti ≤0.005%, B ≤0.0010%, N 0.010%~0.025%, with the balance being Fe and unavoidable impurities. The production process includes converter smelting, LF refining, RH vacuum treatment, continuous casting, billet heating, and rolling. This method optimizes alloy composition and process control, making it less likely for the austenite grains of steel to coarsen after high-temperature carburizing. After carburizing, the steel can be directly quenched without normalizing treatment, resulting in a fine-grained martensite structure. This effectively simplifies the gear production process, reduces energy consumption, and minimizes deformation and oxidation decarburization, while ensuring that the gears have high surface hardness, high wear resistance, and excellent core toughness.

The utility model provides a kind of temperature-controllable vacuum drying equipment, including including process cavity and vacuum system;The process cavity is provided with the support platform for placing the product to be dried in;The vacuum system is communicated with the process cavity, for extracting vacuum to the process cavity;Heating element is provided in the cavity wall of the process cavity, and the heating element is used to adjust the inner wall temperature of the process cavity.The present application is heated in real time to the inner wall of process cavity, to promote the solvent volatilization adsorbed on the inner wall, to avoid the influence on subsequent drying crystallization process.

The present disclosure provides a partition cooling system, a cooling control method, a crystal bar, a wafer and a medium, comprising a partition independent heat exchange component, a thermal state sensing unit and a control unit, wherein the partition independent heat exchange component is arranged as multiple independent heat exchange levels along the vertical direction of crystal pulling, and the heat exchange levels respectively apply local cooling intensity to multiple height spatial domains; the thermal state sensing unit is arranged along the growth path of the single crystal silicon ingot and is configured to obtain real-time thermodynamic state data corresponding to multiple height spatial domains on the growth path of the silicon ingot during single crystal growth. The control unit is communicatively coupled with the partition independent heat exchange component and the thermal state sensing unit, used to receive real-time thermodynamic state data and independently control the partition independent heat exchange component.

The invention discloses a triphenylamine gallium porphyrin complex and application of the triphenylamine gallium porphyrin complex as a hole transport layer material. The structure of the complex is shown in the following formula, wherein R represents methoxy, methylthio or hydrogen. The complex has an energy level better matched with a perovskite layer and better intrinsic hole transport characteristics, and under the condition that no chemical doping is needed, a formal (n-i-p) perovskite solar cell prepared from the complex obtains 16.25% of photoelectric conversion efficiency and is comparable with an early-stage doped Spiro-OMeTAD system. The lithium salt and the organic dopant which are easy to absorb moisture and migrate are completely abandoned, so that the problem of device degradation caused by the lithium salt and the organic dopant is radically eliminated, and the long-term stability of the device under hot, wet and running conditions is synchronously and greatly improved; the preparation process is greatly simplified, the process window is obviously widened, the production repeatability and the yield are improved, and by omitting expensive dopants and simplifying production steps and quality control links, the material and process cost is directly reduced, and the industrial application potential is improved.

The invention relates to a multispectral TDICCD preparation method for improving spectral response consistency, and belongs to the field of multispectral TDICCDs. The method comprises the following steps: sequentially forming a potential well and a gate oxide layer on a silicon epitaxial substrate; depositing a first layer of polycrystalline silicon on the surface of the gate oxide layer, performing large-dose ion implantation, and then performing nitrogen treatment annealing; forming an electrode pattern on the first layer of polycrystalline silicon, and then forming a first interlayer insulating layer through a silicon dioxide and silicon nitride deposition process; depositing to form a second layer of polycrystalline silicon, performing large-dose ion implantation, and then performing nitrogen treatment annealing; forming an electrode pattern on the second layer of polycrystalline silicon, and then forming a second interlayer insulating layer through a silicon dioxide and silicon nitride deposition process; a layer of BPSG is deposited on the surface of a currently formed device, then high-temperature backflow treatment is performed, and then low-temperature silicon dioxide deposition and CMP processes are performed to flatten the surface. The method is high in process stability and operability, and spectral response consistency can be improved.

The invention provides a photoetching method and a semiconductor structure. The photoetching method comprises the steps that a substrate is provided, the substrate is provided with a first type region and a second type region, and a target mask material layer is formed on the surface of the substrate; providing a photomask assembly, wherein the photomask assembly comprises a first photomask and a second photomask; performing first exposure etching on the target mask material layer according to the first photomask so as to remove the target mask material corresponding to the first type region; performing second exposure etching on the target mask material layer according to a second photomask so as to remove the target mask material corresponding to the second type region; wherein the orthographic projection of the process window of the first exposure etching and the orthographic projection of the process window of the second exposure etching on the substrate are at least partially overlapped. According to the photoetching method, it can be ensured that the mask material possibly remaining at the junction area can be removed, it is avoided that the follow-up planarization process is abnormal due to mask material residues, and meanwhile the local load effect in the planarization process is relieved.

The application provides a semiconductor device and a preparation method thereof. The preparation method comprises forming a self-aligned blocking layer; forming a silicon oxide protection layer; performing a patternless etching process, the remaining silicon oxide protection layer covering the self-aligned blocking layer on the sidewall of the first sidewall structure and the sidewall of the second sidewall structure; performing a pre-cleaning process, the silicon oxide protection layer being consumed during the pre-cleaning process; forming a metal silicide, the metal silicide covering the semiconductor substrate on both sides of the first polysilicon gate and the first gate structure, the process of forming the metal silicide comprising performing a SiCoNi process, the silicon oxide protection layer being consumed again during the SiCoNi process. By forming the silicon oxide protection layer before the pre-cleaning process, the consumption of the first sidewall structure and the self-aligned blocking layer in the pre-cleaning process and the SiCoNi process is reduced, thereby avoiding the situation that the leakage current is too high due to too small spacing, and avoiding the second area growing metal silicide, so as to improve the device performance.

The invention discloses a thermomechanical treatment method of a copper-chromium-zirconium alloy strip, which comprises the following steps: weighing casting raw materials according to a preset ratio range, and putting the casting raw materials into a smelting furnace for smelting and casting to obtain a cast ingot, the casting raw materials comprising a Cu raw material, a Cr raw material, a Zr raw material and impurities; carrying out heating treatment and hot rolling treatment on the cast ingot to obtain a hot-rolled blank, and carrying out primary solid solution treatment on the hot-rolled blank to obtain a primary solid solution blank; primary cold rolling treatment is carried out on the primary solid solution blank, intermediate heat treatment is carried out on a primary cold-rolled strip, secondary solid solution treatment is carried out on an intermediate strip, and a secondary solid solution blank is obtained; secondary cold rolling treatment is conducted on the secondary solid solution blank, and a secondary cold-rolled strip is obtained; and the secondary cold-rolled strip is subjected to aging treatment, and the copper-chromium-zirconium alloy strip is obtained. By designing the combination of multi-stage solid solution and specific intermediate heat treatment, a precipitated phase is induced to be precipitated in a finer and more dispersed form in the cold rolling process, and the strength and conductivity of the alloy are improved.