48results about How to "Increased process window" patented technology

The invention discloses a power regulation method of a radio frequency power supply and semiconductor process equipment. The method comprises the following steps: when a process formula is executed in a multi-station chamber, obtaining the actual load power of each station with a wafer; standard load power corresponding to the technological formula and the stations with the wafers is obtained; and adjusting the power of the radio frequency power supply according to the actual load power and the standard load power of each station with the wafer. The dynamic power of the radio frequency power supply is adjusted according to different actual states and different operation process formulas of semiconductor process equipment, so that the power output stability of each station is ensured, the film thickness consistency is improved, various process formulas can be covered, the process window is enlarged, and the production efficiency is improved. Adjusting modules do not need to be arranged at all stations respectively, the structure is simple, control calculation logic is simple, and a machine table end is easy to achieve.

The invention discloses a color filter and a forming method thereof, and the method comprises the steps: providing a light-transmitting substrate which comprises a display region and a frame region surrounding the display region; a black matrix layer is formed on the light-transmitting substrate, the black matrix layer is internally provided with a plurality of opening units which are located in the display area and arranged periodically and open grooves located in the frame area, the open grooves surround the opening units, and the opening units and the open grooves are exposed out of the light-transmitting substrate; color layers are formed in the opening units; forming a protective layer on the black matrix layer and the color layer; a shielding layer is formed on the surface of the protective layer on the frame area, the shielding layer has a first projection on the surface of the light-transmitting substrate, the slot has a second projection on the surface of the light-transmitting substrate, the second projection and the first projection are at least partially overlapped, and the shielding layer is beneficial to improving the light-transmitting problem and enlarging a process window.

The invention discloses a crystal growth synthesis furnace which comprises a composite furnace body, a heating and temperature control system, an optical observation window assembly and a growth monitoring and control system. A furnace chamber of the composite furnace body is of a multi-layer gradient composite lining structure composed of a pressure-bearing water-cooled jacket, a carbon fiber reinforced silicon carbide composite material layer, a foam silicon carbide ceramic heat insulation layer and high-purity graphite paper. The heating and temperature control system adopts a distributed design and comprises a main heater, an upper auxiliary heating ring, a lower auxiliary heating disc and a lateral compensation heater. The optical observation window assembly is fixed to the center of the upper furnace cover and matched with the high-speed imaging unit to achieve in-situ monitoring of the growth process. According to the crystal growth synthesis furnace provided by the invention, accurate regulation and control of a three-dimensional temperature field and real-time visual monitoring of a growth interface in a silicon carbide crystal growth process are realized, and the crystal quality, the growth success rate and the process repeatability are remarkably improved.

This invention provides a method for forming interdigitated electrodes, wherein the interdigitated electrodes are metal stacks. The method includes: providing a piezoelectric substrate; forming a metal material stack and a composite mask material layer on the piezoelectric substrate; the metal material stack includes a first metal material layer and a second metal material layer; the composite mask material layer includes a first mask material layer and a second mask material layer made of different materials; patterning the composite mask material layer to obtain a composite mask layer; the composite mask layer includes a first mask layer corresponding to the first mask material layer and a second mask layer corresponding to the second mask material layer; etching the first metal material layer using the composite mask layer as a mask to obtain a first metal layer, simultaneously consuming the first mask layer; and etching the second metal material layer using the second mask layer as a mask to obtain a second metal layer. This invention solves the problem that the interdigitated electrode material needs to be coated with a thick photoresist, and the unexpected reduction in photoresist thickness during the etching process makes it difficult to control the morphology of the interdigitated electrodes.

The invention discloses a manufacturing method of a super junction device. The manufacturing method comprises the following steps: growing a first epitaxial layer; and injecting a first P-type impurity into a surface region of the first epitaxial layer in a first selected region, wherein the first selected region at least comprises a partial region, close to the transition region, of the terminal region. And forming a trench gate. And forming a well region and performing annealing. And forming a second groove. And growing a P-type doped second epitaxial layer in the second groove, removing the second epitaxial layer outside the second groove, and flattening the surface of the second epitaxial layer in the second groove. And completing a subsequent front process and setting a thermal process according to the requirement of controlling PN impurity mutual diffusion of the super junction structure, wherein the subsequent front process comprises the step of forming a protective epoxy film covering the inner side region of a cut-off region of the transition region and the terminal region. And completing a back process. According to the invention, mutual diffusion of PN impurities of the super junction structure can be effectively controlled, the reliability of a product can be improved, PN balance of a terminal region can be improved, BVdss of a device and consistency of the BVdss are improved, and the EAS capability is improved.

The application discloses a 3D memory device and a manufacturing method thereof. The 3D memory device comprises a chip storage area, the chip storage area comprises: a stack structure on a semiconductor substrate; a plurality of gate line gaps penetrating through the stack structure, part of the gate line gaps divide the chip storage area into a plurality of block storage areas, the plurality of gate line gaps are arranged along a first direction, and a plurality of channel columns penetrating through the stack structure are arranged between adjacent gate line gaps, the chip storage area comprises a central area and at least one edge area arranged along the first direction, and the minimum distance between at least one gate line gap and its adjacent channel column in the at least one edge area is greater than the minimum distance between at least one gate line gap and its adjacent channel column in the central area. By increasing the minimum distance between the gate line gap and its adjacent channel column in the edge area, the influence of stress and load effect on the 3D NAND device is avoided, and the low reliability and low yield of the 3D NAND device are avoided.

The invention relates to a semiconductor device and a manufacturing method thereof, and the method comprises the steps: forming a first gate structure, a second gate structure and an interlayer dielectric layer on a substrate, and enabling the interlayer dielectric layer to cover the substrate at two sides of the first gate structure and the substrate at two sides of the second gate structure, the width of the section of the first gate structure in the direction perpendicular to the surface of the substrate is larger than that of the section of the second gate structure in the direction perpendicular to the surface of the substrate, and the surface of the first gate structure is higher than that of the second gate structure; forming a surface filling layer covering the first gate structure and the second gate structure on the interlayer dielectric layer; thinning the surface filling layer to expose the first gate structure; and etching the first gate structure to enable the surface of the first gate structure to be flush with the surface of the second gate structure. According to the invention, the height difference between the first gate structure and the second gate structure is reduced or eliminated, and the process window of the subsequent process is increased.

The application provides a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a semiconductor substrate, including a conductive channel region; forming a gate structure on the surface of the semiconductor substrate; forming a mask on the surface opposite to the gate structure, and the mask corresponds to the conductive channel region; the mask is provided with a first recessed part; removing the mask and the gate structure on both sides of the conductive channel region, and the gate structure corresponding to the conductive channel region is formed with a second recessed part; doping the substrate on both sides of the gate structure to form a doped region; forming a metal silicide layer on the surface of the gate structure and the doped region; forming a dielectric layer on the surface of the metal silicide layer, and the dielectric layer is provided with a first contact hole corresponding to the doped region and a second contact hole corresponding to the second recessed part; forming a first metal contact body in the first contact hole and a second metal contact body in the second contact hole. The application can increase the process window of etching the contact hole and reduce the abnormal rate of etching through the metal silicide layer.

The utility model discloses plastic-film-free packaging paper which comprises a kraft paper base layer, the bottom surface of the kraft paper base layer is provided with a low-temperature heat-sealing layer, the low-temperature heat-sealing layer is formed by coating a water-based heat-sealing adhesive on the kraft paper base layer, and the surface of the kraft paper base layer is sequentially coated with a pre-coating layer, a printing layer and a protective gloss oil layer. By means of the mode, the packaging paper without the plastic film is endowed with heat sealing performance through the layers, heat sealing can be rapidly conducted under the low-temperature condition, the packaging paper is easy to recycle after being used, the mechanical property of the paper is improved, and the packaging paper can be made into a coiled material to be used for online packaging.

The application provides a method for removing titanium nitride and a wafer processing system. The wafer processing system comprises at least a wafer chuck, a chemical spraying unit and a heating unit. The wafer with a titanium nitride layer to be removed on the front surface is placed on the wafer chuck, and the front surface of the wafer to be processed faces the chemical spraying unit. The chemical spraying unit sprays the chemical liquid for removing the titanium nitride layer to the front surface of the wafer to be processed through the first nozzle according to the preset spraying timing. Meanwhile, the heating unit heats the back surface of the wafer to be processed during the removal of the titanium nitride layer. The temperature difference between the wafer and the chemical liquid can be quickly shortened, the etching rate is stabilized, the operation time is shortened, and the process window is expanded.

The application provides an advanced packaging semiconductor device manufacturing method and an advanced packaging semiconductor device. The method comprises the following steps: providing a substrate formed with a plurality of first through silicon via structures, the top of the first through silicon via structure being away from the first surface of the substrate by a first depth; performing a thinning treatment on the second surface of the substrate until the second surface is away from the top of the longest first through silicon via structure by a first distance; forming a hard mask layer on the second surface of the substrate, and patterning to define openings corresponding to the first through silicon via structures; etching the substrate to form second openings by using the hard mask layer as a mask; depositing a second dielectric layer on the sidewall and bottom of the second openings; etching the second dielectric layer and the first dielectric layer at the bottom of the second openings to expose the metal layer; and filling the second openings with a metal material to form electrically connected second through silicon via structures. The application perfectly compensates for the problem of uneven TSV depth, widens the process window, and significantly improves the product yield and reliability.

The application provides a semiconductor structure and a forming method thereof, wherein a first through silicon via structure is formed through two processes of front side processing and back side processing, and a second through silicon via structure is formed through one process of front side processing; since the first through silicon via structure is formed through two processes, the critical dimension and the depth adjustment range of the first through silicon via structure are large, so that the first through silicon via structure can be designed to have a small critical dimension, and the critical dimension is reduced; in addition, the first through silicon via structure and the second through silicon via structure are connected with back-end metal interconnections located on different planes, so that the process window of the back-end metal wiring is increased.

The utility model provides a thickness measuring pad and a wafer cutting channel, and the thickness measuring pad is located in the cutting channel of a wafer and is used for monitoring the film thickness of a thin film technology in a semiconductor manufacturing process. According to one embodiment, the plane shape of the thickness measuring pad on the plane where the wafer is located is a rectangle, and the angle between the rectangular edge of the thickness measuring pad and the edge of the cutting channel is larger than 0 degree and smaller than 90 degrees. According to the thickness measuring pad in the wafer cutting channel provided by the utility model, the cutting efficiency is improved by shortening the length of a cut line of the thickness measuring pad during scribing, and meanwhile, process windows for laser cutting and follow-up flywheel knife cutting can be increased.

The application discloses a high-strength and high-toughness Al-Ca-In series aluminum alloy low-oxygen spherical powder for additive manufacturing and a preparation method thereof, relates to the technical field of additive manufacturing powder, and comprises the following components in percentage by mass: 1.5-3.0% of magnesium, 0.15-0.60% of manganese, 1.0-2.0% of calcium, 0.06-0.25% of indium, 0.08-0.18% of zirconium and 0-0.05% of titanium, and the balance of aluminum and impurities, wherein the total oxygen is not more than 0.10%; the powder surface has a nitrogen-containing diffusion barrier layer with a thickness of 2-8 nanometers and an ultrathin oxide layer with a thickness of 0.5-2.0 nanometers in sequence, and the surface enrichment and interface capture indexes are limited; and the powder is prepared by high-temperature dissolution of manganese and zirconium, low-temperature segmented calcium addition, nitrogen-containing gas atomization and low-temperature micro-oxidation. The powder inhibits the surface migration and oxidation loss of calcium and indium, improves the component stability in recycling and forming, reduces defects and performance dispersion, and is suitable for the high-strength and high-toughness manufacturing consistency of thin-wall lattice load-bearing parts.

The utility model relates to the technical field of vacuum coating equipment, in particular to a multifunctional adjustable target distance rotating stand for magnetron sputtering equipment, which comprises a target distance rotating stand and a target distance adjusting mechanism arranged on the target distance rotating stand, and the target distance adjusting mechanism comprises a transmission gear set and a plurality of target distance telescopic pieces. The transmission gear set comprises a control gear and a power gear which are meshed with each other, each target distance telescopic piece is in transmission connection with the control gear and used for clamping a part to be coated, the power gear is driven by a motor, and when the power gear drives the control gear to rotate, the target distance telescopic pieces are close to or away from the target distance rotating frame. According to the utility model, the target distance can be accurately adjusted in the coating process, so that the coating uniformity, the process flexibility and the film layer quality are improved.

The invention relates to the technical field of cosmetics and preparations thereof, and discloses a heat-resistant liquid crystal emulsion system based on acetylated sodium hyaluronate as well as a preparation method and application thereof, the heat-resistant liquid crystal emulsion system comprises the following components in parts by weight: 1-6 parts of a liquid crystal emulsifier, 0.01-0.2 part of acetylated sodium hyaluronate, 5-60 parts of grease, 0.1-1 part of a thickening agent, 0.1-1 part of a preservative and the balance of water, totaling 100 parts. The preparation method comprises the following steps: respectively preheating the oil phase and the water phase according to the ratio, emulsifying under high-speed homogenization, and stirring and cooling at a controlled temperature. The core of the invention is that acetylated sodium hyaluronate is introduced into a liquid crystal system as a structural stabilizer, and the thermal stability of a liquid crystal structure is remarkably improved through the anchoring effect of the acetylated sodium hyaluronate and a liquid crystal layer; after the emulsion is stored at 40 DEG C for a long time, the liquid crystal texture is kept complete, and the emulsion has excellent long-acting moisturizing performance and can be used as an ideal carrier of high-end cosmetics and external medicine preparations.

A method for forming a semiconductor structure includes: providing a substrate; forming a first material layer on the substrate; performing ion implantation on the first material layer to form ion doped regions in the first material layer, a size of the ion doped regions in a first direction is a first size, the first direction is parallel to a surface of the substrate, a size of the ion doped regions in a direction perpendicular to the first direction is a second size, the first size is greater than or equal to the second size; forming a plurality of first mask structures on the first material layer, each first mask structure is located on at least part of a surface of each ion doped region; etching the first material layer to form a plurality of second core structures by taking the first mask structures as masks, each second core structure includes an ion doped region and a sacrifice structure adjacent to the ion doped region; forming a second side wall structure on a sidewall of each second core structure; and removing the sacrifice structure. The method for forming the semiconductor structure improves flexibility of a structure pattern, and improves a process window and compatibility.

The application belongs to the technical field of cord steel preparation, and particularly relates to a high-strength and high-plasticity cord steel and a preparation method thereof, the preparation method comprising the following steps: S1, obtaining a cord steel casting blank, heating, rolling and cooling the cord steel casting blank to obtain a cord steel wire rod, and the structure of the cord steel wire rod is a pearlite structure with an average interlamellar spacing of 95-100 nm; S2, cold drawing the cord steel wire rod to obtain a cord steel wire material, and the total surface reduction of the cold drawing is greater than or equal to 85%; and S3, heat treating the cord steel wire material to obtain the high-strength and high-plasticity cord steel, and the holding temperature of the heat treatment is 280-300 DEG C. According to the application, a pearlite matrix is obtained through alloy composition and cooling design, and severe plastic deformation is performed to construct an initial state with high defect density, low-temperature heat treatment is adopted to drive short-range diffusion of interface carbon atoms to construct a composition gradient and drive diffusion of micro-alloy elements to regulate nanometer precipitates, and the interface plasticization and precipitation reinforcement are synergized.

This application relates to the field of metal powder preparation technology, and in particular to a method for preparing silver powder for ultrafine line printing, comprising the following steps: preparing a silver ammonia solution and adding a dispersant, stirring to dissolve, adding a reducing agent solution, and aging to obtain nano-silver sol; forming a mixture of an initiator and deionized water, preparing aqueous solutions of acrylic acid and acrylamide separately, and adding them to the mixture for reaction, cooling and filtering to obtain an acrylic acid-acrylamide copolymer; weighing silver nitrate and deionized water, stirring to obtain solution A; weighing a reducing agent and deionized water, adjusting the pH to 1-2, and then adding the nano-silver sol and acrylic acid-acrylamide copolymer to obtain solution B; rapidly adding solution A to solution B, adding a surface modifier after the reaction is complete, aging, centrifuging, washing, and drying. The silver powder prepared by this application has the advantages of small average particle size, good overall uniformity, and small surface area, making it suitable for the field of ultrafine line printing.

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, the substrate comprising a first conductive structure and a device structure, the substrate further comprising a first dielectric layer, a second dielectric layer, and an etch stop layer, wherein the second dielectric layer has a resistor layer; forming a first opening and a second opening in the second dielectric layer, wherein the bottom of the first opening exposes the etch stop layer on the first conductive structure, and the bottom of the second opening exposes the resistor layer; using a selective film forming process, forming an intermediate conductive film on the surface of the exposed resistor layer; after forming the intermediate conductive film, etching the exposed etch stop layer until the surface of the first conductive structure is exposed; after etching the exposed etch stop layer, forming a second conductive structure in the first opening; and after etching the exposed etch stop layer, forming a third conductive structure in the second opening. Thus, the semiconductor structure can have better performance and reliability while reducing the difficulty of the semiconductor structure manufacturing process.

The present disclosure provides a base bias adjustment apparatus and method, and a semiconductor process device. The base bias adjustment apparatus includes: a positive bias adjustment unit; a negative bias adjustment unit; and an anti-interference unit. A first terminal of the positive bias adjustment unit is grounded, and a second terminal of the positive bias adjustment unit is electrically connected to a base for adjusting a bias voltage of the base to have a positive bias voltage at the base. A first terminal of the negative bias adjustment unit is grounded, and a second terminal of the negative bias adjustment unit is electrically connected to the base through the anti-interference unit for adjusting the bias voltage of the base to have a negative bias voltage at the base. The anti-interference unit is electrically connected between the negative bias adjustment unit and the base for suppressing a current from a circuit between the positive bias adjustment unit and the base from flowing into a circuit between the negative bias adjustment unit and the base, thereby facilitating simultaneous operation of the positive bias adjustment unit and the negative bias adjustment unit in a process. The technical solution of the present disclosure meets different process needs, thereby expanding a process window.

A semiconductor terminal structure and its formation method are disclosed. The method includes: forming a hard mask layer on the surface of an epitaxial layer, comprising a first hard mask layer and a second hard mask layer located on the surface of the first hard mask layer, wherein the hard mask layer has a plurality of first openings, the width of the plurality of first openings gradually decreasing along a first direction, or gradually decreasing and then remaining constant; forming a plurality of first doped regions in the epitaxial layer using the hard mask layer as a mask and employing a first doping process; etching the first hard mask layer using an isotropic etching process using the second hard mask layer as a mask, thereby exposing one end of the top surface of the main junction region; and forming a second doped region in the epitaxial layer using a second doping process using the first hard mask layer as a mask, wherein the second doped region and the first doped region have a partially overlapping region, and the doping concentration of the overlapping region is less than or equal to the doping concentration of the main junction region. This structure can effectively reduce the terminal's occupied area, improve the process window, and improve the terminal's breakdown voltage.

The application relates to the technical field of integrated circuits, and discloses a mask layout optimization method, equipment, a storage medium and a program product, the method comprising the following steps: acquiring an initial layout to be optimized, the initial layout comprising a plurality of target patterns, the target pattern being a hole pattern with symmetry; synchronously rotating the plurality of target patterns on the initial layout to a plurality of different angles to obtain a plurality of intermediate layouts; adding sub-resolution auxiliary patterns to the initial layout and each intermediate layout respectively to obtain a plurality of sub-resolution auxiliary pattern sets; merging the plurality of sub-resolution auxiliary pattern sets; adding the merged sub-resolution auxiliary pattern set to the initial layout; and optimizing the merged sub-resolution auxiliary pattern set according to mask manufacturability rules. The application realizes sufficient addition of auxiliary patterns and improves a process window by rotating the target pattern to a plurality of angles, adding auxiliary patterns adapted to the angles, and merging the auxiliary patterns.

A semiconductor structure and a method for forming the same, wherein the semiconductor structure comprises: a substrate; a first well region and a drift region in the substrate; a gate structure on the substrate, a source region and a drain region on both sides of the gate structure, and a first dielectric layer on the gate structure, a projection of the gate structure on a surface of the drift region being a first pattern; a first conductive layer on the first dielectric layer, and a second dielectric layer on the first dielectric layer, a projection of the first conductive layer on the surface of the drift region being a second pattern, the first pattern being within the second pattern; a trench structure in the first dielectric layer and the second dielectric layer, the trench structure being above the drift region, the trench structure comprising a first trench and a second trench below the first trench, the first trench exposing a part of a top surface of the first conductive layer, and a bottom of the second trench being higher than the surface of the drift region; and a floating plug in the trench structure. The semiconductor structure and the method for forming the same improve device performance.

The present invention discloses a method for manufacturing a zero-layer interlayer film, comprising: step 1, forming a plurality of first gate structures formed by stacking a first gate dielectric layer and a polysilicon gate on the surface of a semiconductor substrate. The hard mask layer is also stacked on the top of the polysilicon gate. The area between each first gate structure is a spacing area. Step 2, growing a zero-layer interlayer film, the zero-layer interlayer film having an uneven top surface and a first depression at the top of the spacing area. Step 3, back-etching the zero-layer interlayer film on the top of the hard mask layer and forming a second depression, the bottom surface of the second depression being lower than the bottom surface of the first depression. Step 4, using the hard mask layer as a stop layer, and using a first chemical mechanical polishing process to flatten the zero-layer interlayer film. The present invention can eliminate butterfly defects on the surface of the zero-layer interlayer film, and can also simultaneously reduce the zero-layer interlayer film material residue on the surface of the hard mask layer and can simultaneously reduce the polishing time, thereby improving the process window.

The invention discloses a manufacturing method of a super junction device. The manufacturing method comprises the following steps: growing a first epitaxial layer; and injecting a first P-type impurity into a surface region of the first epitaxial layer in a first selected region, wherein the first selected region at least comprises a partial region, close to the transition region, of the terminal region. And forming a trench gate, removing the gate conductive material layer outside the gate trench of the trench gate, and enabling the top surface of the gate conductive material layer in the gate trench to be flat. And forming a well region and performing annealing. And forming a second groove. And growing a P-type doped second epitaxial layer in the second groove, completely removing the second epitaxial layer outside the second groove, and flattening the surface of the second epitaxial layer in the second groove. And a subsequent front process is completed, and a thermal process is set according to the requirement for controlling mutual diffusion of PN impurities of the super junction structure. And completing a back process. According to the invention, mutual diffusion of PN impurities of the super junction structure can be effectively controlled, PN balance of a terminal region can be improved, BVdss of the device is improved, consistency of the BVdss is improved, and EAS capability is improved.

This invention provides a method for regulating the eutectic reaction mechanism of DBC (Dielectric-Ceramic Composite) substrates, belonging to the field of DBC substrate fabrication technology in power electronic packaging. Addressing the problems of interfacial brittleness, intermetallic compound aggregation, low bonding strength, and poor thermal cycling reliability caused by thermal expansion coefficient mismatch and stress concentration in traditional DBC processes, this invention proposes a three-pronged approach to actively regulate the stress field: interface microstructure guidance, gradient thermal field control, and dynamic mechanical constraint. Through ten steps including substrate pretreatment, microstructure patterning, gradient thermal field construction, dynamic pressure application, in-situ stress monitoring, and segmented cooling, precise spatiotemporal control of the interface stress field is achieved, promoting the formation of a dense and uniform interface layer. Experiments show that the DBC substrate prepared by this invention exhibits over 30% improved interfacial bonding strength and over 2 times improved thermal cycling life. It also demonstrates strong process compatibility and excellent controllability, making it suitable for demanding applications such as high-end power electronic devices.

This invention discloses a silicon carbide superjunction terminal with an L-type buffer and stepped pillars, and its fabrication method. The superjunction terminal includes a drain, an N-type substrate, and an N-type buffer layer stacked sequentially from bottom to top. The N-type buffer layer is divided into a cellular active region, a transition region, and a terminal region from the inside out. The cellular active region includes active region P-type pillars and active region N-type pillars; the transition region and terminal region include transition region P-type pillars and transition region N-type pillars. The depth of multiple transition region P-type pillars decreases stepwise. An N-lightly doped charge adjustment layer is filled between the lower surface of each transition region P-type pillar and the N-type buffer layer, as well as between adjacent transition region P-type pillars and transition region N-type pillars. A P+ type doped connection layer covers the upper surface of the transition region. A trench-type P-type field-limiting ring is formed on the upper surface of the terminal region. This invention achieves a synergistic balance between suppressing deep right-angle electric field distortion, solving dynamic hole accumulation, improving chip area utilization, and avoiding surface field plate risks.