575 results about "Microcrystalline silicon" patented technology

It is an object to provide a semiconductor device which has a large size and operates at high speed. A top gate transistor which includes a semiconductor layer of single-crystal and a bottom gate transistor which includes a semiconductor layer of amorphous silicon (microcrystalline silicon) are formed over the same substrate. Then, gate electrodes of each transistor are formed with the same layer, and source and drain electrodes are also formed with the same layer. Thus, manufacturing steps are reduced. In other words, two types of transistors can be manufactured by adding only a few steps to the manufacturing process of a bottom gate transistor.

It is an object to provide a semiconductor device which has a large size and operates at high speed. A top gate transistor which includes a semiconductor layer of single-crystal and a bottom gate transistor which includes a semiconductor layer of amorphous silicon (microcrystalline silicon) are formed over the same substrate. Then, gate electrodes of each transistor are formed with the same layer, and source and drain electrodes are also formed with the same layer. Thus, manufacturing steps are reduced. In other words, two types of transistors can be manufactured by adding only a few steps to the manufacturing process of a bottom gate transistor.

Embodiments of the present invention generally relate to methods for forming a SiGe layer. In one embodiment, a seed SiGe layer is first formed using plasma enhanced chemical vapor deposition (PECVD), and a bulk SiGe layer is formed directly on the PECVD seed layer also using PECVD. The processing temperature for both seed and bulk SiGe layers is less than 450 degrees Celsius.

The electrode material for a lithium secondary battery according to the present invention includes particles of a solid state alloy having silicon as a main component, wherein the particles of the solid state alloy have a microcrystal or amorphous material including an element other than silicon, dispersed in microcrystalline silicon or amorphized silicon. The solid state alloy preferably contains a pure metal or a solid solution. The composition of the alloy preferably has an element composition in which the alloy is completely mixed in a melted liquid state, whereby the alloy has a single phase in a melted liquid state without presence of two or more phases. The element composition can be determined by the kind of elements constituting the alloy and an atomic ratio of the elements.

A MOS or CMOS sensor for high performance imaging in broad spectral ranges including portions of the infrared spectral band. These broad spectral ranges may also include portions or all of the visible spectrum, therefore the sensor has both daylight and night vision capabilities. The sensor includes a continuous multi-layer photodiode structure on a many pixel MOS or CMOS readout array where the photodiode structure is chosen to include responses in the near infrared spectral ranges. A preferred embodiment incorporates a microcrystalline copper indium diselenide / cadmium sulfide photodiode structure on a CMOS readout array. An alternate preferred embodiment incorporates a microcrystalline silicon germanium photodiode structure on a CMOS readout array. Each of these embodiments provides night vision with image performance that greatly surpasses the GEN III night vision technology in terms of enhanced sensitivity, pixel size and pixel count. Further advantages of the invention include low electrical bias voltages, low power consumption, compact packaging, and radiation hardness. In special preferred embodiments CMOS stitching technology is used to provide multi-million pixel focal plane array sensors. One embodiments of the invention made without stitching is a two-million pixel sensor. Other preferred embodiments available using stitching techniques include sensors with 250 million (or more) pixels fabricated on a single wafer. A particular application of these very high pixel count sensors is as a focal plane array for a rapid beam steering telescope in a low earth orbit satellite useful for tracking over a 1500-meter wide track with a resolution of 0.3 meter.

A photovoltaic element of the present invention is a photovoltaic element having a plurality of pin junctions each formed of a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer each comprising a non-single-crystal material comprising a Group IVA element as a principal component, the photovoltaic element having a first pin junction comprising microcrystal silicon carbide (hereinafter referred to as microcrystal SiC) as a principal component of the i-type semiconductor layer and a second pin junction comprising microcrystal silicon (hereinafter referred to as microcrystal Si) as a principal component of the i-type semiconductor layer, wherein the first pin junction is provided closer to the light incidence side than the second pin junction. Provided thereby are a low cost photovoltaic element which exhibits little photodeterioration and with a high photoelectric conversion efficiency, and production method of the photovoltaic element capable of forming i-type microcrystal silicon and microcrystal SiC at a practical deposition rate.

Methods for depositing a microcrystalline silicon film layer with improved deposition rate and film quality are provided in the present invention. Also, photovoltaic (PV) cell having a microcrystalline silicon film is provided. In one embodiment, the method produces a microcrystalline silicon film on a substrate at a deposition rate greater than about 20 nm per minute, wherein the microcrystalline silicon film has a crystallized volume between about 20 percent to about 80 percent.

An apparatus and methods for depositing amorphous and microcrystalline silicon films during the formation of solar cells are provided. In one embodiment, a method and apparatus is provided for generating and introducing hydrogen radicals directly into a processing region of a processing chamber for reaction with a silicon-containing precursor for film deposition on a substrate. In one embodiment, the hydrogen radicals are generated by a remote plasma source and directly introduced into the processing region via a line of sight path to minimize the loss of energy by the hydrogen radicals prior to reaching the processing region.

The invention features a miniature, second-order, microcrystalline silicon microphone diaphragm formed using silicon microfabrication techniques. The diaphragm is composed of two or more rigid diaphragm elements hinged to one another providing second- or higher-order response depending on the number of diaphragm elements used. The response of the differential diaphragm has a response that is highly dependent on the direction of the incident sound. The diaphragms are useful for constructing highly innovative microphones that have far greater directionality, better sensitivity, wider frequency response, and lower noise than is achievable with current technology.

A thin film silicon solar cell for use in photovoltaic cells having a carrier substrate, a front transparent conductive oxide contact, a thin film silicon solar cell layer having at least one layer of hydrogenated microcrystalline silicon or nanocrystalline silicon, and a back contact having a transparent conductive oxide contact layer and a back reflective layer comprising a white pigmented dielectric reflective media.

Photovoltaic devices or solar cells are provided. More particularly, the present invention provides photovoltaic devices having IR and / or UV absorbing nanostructured layers that increase efficiency of solar cells. In some embodiments the nanostructured materials are integrated with one or more of: crystalline silicon (single crystal or polycrystalline) solar cells and thin film (amorphous silicon, microcrystalline silicon, CdTe, CIGS and III-V materials) solar cells whose absorption is primarily in the visible region. In some embodiments the nanoparticle materials are comprised of quantum dots, rods or multipods of various sizes.

Photovoltaic devices and methods of manufacture are provided. In an embodiment, the devices comprise a micro-crystal silicon cell having an amorphous silicon layer formed on the micro-crystal cell.

[Problem(s)] A stacked photovoltaic device can be provided which is practicable and low-cost and yet has a high reliability, and also has a high photoelectric conversion efficiency. [Means for Solving the Problem] A stacked photovoltaic device comprises at least three p-i-n junction constituent devices superposed in layers, each having a p-type layer, an i-type layer and an n-type layer which are formed of silicon type non-single-crystal semiconductors. An amorphous silicon is used as the i-type layer of a first p-i-n junction, a microcrystalline silicon is used as the i-type layer of a second p-i-n junction and a microcrystalline silicon is used as the i-type layer of a third p-i-n junction, the first to third layers being in the order from the light-incident side.

Embodiments of the present invention relate to fabricating low cost polysilicon solar cell on flexible substrates using inkjet printing. Particular embodiments form polycrystalline or microcrystalline silicon solar cells on substrates utilizing liquid silane, by employing inkjet printing or other low cost commercial printing techniques including but not limited to screen printing, roller coating, gravure coating, curtain coating, spray coating and others. Specific embodiments employ silanes such as cyclopentasilane (C5H10) or cyclohexasilane (C6H12), which are liquids at room temperature but undergo a ring opening chemical reaction upon exposure to radiation of a wavelength of ultraviolet (UV) or shorter. . Opening of the rings of the liquid silane converts it into a polymerized material comprising saturated and unsaturated silicon chains of varied length. Heating to approximately 250-400° C. converts these materials into a hydrogenated amorphous silicon film. Controlled annealing at higher effective temperatures causes the amorphous film to change phase to polycrystalline or microcrystalline silicon, depending upon specific processing conditions.

A MOS or CMOS sensor for high performance imaging in broad spectral ranges including portions of the infrared spectral band. These broad spectral ranges may also include portions or all of the visible spectrum, therefore the sensor has both daylight and night vision capabilities. The sensor includes a continuous multi-layer photodiode structure on a many pixel MOS or CMOS readout array where the photodiode structure is chosen to include responses in the near infrared spectral ranges. A preferred embodiment incorporates a microcrystalline copper indium diselenide / cadmium sulfide photodiode structure on a CMOS readout array. An alternate preferred embodiment incorporates a microcrystalline silicon germanium photodiode structure on a CMOS readout array. Each of these embodiments provides night vision with image performance that greatly surpasses the GEN III night vision technology in terms of enhanced sensitivity, pixel size and pixel count. Further advantages of the invention include low electrical bias voltages, low power consumption, compact packaging, and radiation hardness. In special preferred embodiments CMOS stitching technology is used to provide multi-million pixel focal plane array sensors. One embodiments of the invention made without stitching is a two-million pixel sensor. Other preferred embodiments available using stitching techniques include sensors with 250 million (or more) pixels fabricated on a single wafer. A particular application of these very high pixel count sensors is as a focal plane array for a rapid beam steering telescope in a low earth orbit satellite useful for tracking over a 1500-meter wide track with a resolution of 0.3 meter.

A deposition apparatus and method for continuously depositing a polycrystalline material such as polysilicon or polycrystalline SiGe layer on a mobile discrete or continuous web substrate. The apparatus includes a pay-out unit for dispensing a discrete or continuous web substrate and a deposition unit that receives the discrete or continuous web substrate and deposits a series of one or more thin film layers thereon in a series of one or more deposition or processing chambers. In a preferred embodiment, polysilicon is formed by first depositing a layer of amorphous or microcrystalline silicon using PECVD and transforming said layer to polysilicon through heating or annealing with one or more lasers, lamps, furnaces or other heat sources. Laser annealing utilizing a pulsed excimer is a preferred embodiment. By controlling the processing temperature, temperature distribution within a layer of amorphous or microcrystalline silicon etc., the instant deposition apparatus affords control over the grain size of polysilicon. Passivation of polysilicon occur through treatment with a hydrogen plasma. Layers of polycrystalline SiGe may similarly be formed. The instant deposition apparatus provides for the continuous deposition of electronic devices and structures that include a layer of a polycrystalline material such as polysilicon and / or polycrystalline SiGe. Representative devices include photovoltaic devices and thin film transistors. The instant deposition apparatus also provides for the continuous deposition of chalcogenide switching or memory materials alone or in combination with other metal, insulating, and / or semiconducting layers.

A display apparatus, such as an organic light emitting diode (“OLED”) display, is driven by thin film transistors (“TFTs”), including a driving TFT and a switching TFT, and a pixel electrode. The display apparatus includes an amorphous silicon layer for the switching TFT and a microcrystalline silicon or polycrystalline silicon layer for the driving TFT. The amorphous silicon layer and the microcrystalline silicon layer are separated by an insulating layer. The apparatus provides product reliability and high image quality. A method of manufacturing the apparatus is characterized by reducing processing steps, and using a special mask which is a half tone mask or a slit mask adapted to forming a source electrode and a drain electrode of the switching TFT or the driving TFT and a semiconductor layer during a photolithographic process.

Disclosed herein is a method of forming a microcrystalline silicon film by using a raw gas containing at least a silicon compound by a high-frequency plasma CVD method, wherein the formation of the film is conducted in such a manner that the residence time, tau (ms) of the raw gas in a film deposition chamber, which is defined as tau (ms)=78.9xVxP / M, in which V is a volume (cm3) of the deposition chamber, P is a deposition pressure (Torr), and M is a total flow rate (sccm) of the raw gas, satisfies tau<40. The method permits the formation of a good-quality microcrystalline silicon film at low cost.

Thin film batteries (TFB) are fabricated by a process which eliminates and / or minimizes the use of shadow masks. A selective laser ablation process, where the laser patterning process removes a layer or stack of layers while leaving layer(s) below intact, is used to meet certain or all of the patterning requirements. For die patterning from the substrate side, where the laser beam passes through the substrate before reaching the deposited layers, a die patterning assistance layer, such as an amorphous silicon layer or a microcrystalline silicon layer, may be used to achieve thermal stress mismatch induced laser ablation, which greatly reduces the laser energy required to remove material.

The invention generally relates to a plasma enhanced chemical vapor deposition chamber for depositing amorphous or microcrystalline silicon on a glass substrate to fabricate solar voltaic cells. The chamber includes a backing plate having at least one fluid receiving conduit to receive cooling fluid to remove heat generated within the chamber by the plasma, thereby stabilizing and cooling the backing plate to assure the uniformity of deposition of materials on the surface of the substrate.

Disclosed is a thin film transistor including: a gate insulating layer covering a gate electrode; a microcrystalline semiconductor region over the gate insulating layer; a pair of amorphous semiconductor region over the microcrystalline semiconductor; a pair of impurity semiconductor layers over the amorphous semiconductor regions; and wirings over the impurity semiconductor layers. The microcrystalline semiconductor region has a surface having a projection and depression on the gate insulating layer side. The microcrystalline semiconductor region includes a first microcrystalline semiconductor region which is not covered with the amorphous regions and a second microcrystalline semiconductor region which is in contact with the amorphous semiconductor regions. A thickness d1 of the first microcrystalline semiconductor region is smaller than a thickness d2 of the second microcrystalline semiconductor region and d1 is greater than or equal to 30 nm.

A method for forming a thin film transistor of an organic light emitting display includes depositing a first metal layer on a substrate, performing a photo-etching-process (PEP) to form a gate of the TFT on the substrate, forming a gate insulating layer, a microcrystalline silicon layer, an amorphous silicon layer, and a doped n+ layer sequentially, and then performing a second PEP to remove a portion of the doped n+ layer, the amorphous silicon layer, and the microcrystalline silicon layer. The method further includes forming a second metal layer, performing a third PEP to form a source and a drain on the substrate and to simultaneously remove a portion of the doped n+ layer to expose the amorphous silicon layer, and finally, forming a passivation layer on the substrate.

A tandem thin-film silicon solar cell comprises a transparent substrate, a first unit cell positioned on the transparent substrate, the first unit cell comprising a p-type window layer, an i-type absorber layer and an n-type layer, an intermediate reflection layer positioned on the first unit cell, the intermediate reflection layer including a hydrogenated n-type microcrystalline silicon oxide of which the oxygen concentration is profiled to be gradually increased and a second unit cell positioned on the intermediate reflection layer, the second unit cell comprising a p-type window layer, an i-type absorber layer and an n-type layer.

An improved PV solar cell structure and methods for manufacturing the same are provided. In one embodiment, a photovoltaic device includes a first photoelectric conversion unit, a first transparent conductive oxide layer and a first microcrystalline silicon layer disposed between and in contact with the photoelectric conversion unit and the transparent conductive oxide layer. In another embodiment, a method of forming a photovoltaic solar cell includes providing a substrate having a first transparent conductive oxide layer disposed thereon, depositing a first microcrystalline silicon layer on the transparent conductive oxide layer, and forming a first photoelectric conversion unit on the microcrystalline silicon layer.

The invention discloses a preparation method of a double-sided passivated crystalline silicon solar cell, belonging to the technical field of photovoltaic power generation. The preparation method comprises the following steps of: firstly, respectively carrying out surface precleaning and surface texturing on P-shaped single crystal silicon and a polycrystalline silicon wafer by adopting an alkaline solution and an acid solution; secondly, diffusing by using phosphorus oxychloride as a diffusion source to form a PN junction; thirdly, removing a phosphosilicate glass on the surface of the silicon wafer by adopting a chemical wet method, and etching the edge of the silicon wafer by adopting a plasma; fourthly, preparing a silicon nitride film on the surface of an emitting region of a P-type silicon wafer by adopting a plasma enhanced chemical vapor deposition method; fifthly, preparing a mixed phase film material of hydrogenated microcrystalline silicon and amorphous silicon by adopting a hot filament chemical vapor deposition method, depositing a film at one side of the P-type silicon wafer, and passivating the defects and a dangling bond on the surface of the P-type silicon wafer; and sixthly, sintering a screen printing back electrode and a screen printing positive electrode to form the solar cell. The invention lowers the probability of compounding photo-generated minority carriers on the back surface, enhances the long-wave light quantum efficiency and creates the conditions of transportation and collection of the photo-generated carriers.

A method capable of making a semiconductor device in a plasma-assisted chemical vapor deposition (CVD) system including a chamber having a first electrode and a second electrode spaced apart from one another, the method comprising providing a substrate on the second electrode, the substrate including a surface being exposed to the first electrode, forming a semiconductor film on the surface of the substrate and applying a first bias to the second electrode during a nucleation stage of the semiconductor film till a predetermined thickness of the semiconductor film is reached, and applying a second bias to the second electrode after the predetermined thickness of the semiconductor film is reached.

A raw material composite 10 for a carbon material used in an electric double layer capacitor contains microcrystalline carbon having a layered crystal structure similar to graphite, and is formed a carbon material for an electric double layer capacitor by undergoing an activation treatment. Here, the raw material composite is characterized in that a Hardgrove grindability index HGI defined by ASTMD-409-71 is 50 or above, an interlayer distance d002 of the microcrystalline carbon determined by an X-ray diffraction method is 0.343 NM or below, and a crystallite size Lc002 of the microcrystalline carbon determined by the X-ray diffraction method is 3.0 nm or below.

A photovoltaic device is formed by depositing at least a first transparent electrode, PIN-structured or NIP-structured microcrystalline silicon layers, a second transparent electrode, and a back electrode in sequence on an electrically insulating transparent substrate. The PIN-structured or NIP-structured microcrystalline silicon layers include a p-type silicon layer, an i-type silicon layer, and an n-type silicon layer. At least one of the first transparent electrode and the second transparent electrode is a ZnO layer doped with Ga, and the Ga concentration is 15 atomic percent or less with respect to Zn.