6 results about "Microcrystalline silicon" patented technology

The invention relates to a solar cell and a photovoltaic module. The solar cell comprises a semiconductor substrate which is provided with a front surface and a back surface which are oppositely arranged; the back surface is a polished surface; the first intrinsic semiconductor layer is arranged on the back surface; the first doped microcrystalline silicon layer is arranged on one side, far away from the semiconductor substrate, of the first intrinsic semiconductor layer; the first doped microcrystalline silicon layer comprises a plurality of first microcrystal grains; wherein the ratio of the length of the first microcrystal grains to the thickness of the first doped microcrystal silicon layer is a, and a meets the following relational expression: a is more than or equal to 0.8 and less than or equal to 1.1; the included angle between the length direction of the first microcrystal grains and the thickness direction of the first doped microcrystal silicon layer is alpha, and alpha meets the following relational expression that alpha is larger than or equal to 0 degree and smaller than or equal to 45 degrees. The battery efficiency can be improved, and the preparation cost can be reduced.

The present application relates to the field of solar cells, and in particular to a solar cell and a photovoltaic module. The solar cell comprises: a substrate; a passivation layer arranged on the surface of the substrate, the passivation layer comprising an intrinsic amorphous silicon layer; an intrinsic silicon oxide layer, wherein the intrinsic silicon oxide layer is arranged on the surface of the passivation layer facing away from the substrate, the content range of high-valence state silicon oxide in the intrinsic silicon oxide layer is greater than 50% and less than or equal to 95%, and the valence state of silicon element in the high-valence state silicon oxide is greater than or equal to +2; a doped layer, wherein the doped layer comprises a doped microcrystalline silicon layer, and the doped microcrystalline silicon layer is arranged on the surface of the intrinsic silicon oxide layer facing away from the passivation layer; a transparent conductive layer, wherein the transparent conductive layer is arranged on the surface of the doped layer facing away from the intrinsic silicon oxide layer; and an electrode, arranged on the transparent conductive layer. The solar cell can solve the problem of performance limitations between the passivation layer and the doped layer caused by the presence of an incubation layer.

Embodiments of the present application disclose a driving substrate, a preparation method thereof and a display panel. The driving substrate of the embodiments of the present application is provided with a first thin film transistor in a pixel area and a second thin film transistor in a frame area. The first active layer of the first thin film transistor comprises an amorphous silicon layer and a microcrystalline silicon layer arranged in stack. The channel of the second active layer of the second thin film transistor comprises polycrystalline silicon, so that the mobility of the second thin film transistor is greater than that of the first thin film transistor. Since the polycrystalline silicon can be formed by crystallization of the amorphous silicon layer and the microcrystalline silicon layer arranged in stack as a whole, the process is simplified, so that the mobility of the second thin film transistor in the frame area can be improved while the cost is reduced.

This invention provides a method for manufacturing a heterojunction solar cell and the heterojunction solar cell itself. The cell includes an N-type monocrystalline silicon wafer. On the front side of the wafer, a first intrinsic amorphous silicon layer, an N-type amorphous silicon / microcrystalline silicon layer, a first transparent conductive film, and a first electrode are sequentially formed. On the back side of the wafer, a second intrinsic amorphous silicon layer, a P-type amorphous silicon / microcrystalline silicon layer, a second transparent conductive film, and a second electrode are sequentially formed. The N-type amorphous silicon / microcrystalline silicon layer is formed before the P-type amorphous silicon / microcrystalline silicon layer, and both are formed using N-type PECVD and P-type PECVD processes, respectively. Before the P-type PECVD process, a plasma etching process is performed on the back side of the wafer to remove the N-type amorphous silicon / microcrystalline silicon layer deposited thereon. The etching gas used in the plasma etching process includes hydrogen, an inert gas, or a mixture of both. This invention avoids the adverse effects of pre-doped elements being deposited around the opposite side and improves the parallel resistance and conversion efficiency of the cell.

The present invention provides a semiconductor device that achieves high integration and high-speed operation of integrated circuits while reducing standby power consumption. [Solution] A semiconductor device that uses a transistor having an oxide semiconductor 101 as an active layer as a switching element, and controls the supply of power voltage to a circuit 100 constituting an integrated circuit using the switching element, wherein the switching element supplies power voltage to the circuit when the circuit is operating, and stops supplying power voltage to the circuit when the circuit is stopped. The circuit to which the power voltage is supplied has one or more semiconductor elements, which are the smallest units that constitute an integrated circuit, such as transistors, diodes, capacitive elements, resistive elements, and inductors, formed using semiconductors. The semiconductor material of the semiconductor element is crystalline silicon, specifically including microcrystalline silicon, polycrystalline silicon, and monocrystalline silicon.

Disclosed in the present invention are a heterojunction solar cell and a manufacturing method therefor, and a device. The manufacturing method comprises: respectively forming, on the front face and the rear face of a silicon substrate, at least one front passivation layer made of an intrinsic amorphous silicon-based material and at least one rear passivation layer made of the intrinsic amorphous silicon-based material; respectively forming, on the at least one front passivation layer and the at least one rear passivation layer, at least one front doped layer and at least one rear doped layer, which are made of a microcrystalline silicon-based material or a nanocrystalline silicon-based material; and during the deposition of at least one of the front doped layer and the rear doped layer, placing the silicon substrate on a carrier plate, wherein one or more silicon substrate accommodating regions are provided on the upper surface of the carrier plate, and at least part of the periphery of each accommodating region is provided with a retaining edge. The present invention simplifies the manufacturing process for the heterojunction solar cell and improves the performance of the heterojunction solar cell.