234 results about "Bottom gate" patented technology

The invention provides a multiband photoresponse nerve synapse device based on a two-dimensional and organic heterostructure, an array and application, and belongs to the technical field of organic electric solid-state devices. The device provided by the invention adopts a three-end bottom gate top contact structure and comprises a gate substrate, an insulating layer, a channel layer and a source / drain electrode, and the channel layer forms an II-type heterojunction by a two-dimensional semiconductor material with a narrow-band gap characteristic and an organic semiconductor material. The heterostructure realizes ultraviolet to far infrared (365nm-10 [mu] m) multiband photoelectric response, and shows synaptic plasticity under light pulse modulation, including short-term enhancement, long-term enhancement and learning-forgetting-re-learning characteristics. Large-area array preparation of the device can be realized through methods such as chemical vapor deposition, solution spin coating, jet printing or layer-by-layer self-assembly. The technology not only can be used for brain-like learning and memory simulation, but also can be applied to the fields of sensing and memory integrated intelligent systems, optical neural networks, artificial vision, multi-mode intelligent sensing and the like.

The invention discloses a P-type tellurium oxide thin film field effect transistor and a preparation method thereof. The transistor is provided with a bottom gate top contact structure. The preparation method comprises the following steps: firstly, cleaning the silicon / silicon dioxide substrate, then depositing a tellurium oxide film as the semiconductor active layer by using a metal mask and an electron beam evaporation method, and finally preparing a layer of nickel with the thickness of about 50nm on the active layer by using the mask to serve as the source electrode and the drain electrode. Compared with a traditional tellurium oxide transistor, the tellurium oxide transistor prepared by the method has the advantages that the carrier mobility and the switching ratio are obviously improved, and the hysteresis effect can be ignored. The electrical performance of the tellurium oxide transistor with the bottom gate top contact structure is improved, and the tellurium oxide transistor has the advantages of being low in cost and simple in process step.

A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor. The at least one stacked FET includes a full gate cut structure that is used to separate different device areas from each other, a top gate cut structure that used to separate the two top transistors, and a bottom gate cut structure that is used to provide the single bottom transistor. The at least one FET device can be used to provide a SRAM containing six transistors.

The invention provides a semiconductor device with a trench gate and a forming method thereof, and the method comprises the steps: firstly executing a first exposure process and a first etching process to form a bottom gate oxide of a trench, then forming a monocrystalline silicon layer, executing a second exposure process and a second etching process to form a trench, exposing the top surface of the bottom gate oxide through the trench, and then forming the trench gate, the trench gate is located in the trench and located on the bottom gate oxide, the first exposure process and the second exposure process adopt the same mask, and the polarity of the second photoresist layer is opposite to that of the first photoresist layer. The unexpected effects of the invention are that the thickness of the bottom gate oxide of the groove can be more conveniently controlled, the bottom gate oxide of the groove is firstly formed, and then the monocrystalline silicon layer and the groove are formed, so that the problem that the bottom gate oxide is easy to seal in advance due to a high-density plasma process after the groove is formed is avoided, the process difficulty can be simplified, and the production efficiency is improved. And meanwhile, the possibility of thick bottom gate oxide is provided for the MOS device with a small critical size, and the density of the device can be improved.

An electrostatic discharge circuit, comprising a first voltage line, a second voltage line and a plurality of transistors. A first voltage signal provided by the first voltage line is greater than a second voltage signal provided by the second voltage line. The plurality of transistors are connected in series between the first voltage line and the second voltage line. At least one of the plurality of transistors is an oxide thin-film transistor, the oxide thin-film transistor comprises a top gate and a bottom gate, and the bottom gate is electrically connected to a third voltage line. The first voltage signal provided by the first voltage line is greater than a third voltage signal provided by the third voltage line.

A kind of pentacene field effect transistor of improving anti-fatigue characteristic, n-type semiconductor layer and charge trapping layer with shallow energy level trap are arranged in pentacene field effect transistor structure;Device has bottom gate type structure: gate electrode / gate insulating layer / n-type semiconductor film / charge trapping dielectric layer with shallow energy level trap / tunneling layer / pentacene / source (drain) electrode;Gate electrode is conductor, resistivity is between 0.1-0.001 Ω·cm;Gate insulating layer dielectric film is insulator, thickness range is 5-150nm;The thickness of n-type semiconductor film layer is 1-200nm;Charge trapping dielectric layer with shallow energy level hole trap, thickness is 1-100nm;Tunneling layer is insulator, thickness range is 1-20nm;Pentacene thickness range is 1-100nm;Source-drain electrode is conductor, thickness range is 50-200nm;Gate electrode is conductor.

The semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is on top of the first transistor. The second gate is electrically coupled to the second transistor. A dielectric isolation layer is between the first gate and the second gate. The first conductive contact is electrically coupled to the first gate. The second conductive contact is electrically coupled to the second gate. Control of the first gate through the first conductive contact is independent of control of the second gate through the second conductive contact.

A GHeT includes a bottom gate formed on a substrate; a first dielectric layer (DL) formed on the bottom gate; a monolayer film formed of an atomically thin material on the first DL; a bottom contact (BC) formed on part of the monolayer film; a second DL formed on the BC; a top contact (TC) formed on the second DL on top of the BC; a network of CNTs formed on the TC and the monolayer film, to define an overlap region with the monolayer film; a third DL formed on the CNT network, the monolayer film and the TC; and a top gate formed on the third DL and overlapping with the overlap region. Such GHeT design allows gate tunability of Gaussian peak position, height and width that define Gaussian transfer characteristic, thereby enabling simplified circuit architectures for various spiking neuron functions for emerging neuromorphic applications.

A semiconductor device includes a merged gate having a top gate and a bottom gate disposed within a gate column with the top gate. A lateral contact plug is disposed between the top gate and the bottom gate to connect the top gate and the bottom gate, the lateral contact plug being confined within a width of the top gate.

The invention relates to the technical field of semiconductor manufacturing, and provides a carbon nanotube thin film field effect transistor, a preparation method thereof and a chip. The preparation method comprises the following steps: providing a layer of substrate; preparing a bottom gate electrode and a gate dielectric layer on the substrate in sequence; preparing a source electrode and a drain electrode on the gate dielectric layer; preparing aminated molecular layers on the surfaces of the source electrode, the drain electrode and the gate dielectric layer; removing the amination molecular layer outside the target area; preparing a carbon nanotube film in the target area; and carrying out annealing treatment. According to the preparation method, exposure treatment is carried out on an amination molecular layer outside a target area so as to damage the amination molecular layer of a non-target area, only the amination molecular layer of the target area is reserved, an adsorption site is provided for carbon nanotube film forming in a channel area, and in the preparation process, a carbon nanotube film does not make contact with photoresist, so that the carbon nanotube film is not damaged. Residue and pollution caused by photoresist protection in the traditional carbon nanotube patterning etching process are avoided, and the use performance of the carbon nanotube thin film field effect transistor is effectively guaranteed.

Semiconductor devices and methods of forming the same include a bottom transistor having a bottom gate. A top transistor has a top gate above the bottom gate and is separated from the bottom transistor by a dielectric layer. A conductive via extends through the top gate and the dielectric layer to contact the bottom transistor. A dielectric liner between the conductive via and the top gate electrically insulates the top gate from the conductive via.

To provide a semiconductor device with a configuration that can sufficiently reduce parasitic capacitance between wirings. This will be one of the issues to address. [Solution] A stack of a first layer in which part or all of a metal thin film is oxidized and an oxide semiconductor layer is formed. In the thin-film transistor with a bottom gate structure used, the oxide semiconductor overlaps with the gate electrode layer. An oxide insulating layer is formed on a part of the body layer to serve as a channel protective layer, and when the insulating layer is formed... An oxide insulating layer is formed to cover the peripheral edges (including the sides) of the stacked oxide semiconductor layers.

To provide a reliable semiconductor device with a transistor arranged by use of an oxide semiconductor.SOLUTION: A semiconductor device comprises a transistor of a bottom gate structure including an oxide semiconductor layer. In the semiconductor device, a first insulating layer is formed in contact with the oxide semiconductor layer and doped with oxygen into a first insulating layer including oxygen in excess of a stoichiometric composition. Forming a second insulating layer on the first insulating layer, the excessive oxygen contained in the first insulating layer can be supplied to an oxide semiconductor layer efficiently. Thus, a reliable semiconductor device having a stable electric property can be provided.SELECTED DRAWING: Figure 1

The application provides an array substrate and an electronic paper display device, and relates to the field of display. The array substrate comprises a substrate, a plurality of scan lines and a plurality of data lines are arranged on the substrate, the plurality of scan lines and the plurality of data lines cross and form a plurality of pixel units, and the pixel unit comprises a pixel electrode and a first thin film transistor. The pixel electrode is arranged opposite to the substrate. The first thin film transistor comprises a gate, a semiconductor layer, a source and a drain. The gate is connected with the scan line, the source is connected with the data line, the drain is electrically connected with the source, the gate comprises a top gate, a bottom gate and a connecting layer, the top gate and the bottom gate are arranged on opposite sides of the semiconductor layer in the thickness direction of the array substrate, and the top gate and the bottom gate are electrically connected through the connecting layer. The application can effectively improve the working stability of the electronic paper display device.

To provide an IGBT (Insulative Gate Bipolar Transistor) which can reduce turn-on power loss and perform screening of a gate insulator.SOLUTION: An insulative gate bipolar transistor comprises: a gate trench 7a which extends in a specified extension direction set in advance in a plane view; a first insulator film 8a which is arranged at a bottom face of the gate trench 7a and at least a part of lateral face; a bottom gate conductive component 9a which is embedded in the gate trench 7a through the first insulator film 8a; a first split insulator film 10a which is arranged on the bottom gate conductive component 9a; an upper gate conductive component 11a which is embedded in the gate trench 7a through the first split insulator film 10a; a gate surface electrode 16 which is overlapped with one end of the gate trench 7a in the extension direction; a first contact hole 13c which electrically connects the gate surface electrode 16 with the bottom gate conductive component 9a; and a second contact hole 13a which electrically connects the gate surface electrode 16 with the upper gate conductive component 11a.SELECTED DRAWING: Figure 1

The invention discloses an infrared bipolar linearly-polarized photoelectric detector and a preparation method thereof, and the infrared bipolar linearly-polarized photoelectric detector is characterized in that a bipolar material graphene is used as a channel material, a two-dimensional N-type semiconductor material molybdenum disulfide MoS2 and an anisotropic narrow-band-gap two-dimensional material black phosphorus BP are stacked on the bipolar material graphene in sequence, and the two-dimensional N-type semiconductor material molybdenum disulfide MoS2 and the anisotropic narrow-band-gap two-dimensional material black phosphorus BP are stacked on the channel material; the polarity of the graphene is regulated and controlled by the bottom gate, the infrared bipolar linearly polarized photoelectric detector with the bipolar linear polarization detection effect that the light current symbol reversibly turns over along with the polarization direction in the infrared band is achieved, and the infrared bipolar linearly polarized photoelectric detector has the advantages of being simple in structure, easy to regulate and control, capable of remarkably improving polarization recognition precision and the signal-to-noise ratio and the like. The programmable and multifunctional integration potential is also realized.

A display substrate and a display device, the display substrate comprising a substrate and a plurality of sub-pixels (Pxij) arranged on one side of the substrate, at least one sub-pixel (Pxij) comprising a pixel driving circuit (pdc), at least one pixel driving circuit (pdc) comprising a plurality of transistors, the transistors comprising an active layer and at least one gate electrode; in the same transistor, the at least one gate electrode at least partially overlaps the active layer, and the at least one gate electrode comprises at least one of a top gate and a bottom gate; in a direction perpendicular to the plane in which the substrate lies, the bottom gate is located on the side of the active layer close to the substrate, and the top gate is located on the side of the active layer away from the substrate; the plurality of transistors at least comprises a driving transistor (T3), and the gate electrode in the driving transistor (T3) comprises a top gate (T3gt) and a bottom gate (T3gb).

A pixel of an electronic device includes a light emitting element connected between a first voltage line and a first node, a first transistor including a first electrode connected to a second node, a second electrode connected to a third node, a gate electrode connected to a fourth node, and a bottom gate electrode, a second transistor connected between a first voltage line and the first node, a third transistor connected between the first node and the second node, a fourth transistor connected between the second node and the fourth node, a fifth transistor connected between a first data line and a fifth node, a sixth transistor connected between a second data line, a seventh transistor connected between the third node and a second voltage line, an eighth transistor connected between the fifth node and the second voltage line, a first capacitor and a second capacitor.

Memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers. Memory cells in the memory-cell tiers individually comprise a horizontal transistor, a capacitor that is on a capacitor side of the horizontal transistor, and part of a digitline that is on a digitline side of the horizontal transistor. Insulator material extends from horizontally aside the capacitor side of a top gate in a lower memory-cell tier through the insulative tier that is between an upper and a lower memory-cell tiers to horizontally aside the capacitor side of a bottom gate in the upper memory-cell tier. The insulator material in the upper memory-cell tier and in the lower memory-cell tier has a laterally-outer linearly-straight surface in a vertical cross-section that is through and horizontally-elongated along an axis. The laterally-outer linearly-straight surface being one of vertical, angled from vertical away from the capacitor side by no more than 40°, or angled from vertical toward the capacitor side by no more than 30°. Methods are disclosed.

The display substrate and the display device are provided. The display substrate comprises a substrate and a plurality of sub-pixels arranged on one side of the substrate. The sub-pixel comprises a pixel driving circuit, and the pixel driving circuit comprises a plurality of transistors. The transistor comprises an active layer and at least one gate electrode. In the same transistor, the at least one gate electrode at least partially overlaps with the active layer, and the at least one gate electrode comprises at least one of a top gate and a bottom gate. The bottom gate is located on the side of the active layer close to the substrate, and the top gate is located on the side of the active layer away from the substrate. In the same pixel driving circuit, the plurality of transistors comprise at least one first type transistor and at least one second type transistor. The first type transistor comprises at least one of a top gate and a bottom gate, and the second type transistor comprises a top gate and a bottom gate. The technical scheme provided by the display substrate and the display device can reduce the difficulty of narrowing the frame of the display substrate.

The invention relates to a field effect transistor sensor based on electric field enrichment and a detection method thereof. The field effect transistor sensor sequentially comprises a substrate, a dielectric layer and a channel induction region, wherein the channel induction region is composed of a drain electrode, a source electrode and a channel region; the bottom grid electrode is located above the channel induction region and is isolated from the channel region through the dielectric layer, so that an attraction electric field is generated in the detection process, and a target object is attracted to the channel induction region; the top grid is arranged above the liquid level of the detection liquid so as to form a repulsive electric field in the detection process, and a target object is repelled away from the surface of the detection liquid, so that electric field enrichment is realized in cooperation with the bottom grid. Through the synergistic effect of the top gate and the bottom gate, the local concentration and capture efficiency of a target object in a channel sensing region can be remarkably improved, the problems of slow response, insufficient sensitivity and the like caused by the fact that a traditional field effect transistor depends on passive diffusion are effectively solved, and rapid and high-sensitivity detection of the trace target object is achieved.

The invention provides a display panel and a display device. The display panel gate drive circuit comprises a signal generation module and an output module which are electrically connected, the signal generation module comprises at least one first-type signal transistor, the output module comprises at least one output transistor, and the first-type signal transistor and the output transistor are both P-type transistors. A shading layer of the display panel comprises a first signal bottom grid electrode of a first type signal transistor and an output bottom grid electrode of an output transistor. According to the invention, the proportion of the number of the output transistors with the output bottom gates in the output module is greater than or equal to the proportion of the number of the first-type signal transistors with the first signal bottom gates in the signal generation module, so that the proportion of double gates of the P-type transistors in the signal generation module is reduced; equivalently, the area of the bottom grid electrode in the grid electrode driving circuit is reduced, so that the water vapor invasion area in the light shielding layer is reduced, and the technical problem that the light shielding metal layer of the display panel is corroded is solved.

The present disclosure provides a ferroelectric device and a preparation method thereof, which can be applied to the technical field of semiconductors. The ferroelectric device comprises a substrate layer; a bottom gate electrode located in the substrate layer; a ferroelectric layer located in the ferroelectric device, a lower surface of the ferroelectric layer being in contact with the bottom gate electrode; a first device isolation layer surrounding the ferroelectric layer; a channel layer in contact with an upper surface of the ferroelectric layer; a source electrode, a drain electrode and a top gate electrode, all of which are in contact with an upper surface of the channel layer; a second device isolation layer between the source electrode, the drain electrode and the top gate electrode; and a stop layer between the first device isolation layer and the second device isolation layer, and surrounding the source electrode, the drain electrode and the top gate electrode.

The invention provides a monolithic three-dimensional integrated photoelectric detector and a preparation method thereof. The preparation method comprises the following steps: forming an isolation passivation layer on a readout integrated circuit serving as a substrate of the photoelectric detector; forming a source conductive through hole, a drain conductive through hole and a bottom gate contact hole in the isolation passivation layer; a conductive material is deposited and planarized, the source electrode conductive through hole, the drain electrode conductive through hole and the bottom gate contact hole are filled with the conductive material, the conductive material in the source electrode conductive through hole forms a source electrode conductive channel, the conductive material in the drain electrode conductive through hole forms a drain electrode conductive channel, and the conductive material in the bottom gate contact hole forms a bottom gate electrode layer; forming a bottom gate dielectric layer on the planarized surface, and forming a channel layer on the bottom gate dielectric layer; forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are electrically connected with the connecting port of the read-out integrated circuit through a source electrode conductive channel and a drain electrode conductive channel respectively; and forming a top gate structure which comprises a top gate dielectric layer and a photosensitive layer.

A thin film device is provided, comprising: a first oxide semiconductor thin film transistor, comprising a top gate electrode, a first metal oxide thin film, and a top gate insulating film located between the top gate electrode and the first metal oxide film; a second oxide semiconductor thin film transistor, comprising a bottom gate electrode, a second metal oxide thin film, and a bottom gate insulating film located between the bottom gate electrode and the second metal oxide film; a bottom gate insulating layer, comprising the bottom gate insulating film; and a storage capacitor configured to store a signal voltage applied to the bottom gate electrode.

The invention belongs to the technical field of semiconductor light-emitting devices, and particularly relates to an organic field effect light-emitting transistor and a preparation method thereof. The organic field effect light emitting transistor provided by the invention comprises a substrate; the bottom gate electrode, the first insulating layer, the source electrode and the active layer are arranged on the upper surface of the substrate, the source electrode makes contact with one side of the active layer, and a hole transport layer, a light-emitting layer, an electron transport layer and a drain electrode are sequentially arranged on the part, close to the other side of the active layer, of the upper surface in a stacked mode; the second insulating layer covers the upper surface of the source electrode, the residual upper surface of the active layer and the residual upper surface of the first insulating layer; and the top gate electrode is arranged on a part of the upper surface of the second insulating layer. According to the organic field effect light-emitting transistor provided by the invention, carrier injection and current channel control are optimized while high mobility is realized, and the driving capability, the light-emitting uniformity and the stability of a device are effectively improved, so that an OLET device with high performance and low power consumption is obtained.

The application belongs to the technical field of organic semiconductor electronic devices, and discloses a flexible threshold value adjustable negative capacitance transistor and a preparation method, and a small logic circuit. The flexible threshold value adjustable negative capacitance transistor comprises a flexible substrate, an organic semiconductor layer, an organic dielectric layer, a source-drain electrode and two gate electrodes. The preparation method is as follows: a bottom gate electrode is prepared on the surface of the flexible substrate and an organic ferroelectric film is spin-coated; an organic polymer film is spin-coated on the surface of the organic dielectric layer as a semiconductor channel layer; a source / drain metal electrode is prepared; finally, an organic ferroelectric film is spin-coated and a top gate electrode is prepared. The application utilizes the negative capacitance principle of the organic ferroelectric transistor to reduce the working voltage and power consumption, and the double-gate structure is made to make the threshold voltage of the transistor adjustable, which has a great effect in the flexible logic circuit based on the unipolar device.

A stacked semiconductor structure including a top transistor stacked above a bottom transistor, and a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor.

The invention discloses an enhanced n-type two-dimensional transistor based on a p-type diamond film and a preparation method of the enhanced n-type two-dimensional transistor. The problem that a depletion mode of a two-dimensional transistor is difficult to convert into an enhanced mode in the prior art is mainly solved. According to the scheme, the method comprises the following steps: firstly, preparing a buried gate of a transistor on an insulating substrate, then transferring a grown p-type diamond film to a gate metal electrode and the surface of the insulating substrate, then transferring a grown two-dimensional material to the p-type film to serve as a transistor channel layer, and preparing a source electrode and a drain electrode; a p-type diamond film is introduced to serve as a p-type gate of the n-type two-dimensional transistor, electrons of a two-dimensional material channel without the gate are exhausted, and meanwhile, induced charge transfer doping of a substrate to a channel layer is isolated, so that the conductivity of the n-type two-dimensional transistor is influenced. According to the invention, the conduction mode of the n-type two-dimensional transistor is converted from a depletion mode to an enhancement mode, the static power consumption of the transistor can be effectively reduced, and the method can be used for preparing the enhanced two-dimensional field effect transistor with high performance.

The invention provides a heterogeneous phototransistor based on double ferroelectric layers and a preparation method and application of the heterogeneous phototransistor, and belongs to the technical field of high-performance sensing and sensing, storage and calculation integration. The heterogeneous phototransistor comprises a bottom gate substrate, a bottom gate dielectric layer and a heterostructure which is sequentially stacked on the bottom gate dielectric layer, the heterostructure is composed of a ferroelectric semiconductor bismuth oxygen selenium layer, a bismuth selenite dielectric layer and a ferroelectric semiconductor alpha-phase indium selenide layer, and source and drain electrodes are arranged on the two sides of the ferroelectric semiconductor alpha-phase indium selenide layer. According to the invention, the directional sensitive response to linear polarized light is realized by utilizing the structural symmetry breaking characteristic of the ferroelectric semiconductors in the double-ferroelectric-layer structure, and meanwhile, through the polarization coupling effect between the two layers of ferroelectric semiconductors and the assistance of the middle bismuth oxyselenite dielectric layer for inhibiting electrostatic energy and blocking carrier migration, the linear polarized light can be effectively absorbed. And the polarization state is effectively stabilized, so that the device has remarkable non-volatile electrical characteristics. According to the invention, in-situ encryption of the optical information at the sensing end can be realized.