103 results about "Bottom gate" patented technology

The invention discloses a P-type tellurium oxide thin film field effect transistor and a preparation method thereof. The transistor is provided with a bottom gate top contact structure. The preparation method comprises the following steps: firstly, cleaning the silicon / silicon dioxide substrate, then depositing a tellurium oxide film as the semiconductor active layer by using a metal mask and an electron beam evaporation method, and finally preparing a layer of nickel with the thickness of about 50nm on the active layer by using the mask to serve as the source electrode and the drain electrode. Compared with a traditional tellurium oxide transistor, the tellurium oxide transistor prepared by the method has the advantages that the carrier mobility and the switching ratio are obviously improved, and the hysteresis effect can be ignored. The electrical performance of the tellurium oxide transistor with the bottom gate top contact structure is improved, and the tellurium oxide transistor has the advantages of being low in cost and simple in process step.

A kind of pentacene field effect transistor of improving anti-fatigue characteristic, n-type semiconductor layer and charge trapping layer with shallow energy level trap are arranged in pentacene field effect transistor structure;Device has bottom gate type structure: gate electrode / gate insulating layer / n-type semiconductor film / charge trapping dielectric layer with shallow energy level trap / tunneling layer / pentacene / source (drain) electrode;Gate electrode is conductor, resistivity is between 0.1-0.001 Ω·cm;Gate insulating layer dielectric film is insulator, thickness range is 5-150nm;The thickness of n-type semiconductor film layer is 1-200nm;Charge trapping dielectric layer with shallow energy level hole trap, thickness is 1-100nm;Tunneling layer is insulator, thickness range is 1-20nm;Pentacene thickness range is 1-100nm;Source-drain electrode is conductor, thickness range is 50-200nm;Gate electrode is conductor.

To provide a semiconductor device with a configuration that can sufficiently reduce parasitic capacitance between wirings. This will be one of the issues to address. [Solution] A stack of a first layer in which part or all of a metal thin film is oxidized and an oxide semiconductor layer is formed. In the thin-film transistor with a bottom gate structure used, the oxide semiconductor overlaps with the gate electrode layer. An oxide insulating layer is formed on a part of the body layer to serve as a channel protective layer, and when the insulating layer is formed... An oxide insulating layer is formed to cover the peripheral edges (including the sides) of the stacked oxide semiconductor layers.

The application provides an array substrate and an electronic paper display device, and relates to the field of display. The array substrate comprises a substrate, a plurality of scan lines and a plurality of data lines are arranged on the substrate, the plurality of scan lines and the plurality of data lines cross and form a plurality of pixel units, and the pixel unit comprises a pixel electrode and a first thin film transistor. The pixel electrode is arranged opposite to the substrate. The first thin film transistor comprises a gate, a semiconductor layer, a source and a drain. The gate is connected with the scan line, the source is connected with the data line, the drain is electrically connected with the source, the gate comprises a top gate, a bottom gate and a connecting layer, the top gate and the bottom gate are arranged on opposite sides of the semiconductor layer in the thickness direction of the array substrate, and the top gate and the bottom gate are electrically connected through the connecting layer. The application can effectively improve the working stability of the electronic paper display device.

The invention discloses an infrared bipolar linearly-polarized photoelectric detector and a preparation method thereof, and the infrared bipolar linearly-polarized photoelectric detector is characterized in that a bipolar material graphene is used as a channel material, a two-dimensional N-type semiconductor material molybdenum disulfide MoS2 and an anisotropic narrow-band-gap two-dimensional material black phosphorus BP are stacked on the bipolar material graphene in sequence, and the two-dimensional N-type semiconductor material molybdenum disulfide MoS2 and the anisotropic narrow-band-gap two-dimensional material black phosphorus BP are stacked on the channel material; the polarity of the graphene is regulated and controlled by the bottom gate, the infrared bipolar linearly polarized photoelectric detector with the bipolar linear polarization detection effect that the light current symbol reversibly turns over along with the polarization direction in the infrared band is achieved, and the infrared bipolar linearly polarized photoelectric detector has the advantages of being simple in structure, easy to regulate and control, capable of remarkably improving polarization recognition precision and the signal-to-noise ratio and the like. The programmable and multifunctional integration potential is also realized.

A display substrate and a display device, the display substrate comprising a substrate and a plurality of sub-pixels (Pxij) arranged on one side of the substrate, at least one sub-pixel (Pxij) comprising a pixel driving circuit (pdc), at least one pixel driving circuit (pdc) comprising a plurality of transistors, the transistors comprising an active layer and at least one gate electrode; in the same transistor, the at least one gate electrode at least partially overlaps the active layer, and the at least one gate electrode comprises at least one of a top gate and a bottom gate; in a direction perpendicular to the plane in which the substrate lies, the bottom gate is located on the side of the active layer close to the substrate, and the top gate is located on the side of the active layer away from the substrate; the plurality of transistors at least comprises a driving transistor (T3), and the gate electrode in the driving transistor (T3) comprises a top gate (T3gt) and a bottom gate (T3gb).

A pixel of an electronic device includes a light emitting element connected between a first voltage line and a first node, a first transistor including a first electrode connected to a second node, a second electrode connected to a third node, a gate electrode connected to a fourth node, and a bottom gate electrode, a second transistor connected between a first voltage line and the first node, a third transistor connected between the first node and the second node, a fourth transistor connected between the second node and the fourth node, a fifth transistor connected between a first data line and a fifth node, a sixth transistor connected between a second data line, a seventh transistor connected between the third node and a second voltage line, an eighth transistor connected between the fifth node and the second voltage line, a first capacitor and a second capacitor.

Memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers. Memory cells in the memory-cell tiers individually comprise a horizontal transistor, a capacitor that is on a capacitor side of the horizontal transistor, and part of a digitline that is on a digitline side of the horizontal transistor. Insulator material extends from horizontally aside the capacitor side of a top gate in a lower memory-cell tier through the insulative tier that is between an upper and a lower memory-cell tiers to horizontally aside the capacitor side of a bottom gate in the upper memory-cell tier. The insulator material in the upper memory-cell tier and in the lower memory-cell tier has a laterally-outer linearly-straight surface in a vertical cross-section that is through and horizontally-elongated along an axis. The laterally-outer linearly-straight surface being one of vertical, angled from vertical away from the capacitor side by no more than 40°, or angled from vertical toward the capacitor side by no more than 30°. Methods are disclosed.

The display substrate and the display device are provided. The display substrate comprises a substrate and a plurality of sub-pixels arranged on one side of the substrate. The sub-pixel comprises a pixel driving circuit, and the pixel driving circuit comprises a plurality of transistors. The transistor comprises an active layer and at least one gate electrode. In the same transistor, the at least one gate electrode at least partially overlaps with the active layer, and the at least one gate electrode comprises at least one of a top gate and a bottom gate. The bottom gate is located on the side of the active layer close to the substrate, and the top gate is located on the side of the active layer away from the substrate. In the same pixel driving circuit, the plurality of transistors comprise at least one first type transistor and at least one second type transistor. The first type transistor comprises at least one of a top gate and a bottom gate, and the second type transistor comprises a top gate and a bottom gate. The technical scheme provided by the display substrate and the display device can reduce the difficulty of narrowing the frame of the display substrate.

The invention relates to a field effect transistor sensor based on electric field enrichment and a detection method thereof. The field effect transistor sensor sequentially comprises a substrate, a dielectric layer and a channel induction region, wherein the channel induction region is composed of a drain electrode, a source electrode and a channel region; the bottom grid electrode is located above the channel induction region and is isolated from the channel region through the dielectric layer, so that an attraction electric field is generated in the detection process, and a target object is attracted to the channel induction region; the top grid is arranged above the liquid level of the detection liquid so as to form a repulsive electric field in the detection process, and a target object is repelled away from the surface of the detection liquid, so that electric field enrichment is realized in cooperation with the bottom grid. Through the synergistic effect of the top gate and the bottom gate, the local concentration and capture efficiency of a target object in a channel sensing region can be remarkably improved, the problems of slow response, insufficient sensitivity and the like caused by the fact that a traditional field effect transistor depends on passive diffusion are effectively solved, and rapid and high-sensitivity detection of the trace target object is achieved.

The invention provides a display panel and a display device. The display panel gate drive circuit comprises a signal generation module and an output module which are electrically connected, the signal generation module comprises at least one first-type signal transistor, the output module comprises at least one output transistor, and the first-type signal transistor and the output transistor are both P-type transistors. A shading layer of the display panel comprises a first signal bottom grid electrode of a first type signal transistor and an output bottom grid electrode of an output transistor. According to the invention, the proportion of the number of the output transistors with the output bottom gates in the output module is greater than or equal to the proportion of the number of the first-type signal transistors with the first signal bottom gates in the signal generation module, so that the proportion of double gates of the P-type transistors in the signal generation module is reduced; equivalently, the area of the bottom grid electrode in the grid electrode driving circuit is reduced, so that the water vapor invasion area in the light shielding layer is reduced, and the technical problem that the light shielding metal layer of the display panel is corroded is solved.

The present disclosure provides a ferroelectric device and a preparation method thereof, which can be applied to the technical field of semiconductors. The ferroelectric device comprises a substrate layer; a bottom gate electrode located in the substrate layer; a ferroelectric layer located in the ferroelectric device, a lower surface of the ferroelectric layer being in contact with the bottom gate electrode; a first device isolation layer surrounding the ferroelectric layer; a channel layer in contact with an upper surface of the ferroelectric layer; a source electrode, a drain electrode and a top gate electrode, all of which are in contact with an upper surface of the channel layer; a second device isolation layer between the source electrode, the drain electrode and the top gate electrode; and a stop layer between the first device isolation layer and the second device isolation layer, and surrounding the source electrode, the drain electrode and the top gate electrode.

The invention provides a monolithic three-dimensional integrated photoelectric detector and a preparation method thereof. The preparation method comprises the following steps: forming an isolation passivation layer on a readout integrated circuit serving as a substrate of the photoelectric detector; forming a source conductive through hole, a drain conductive through hole and a bottom gate contact hole in the isolation passivation layer; a conductive material is deposited and planarized, the source electrode conductive through hole, the drain electrode conductive through hole and the bottom gate contact hole are filled with the conductive material, the conductive material in the source electrode conductive through hole forms a source electrode conductive channel, the conductive material in the drain electrode conductive through hole forms a drain electrode conductive channel, and the conductive material in the bottom gate contact hole forms a bottom gate electrode layer; forming a bottom gate dielectric layer on the planarized surface, and forming a channel layer on the bottom gate dielectric layer; forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are electrically connected with the connecting port of the read-out integrated circuit through a source electrode conductive channel and a drain electrode conductive channel respectively; and forming a top gate structure which comprises a top gate dielectric layer and a photosensitive layer.

The application belongs to the technical field of organic semiconductor electronic devices, and discloses a flexible threshold value adjustable negative capacitance transistor and a preparation method, and a small logic circuit. The flexible threshold value adjustable negative capacitance transistor comprises a flexible substrate, an organic semiconductor layer, an organic dielectric layer, a source-drain electrode and two gate electrodes. The preparation method is as follows: a bottom gate electrode is prepared on the surface of the flexible substrate and an organic ferroelectric film is spin-coated; an organic polymer film is spin-coated on the surface of the organic dielectric layer as a semiconductor channel layer; a source / drain metal electrode is prepared; finally, an organic ferroelectric film is spin-coated and a top gate electrode is prepared. The application utilizes the negative capacitance principle of the organic ferroelectric transistor to reduce the working voltage and power consumption, and the double-gate structure is made to make the threshold voltage of the transistor adjustable, which has a great effect in the flexible logic circuit based on the unipolar device.

A stacked semiconductor structure including a top transistor stacked above a bottom transistor, and a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor.

The invention discloses a method and a structure for integrating a double-gate JFET (junction field effect transistor) device in a bipolar junction transistor process, and the method comprises the steps: providing a substrate, and forming a buried layer structure, an epitaxial layer and an isolation structure of the bipolar junction transistor and the JFET device on the substrate; carrying out penetration doping and well region doping in the epitaxial layer; forming a collector crystalline region, a base crystalline region, a bottom gate crystalline region, a top gate crystalline region, a source crystalline layer and a drain crystalline region above the epitaxial layer; depositing a dielectric layer on the epitaxial layer, etching to form a base region window, and forming a heavily doped collector region, a heavily doped outer base region, a heavily doped bottom gate, a heavily doped top gate, a source region and a drain region through the base region window; s500, forming an emitter region window, and forming an emitter crystalline region in the emitter region window; and forming electrodes of the bipolar junction transistor and the JFET device on the dielectric layer. According to the invention, the high-speed bipolar junction transistor and the JFET device can be integrated in a single manufacturing process under the condition that a large amount of process complexity is not increased.

The utility model provides an annular discharging gate of a large pellet silo, which aims at solving the technical problems that materials are stored at the bottom of the silo and the silo is unstable when the existing large pellet silo is used for discharging materials. The discharging gate comprises a silo wall, a silo bottom, a silo bottom gate plate, a lifting plate and a lifting assembly. The silo bottom comprises an upper conical bottom plate and a lower conical bottom plate, the top end of the upper conical bottom plate is fixedly connected with the bottom end of the silo wall, and the bottom end of the lower conical bottom plate is connected with the bottom end of the cylindrical silo bottom flashboard; the lifting plate comprises a vertical plate and a flat plate, the outer wall of the vertical plate is connected with the inner side of the bottom end of the upper conical bottom plate, the inner ring of the flat plate is fixedly connected with the bottom end of the vertical plate, and the lower surface of the flat plate is fixedly connected with the top end of the bin bottom flashboard. The two ends of the lifting assembly are connected with the upper conical bottom plate and the flat plate of the lifting plate correspondingly. According to the device, the advantages of high compressive strength and good fluidity of pellets are utilized, smooth discharging at the bottom of the silo is guaranteed, silo deviation is avoided, and the problems of dead material areas at the bottom of the silo are solved.

A SnS2 / MoSe2 heterojunction tunneling field effect transistor based on double-gate regulation and its preparation method and application. The present application belongs to the technical field of multifunctional optoelectronic transistors. The purpose of the present application is to solve the technical problem that the heat-activated carriers of the existing tunneling field effect transistor are greatly affected by the environment and have a short service life. The tunneling field effect transistor of the present application uses graphene nanosheet / h-BN nanosheet as the top gate, SiO2 / Si as the bottom gate, and SnS2 / MoSe2 as the heterojunction. Method: First, obtain SnS2, MoSe2, h-BN, graphene nanosheet on the bottom gate by mechanical exfoliation method; then transfer MoSe2, h-BN, graphene nanosheet onto SnS2 nanosheet in sequence by dry transfer method; then evaporate metal bonding layer / Au electrode layer to obtain gate, drain and source, and obtain tunneling field effect transistor after annealing. It is applied to the field of logic circuit components.

The application discloses a display driving circuit and a display panel, which at least comprise a double-gate structure and a gate selection unit connected with the gate of the double-gate structure; the double-gate structure comprises a bottom gate, a top gate, a source and a drain controlled to be turned on by the bottom gate and / or the top gate; the bottom gate is connected with a first gate driving module through the gate selection unit, the top gate is connected with a second gate driving module through the gate selection unit, the source is connected with a data line, and the drain is connected with a pixel electrode, so as to control the working voltage of the gate of the double-gate structure through the gate selection unit, and then the display gray scale of the pixel electrode is controlled. Through the above structure, the gray scale number of picture display is improved.

This invention provides a shift register, a gate driving circuit, and a display device, relating to the field of display technology, for better narrowing the bezel width of display products. The shift register includes an output circuit, which includes a first output transistor, which is a dual-gate transistor. The top gate of the first output transistor is coupled to a cascaded signal output terminal, and the bottom gate of the first output transistor is coupled to a control terminal. The first electrode of the first output transistor is coupled to a first-level signal input terminal, and the second electrode of the first output transistor is coupled to a gate driving signal output terminal. The cascaded signal output terminal is used to control the first output transistor to be turned on or off, and the control terminal is used to control the characteristic parameters of the first output transistor.

The invention relates to the technical field of semiconductors, and discloses a double-gate two-dimensional transistor for multifunctional storage and logic calculation, which comprises a substrate, a floating gate layer, a tunneling layer, a channel layer, a top gate insulating layer, a bottom gate electrode, a top gate electrode, a source electrode and a drain electrode, the substrate is an N-type single-polished silicon oxide wafer, the floating gate layer is a graphene layer, the tunneling layer is a hexagonal boron nitride layer, the channel layer is a molybdenum disulfide layer, and the top gate insulating layer is a hexagonal boron nitride layer; the floating gate layer is arranged on the upper surface of the substrate, the tunneling layer covers the upper surface of the floating gate layer, the channel layer is arranged on the upper surface of the tunneling layer, and the top gate insulating layer covers the upper surface of the channel layer. By means of a heterogeneous stack structure of h-BN / MoS graphene and a double-gate independent regulation and control mechanism, single device integration of light perception, nonvolatile storage and logic operation is achieved, additional splicing links of sensing, storage and calculation units in a traditional system are omitted, and a hardware architecture is greatly simplified.

The present disclosure relates to a complementary field effect transistor (CFET) device (1) and a method of manufacturing a CFET device (1). The CFET device (1) comprises a bottom transistor structure (10) arranged in a bottom layer of the CFET device (1), the bottom transistor structure (10) comprising: at least one bottom channel (11); and a bottom gate (12) for electrically controlling the at least one bottom channel (11). The CFET device (1) further comprises a top transistor structure (20) arranged in the top layer of the CFET device (1) and over the bottom layer, the top transistor structure (20) comprising: at least one top channel (21); a top gate for electrically controlling the at least one top channel (21); the at least one top channel (21) is arranged at an angle to the at least one bottom channel (11).

Provided are a display substrate and a display apparatus. The display substrate comprises a base substrate and a plurality of sub-pixels disposed on a side of the base substrate, wherein each sub-pixel comprises a pixel driver circuit, the pixel driver circuit comprises a plurality of transistors, and each transistor comprises an active layer and at least one gate; in the same transistor, at least one gate at least partially overlaps the active layer, and the at least one gate comprises at least one of a top gate and a bottom gate; the bottom gate is located on a side of the active layer close to the base substrate, and the top gate may be located on a side of the active layer away from the base substrate; in the same pixel driver circuit, the plurality of transistors comprises at least one first-type transistor and at least one second-type transistor, wherein the first-type transistor may comprise at least one of the top gate and the bottom gate, and the second-type transistor comprises the top gate and the bottom gate.

A display panel includes a pixel driving circuit including a first type transistor and a second type transistor, the display panel further includes a base substrate, a first active layer located on a side of the base substrate, a second active layer located on the side of the first active layer away from the base substrate, a first conductive layer located between the first active layer and the second active layer; at least partial structure of the first active layer is used to form a channel region of the first type transistor; at least partial structure of the second active layer is used to form the channel region of the second type transistor; partial structure of the first conductive layer is used to form the gate of the first type transistor, partial structure of the first conductive layer is used to form the bottom gate of the second type transistor.

The invention discloses a programmable optical pulse tuning short-wave infrared photoelectric detector and a preparation method, and relates to the technical field of two-dimensional photoelectric devices. Comprising a patterned bottom gate electrode, a two-dimensional ferroelectric material layer, an insulating dielectric layer, a two-dimensional semiconductor channel layer, source and drain electrodes and an upper insulating protection layer, and an asymmetric ferroelectric floating gate structure is formed. By utilizing the semi-floating gate coupling effect between the ferroelectric floating gate and the channel, the device can realize bidirectional reversible adjustment of light responsivity under different light programming conditions, and can form a plurality of stable and distinguishable light response states under the condition of no external gate voltage. The preparation method is simple in process and comprises the steps of substrate cleaning, bottom gate pattern preparation, CIPS / h-BN / BP stacking, source and drain electrode transfer, protection layer packaging and annealing treatment. The device has the advantages of low power consumption, full light control, multistage programmability and the like, and can be applied to visual perception, image convolution processing, photoelectric neuromorphic calculation and the like.

A semiconductor device includes: a substrate including a trench; a bottom gate electrode suitable for gap-filling a lower portion of the trench and including a silicon-doped first metal nitride; and a top gate electrode formed over the bottom gate electrode, and including a silicon-doped second metal nitride having a higher silicon content than a silicon content of the bottom gate electrode and having a higher ratio of a metal content to a nitrogen content than a ratio of a metal content to a nitrogen content of the bottom gate electrode.

A SiC trench power device comprises at least one SiC MOSFET and a SiC super barrier rectifier (SBR) integrated together in each unit cell having at least one-step gate trench structure for the SiC MOSFET. The at least one step gate trench comprising a first top gate trench and at least one first bottom gate trench; the first top gate trench has a trench width larger than that of the at least one first bottom gate trench; a gate electrode of the SiC MOSFET is disposed in the first top gate trench surrounded with a first insulating film on a bottom region of the first top gate trench, and surrounded with a first gate oxide on sidewalls of the top step gate trench; the first insulating film fills up the at least one first bottom gate trench having a thickness greater than that of the first gate oxide; and a Y-shape grounded P-shield region surrounds the at least one first bottom gate trench for the first gate oxide electric field reduction and short circuit capability enhancement.

According to one aspect, a method of operating a memory is provided. The method may include applying a first power supply voltage to a common source during a program precharge process. The method may include applying a first voltage to a first bottom gate line and applying a second voltage to a second bottom gate line starting at a first moment of the program precharge process. The method may include applying a second power supply voltage to the first bottom gate line and applying a third voltage to the second bottom gate line after the first moment of the program precharge process.

The invention belongs to the technical field of semiconductor devices, and particularly relates to a low-temperature preparation method for improving performance and stability of a metal oxide thin film transistor. According to the preparation method disclosed by the invention, the thin film transistor is firstly subjected to fluorine plasma treatment and then subjected to low-temperature annealing treatment, so that the electrical property and the stability of the thin film transistor are effectively improved, and compared with a traditional high-temperature annealing technology, the temperature thermal budget is reduced, and the flexible application of the device is expanded. The metal oxide thin film transistor prepared by the invention comprises a substrate, a bottom gate electrode, a gate dielectric layer, a channel layer, a first source electrode, a first drain electrode, a second source electrode and a second drain electrode. In the preparation process, reasonable plasma processing sputtering power and time are set, metal hydroxyl defects existing on the surface of the active channel layer are reduced under the condition that a channel layer material is not damaged, and therefore the performance such as the switching ratio and the subthreshold swing of the thin film transistor is improved.

The application belongs to the technical field of chip structure design, and more particularly to a dynamic random access memory with adjustable storage time and a preparation method thereof. The dynamic random access memory has a heterogeneous integrated sensing and computing integrated structure, wherein the drain of the first field effect transistor is connected with the bottom gate electrode of the second floating gate transistor. During operation, the bottom gate injection charge of the second floating gate transistor is adjusted by applying a pulse voltage signal to the first field effect transistor, the gate voltage of the bottom gate of the second floating gate transistor is instantaneously regulated, the potential barrier of the floating gate and the tunneling layer is changed, the number of stored charges in the floating gate storage layer is changed to realize the modulation of the threshold voltage of the second floating gate transistor, and flexible storage function is realized.