294 results about "Bottom gate" patented technology

The disclosure relates to a CFET device (100) comprising: a bottom FET device (130) and a top FET device (140) stacked on top of the bottom FET device (130), the bottom FET device (130) comprising a bottom channel nanostructure (132) and a bottom gate electrode (134) comprising a side gate portion (134a) arranged along a first side surface (132a) of the bottom channel nano structure, and the top FET device (140) comprising a top channel nanosheet (142) and a top gate electrode (144) configured to define a tri-gate with respect to the top channel nanosheet and comprising a side gate portion (144b) arranged along a second side surface (142b) of the top channel nanosheet, wherein the side gate portion (134a) of the bottom gate electrode (134) defines a via contact portion protruding outside the top gate electrode (144) and the first side surface (142a) of the top channel nanosheet (142); and atop gate contact via (146) for coupling the top gate electrode (144) to a first conductive line (124) over the top FET device (140) and a bottom gate contact via (136) for coupling the via contact portion (134a) of the bottom gate electrode (134) to a second conductive line (128) over the top FET device (140).

The invention provides a multiband photoresponse nerve synapse device based on a two-dimensional and organic heterostructure, an array and application, and belongs to the technical field of organic electric solid-state devices. The device provided by the invention adopts a three-end bottom gate top contact structure and comprises a gate substrate, an insulating layer, a channel layer and a source / drain electrode, and the channel layer forms an II-type heterojunction by a two-dimensional semiconductor material with a narrow-band gap characteristic and an organic semiconductor material. The heterostructure realizes ultraviolet to far infrared (365nm-10 [mu] m) multiband photoelectric response, and shows synaptic plasticity under light pulse modulation, including short-term enhancement, long-term enhancement and learning-forgetting-re-learning characteristics. Large-area array preparation of the device can be realized through methods such as chemical vapor deposition, solution spin coating, jet printing or layer-by-layer self-assembly. The technology not only can be used for brain-like learning and memory simulation, but also can be applied to the fields of sensing and memory integrated intelligent systems, optical neural networks, artificial vision, multi-mode intelligent sensing and the like.

The invention discloses a P-type tellurium oxide thin film field effect transistor and a preparation method thereof. The transistor is provided with a bottom gate top contact structure. The preparation method comprises the following steps: firstly, cleaning the silicon / silicon dioxide substrate, then depositing a tellurium oxide film as the semiconductor active layer by using a metal mask and an electron beam evaporation method, and finally preparing a layer of nickel with the thickness of about 50nm on the active layer by using the mask to serve as the source electrode and the drain electrode. Compared with a traditional tellurium oxide transistor, the tellurium oxide transistor prepared by the method has the advantages that the carrier mobility and the switching ratio are obviously improved, and the hysteresis effect can be ignored. The electrical performance of the tellurium oxide transistor with the bottom gate top contact structure is improved, and the tellurium oxide transistor has the advantages of being low in cost and simple in process step.

The invention provides a shift register, a gate drive circuit and a display device, relates to the technical field of display, and is used for narrowing the frame width of a display product better. The shift register comprises an output circuit, the output circuit comprises a first output transistor, the first output transistor comprises a double-gate transistor, a top gate of the first output transistor is coupled with a cascade signal output end, a bottom gate of the first output transistor is coupled with a regulation and control end, and the double-gate transistor comprises a double-gate transistor. A first electrode of the first output transistor is coupled with a first level signal input end, and a second electrode of the first output transistor is coupled with a gate driving signal output end; the cascade signal output end is used for controlling the first output transistor to be switched on or switched off, and the regulation and control end is used for controlling characteristic parameters of the first output transistor.

A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor. The at least one stacked FET includes a full gate cut structure that is used to separate different device areas from each other, a top gate cut structure that used to separate the two top transistors, and a bottom gate cut structure that is used to provide the single bottom transistor. The at least one FET device can be used to provide a SRAM containing six transistors.

The invention provides a semiconductor device with a trench gate and a forming method thereof, and the method comprises the steps: firstly executing a first exposure process and a first etching process to form a bottom gate oxide of a trench, then forming a monocrystalline silicon layer, executing a second exposure process and a second etching process to form a trench, exposing the top surface of the bottom gate oxide through the trench, and then forming the trench gate, the trench gate is located in the trench and located on the bottom gate oxide, the first exposure process and the second exposure process adopt the same mask, and the polarity of the second photoresist layer is opposite to that of the first photoresist layer. The unexpected effects of the invention are that the thickness of the bottom gate oxide of the groove can be more conveniently controlled, the bottom gate oxide of the groove is firstly formed, and then the monocrystalline silicon layer and the groove are formed, so that the problem that the bottom gate oxide is easy to seal in advance due to a high-density plasma process after the groove is formed is avoided, the process difficulty can be simplified, and the production efficiency is improved. And meanwhile, the possibility of thick bottom gate oxide is provided for the MOS device with a small critical size, and the density of the device can be improved.

An electrostatic discharge circuit, comprising a first voltage line, a second voltage line and a plurality of transistors. A first voltage signal provided by the first voltage line is greater than a second voltage signal provided by the second voltage line. The plurality of transistors are connected in series between the first voltage line and the second voltage line. At least one of the plurality of transistors is an oxide thin-film transistor, the oxide thin-film transistor comprises a top gate and a bottom gate, and the bottom gate is electrically connected to a third voltage line. The first voltage signal provided by the first voltage line is greater than a third voltage signal provided by the third voltage line.

A kind of pentacene field effect transistor of improving anti-fatigue characteristic, n-type semiconductor layer and charge trapping layer with shallow energy level trap are arranged in pentacene field effect transistor structure;Device has bottom gate type structure: gate electrode / gate insulating layer / n-type semiconductor film / charge trapping dielectric layer with shallow energy level trap / tunneling layer / pentacene / source (drain) electrode;Gate electrode is conductor, resistivity is between 0.1-0.001 Ω·cm;Gate insulating layer dielectric film is insulator, thickness range is 5-150nm;The thickness of n-type semiconductor film layer is 1-200nm;Charge trapping dielectric layer with shallow energy level hole trap, thickness is 1-100nm;Tunneling layer is insulator, thickness range is 1-20nm;Pentacene thickness range is 1-100nm;Source-drain electrode is conductor, thickness range is 50-200nm;Gate electrode is conductor.

The semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is on top of the first transistor. The second gate is electrically coupled to the second transistor. A dielectric isolation layer is between the first gate and the second gate. The first conductive contact is electrically coupled to the first gate. The second conductive contact is electrically coupled to the second gate. Control of the first gate through the first conductive contact is independent of control of the second gate through the second conductive contact.

A display device includes a substrate, a first transistor including a first bottom gate electrode disposed on the substrate, a first active layer disposed on the first bottom gate electrode and including a first channel region, a first drain region, and a first source region, and a first top gate electrode disposed on a portion of the first active layer including the first channel region, a first insulating layer disposed between the first bottom gate electrode and the first active layer, and a second insulating layer disposed between the first active layer and the first top gate electrode. The second insulating layer includes: a first portion disposed on a portion of the first active layer including the first channel region and having a first thickness and a second portion disposed on a remaining portion of the first active layer and having a second thickness smaller than the first thickness.

The invention discloses a neuromorphic transistor taking lithium niobate or lithium tantalate single crystal as a gate medium and a preparation method of the neuromorphic transistor, and belongs to the technical field of semiconductor devices. The neuromorphic transistor comprises a substrate layer, a bottom gate electrode layer, a gate dielectric layer and a patterned electrode assembly which are arranged from top to bottom. The material of the substrate layer comprises single crystal LiNbO3 (0001) or single crystal LiTaO3 (0001); the bottom gate electrode layer comprises a single crystal ZnSnO3 thin film; and the gate dielectric layer comprises a single crystal LiNbO3 film or a single crystal LiTaO3 film. A gate dielectric layer can be directly deposited after a single crystal ZnSnO3 thin film is epitaxially grown on the single crystal LiNbO3 (0001) or single crystal LiTaO3 (0001) substrate, the situation of lattice mismatch is effectively avoided, meanwhile, introduction of a buffer layer is reduced, thin film growing methods in a device structure are physical vapor deposition methods, safety is higher, and process cost is lower.

A GHeT includes a bottom gate formed on a substrate; a first dielectric layer (DL) formed on the bottom gate; a monolayer film formed of an atomically thin material on the first DL; a bottom contact (BC) formed on part of the monolayer film; a second DL formed on the BC; a top contact (TC) formed on the second DL on top of the BC; a network of CNTs formed on the TC and the monolayer film, to define an overlap region with the monolayer film; a third DL formed on the CNT network, the monolayer film and the TC; and a top gate formed on the third DL and overlapping with the overlap region. Such GHeT design allows gate tunability of Gaussian peak position, height and width that define Gaussian transfer characteristic, thereby enabling simplified circuit architectures for various spiking neuron functions for emerging neuromorphic applications.

A semiconductor device includes a merged gate having a top gate and a bottom gate disposed within a gate column with the top gate. A lateral contact plug is disposed between the top gate and the bottom gate to connect the top gate and the bottom gate, the lateral contact plug being confined within a width of the top gate.

To provide a large-sized semiconductor device that operates at high speed.SOLUTION: A top gate-type transistor having a monocrystal semiconductor layer and a bottom gate-type transistor having an amorphous silicon (or microcrystal silicon) semiconductor layer are formed on the same substrate. The gate wire that each of the transistors includes is formed in the same layer, and the source and drain electrodes likewise are formed in the same layer. In this way, the manufacturing steps are cut back. Thus, by only adding a few steps to the manufacturing process of bottom gate-type transistors, it is possible to manufacture two types of transistors.SELECTED DRAWING: Figure 6

The invention relates to the technical field of semiconductor manufacturing, and provides a carbon nanotube thin film field effect transistor, a preparation method thereof and a chip. The preparation method comprises the following steps: providing a layer of substrate; preparing a bottom gate electrode and a gate dielectric layer on the substrate in sequence; preparing a source electrode and a drain electrode on the gate dielectric layer; preparing aminated molecular layers on the surfaces of the source electrode, the drain electrode and the gate dielectric layer; removing the amination molecular layer outside the target area; preparing a carbon nanotube film in the target area; and carrying out annealing treatment. According to the preparation method, exposure treatment is carried out on an amination molecular layer outside a target area so as to damage the amination molecular layer of a non-target area, only the amination molecular layer of the target area is reserved, an adsorption site is provided for carbon nanotube film forming in a channel area, and in the preparation process, a carbon nanotube film does not make contact with photoresist, so that the carbon nanotube film is not damaged. Residue and pollution caused by photoresist protection in the traditional carbon nanotube patterning etching process are avoided, and the use performance of the carbon nanotube thin film field effect transistor is effectively guaranteed.

It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.

Semiconductor devices and methods of forming the same include a bottom transistor having a bottom gate. A top transistor has a top gate above the bottom gate and is separated from the bottom transistor by a dielectric layer. A conductive via extends through the top gate and the dielectric layer to contact the bottom transistor. A dielectric liner between the conductive via and the top gate electrically insulates the top gate from the conductive via.

To provide a semiconductor device with a configuration that can sufficiently reduce parasitic capacitance between wirings. This will be one of the issues to address. [Solution] A stack of a first layer in which part or all of a metal thin film is oxidized and an oxide semiconductor layer is formed. In the thin-film transistor with a bottom gate structure used, the oxide semiconductor overlaps with the gate electrode layer. An oxide insulating layer is formed on a part of the body layer to serve as a channel protective layer, and when the insulating layer is formed... An oxide insulating layer is formed to cover the peripheral edges (including the sides) of the stacked oxide semiconductor layers.

To provide a reliable semiconductor device with a transistor arranged by use of an oxide semiconductor.SOLUTION: A semiconductor device comprises a transistor of a bottom gate structure including an oxide semiconductor layer. In the semiconductor device, a first insulating layer is formed in contact with the oxide semiconductor layer and doped with oxygen into a first insulating layer including oxygen in excess of a stoichiometric composition. Forming a second insulating layer on the first insulating layer, the excessive oxygen contained in the first insulating layer can be supplied to an oxide semiconductor layer efficiently. Thus, a reliable semiconductor device having a stable electric property can be provided.SELECTED DRAWING: Figure 1

The application provides an array substrate and an electronic paper display device, and relates to the field of display. The array substrate comprises a substrate, a plurality of scan lines and a plurality of data lines are arranged on the substrate, the plurality of scan lines and the plurality of data lines cross and form a plurality of pixel units, and the pixel unit comprises a pixel electrode and a first thin film transistor. The pixel electrode is arranged opposite to the substrate. The first thin film transistor comprises a gate, a semiconductor layer, a source and a drain. The gate is connected with the scan line, the source is connected with the data line, the drain is electrically connected with the source, the gate comprises a top gate, a bottom gate and a connecting layer, the top gate and the bottom gate are arranged on opposite sides of the semiconductor layer in the thickness direction of the array substrate, and the top gate and the bottom gate are electrically connected through the connecting layer. The application can effectively improve the working stability of the electronic paper display device.

To provide an IGBT (Insulative Gate Bipolar Transistor) which can reduce turn-on power loss and perform screening of a gate insulator.SOLUTION: An insulative gate bipolar transistor comprises: a gate trench 7a which extends in a specified extension direction set in advance in a plane view; a first insulator film 8a which is arranged at a bottom face of the gate trench 7a and at least a part of lateral face; a bottom gate conductive component 9a which is embedded in the gate trench 7a through the first insulator film 8a; a first split insulator film 10a which is arranged on the bottom gate conductive component 9a; an upper gate conductive component 11a which is embedded in the gate trench 7a through the first split insulator film 10a; a gate surface electrode 16 which is overlapped with one end of the gate trench 7a in the extension direction; a first contact hole 13c which electrically connects the gate surface electrode 16 with the bottom gate conductive component 9a; and a second contact hole 13a which electrically connects the gate surface electrode 16 with the upper gate conductive component 11a.SELECTED DRAWING: Figure 1

The invention discloses an infrared bipolar linearly-polarized photoelectric detector and a preparation method thereof, and the infrared bipolar linearly-polarized photoelectric detector is characterized in that a bipolar material graphene is used as a channel material, a two-dimensional N-type semiconductor material molybdenum disulfide MoS2 and an anisotropic narrow-band-gap two-dimensional material black phosphorus BP are stacked on the bipolar material graphene in sequence, and the two-dimensional N-type semiconductor material molybdenum disulfide MoS2 and the anisotropic narrow-band-gap two-dimensional material black phosphorus BP are stacked on the channel material; the polarity of the graphene is regulated and controlled by the bottom gate, the infrared bipolar linearly polarized photoelectric detector with the bipolar linear polarization detection effect that the light current symbol reversibly turns over along with the polarization direction in the infrared band is achieved, and the infrared bipolar linearly polarized photoelectric detector has the advantages of being simple in structure, easy to regulate and control, capable of remarkably improving polarization recognition precision and the signal-to-noise ratio and the like. The programmable and multifunctional integration potential is also realized.

A display substrate and a display device, the display substrate comprising a substrate and a plurality of sub-pixels (Pxij) arranged on one side of the substrate, at least one sub-pixel (Pxij) comprising a pixel driving circuit (pdc), at least one pixel driving circuit (pdc) comprising a plurality of transistors, the transistors comprising an active layer and at least one gate electrode; in the same transistor, the at least one gate electrode at least partially overlaps the active layer, and the at least one gate electrode comprises at least one of a top gate and a bottom gate; in a direction perpendicular to the plane in which the substrate lies, the bottom gate is located on the side of the active layer close to the substrate, and the top gate is located on the side of the active layer away from the substrate; the plurality of transistors at least comprises a driving transistor (T3), and the gate electrode in the driving transistor (T3) comprises a top gate (T3gt) and a bottom gate (T3gb).

The invention relates to the technical field of vacuum microelectronic devices, in particular to a nano cold cathode electron source array and a preparation method thereof, and the nano cold cathode electron source array comprises a substrate; the bottom cathode electrode strips are arranged in parallel; the bottom gate electrode strips are arranged in parallel; the insulating layer covers and separates the bottom cathode electrode strip and the bottom gate electrode strip, and the insulating layer is located at the top of the substrate; a top cathode electrode and a top gate electrode which are manufactured at the top of the insulating layer are respectively connected with the bottom cathode electrode strip and the bottom gate electrode strip through the first etching through hole and the second etching through hole; and the composite cold cathode comprises a nano cold cathode manufactured at the top of the top cathode electrode and a surface film coating the nano cold cathode. According to the invention, the conductivity, thermal conductivity, work function and other characteristics of the composite cold cathode can be regulated and controlled through the surface film, the field emission characteristic of the nano cold cathode in a cold cathode electron source is improved, large-area preparation can be realized, and the application of the cold cathode electron source in a large-area flat X-ray source device is expanded.

An ion sensing device includes a first field-effect transistor, a second field-effect transistor, a reference electrode configured to directly contact a sample solution, a first ion-sensitive film, and a second ion-sensitive film. Each of the first field-effect transistor and the second field-effect transistor includes a semiconductor film, a bottom gate electrode, a bottom gate insulating film located between the bottom gate electrode and the semiconductor film, and a top gate insulating film. Surface materials in contact with the sample solution for the first ion-sensitive film and the second ion-sensitive films are the same. A sensitivity of the combination of the first field-effect transistor and the first ion-sensitive film is higher than a sensitivity of the combination of the second field-effect transistor and the second ion-sensitive film.

A pixel of an electronic device includes a light emitting element connected between a first voltage line and a first node, a first transistor including a first electrode connected to a second node, a second electrode connected to a third node, a gate electrode connected to a fourth node, and a bottom gate electrode, a second transistor connected between a first voltage line and the first node, a third transistor connected between the first node and the second node, a fourth transistor connected between the second node and the fourth node, a fifth transistor connected between a first data line and a fifth node, a sixth transistor connected between a second data line, a seventh transistor connected between the third node and a second voltage line, an eighth transistor connected between the fifth node and the second voltage line, a first capacitor and a second capacitor.

Memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers. Memory cells in the memory-cell tiers individually comprise a horizontal transistor, a capacitor that is on a capacitor side of the horizontal transistor, and part of a digitline that is on a digitline side of the horizontal transistor. Insulator material extends from horizontally aside the capacitor side of a top gate in a lower memory-cell tier through the insulative tier that is between an upper and a lower memory-cell tiers to horizontally aside the capacitor side of a bottom gate in the upper memory-cell tier. The insulator material in the upper memory-cell tier and in the lower memory-cell tier has a laterally-outer linearly-straight surface in a vertical cross-section that is through and horizontally-elongated along an axis. The laterally-outer linearly-straight surface being one of vertical, angled from vertical away from the capacitor side by no more than 40°, or angled from vertical toward the capacitor side by no more than 30°. Methods are disclosed.

The display substrate and the display device are provided. The display substrate comprises a substrate and a plurality of sub-pixels arranged on one side of the substrate. The sub-pixel comprises a pixel driving circuit, and the pixel driving circuit comprises a plurality of transistors. The transistor comprises an active layer and at least one gate electrode. In the same transistor, the at least one gate electrode at least partially overlaps with the active layer, and the at least one gate electrode comprises at least one of a top gate and a bottom gate. The bottom gate is located on the side of the active layer close to the substrate, and the top gate is located on the side of the active layer away from the substrate. In the same pixel driving circuit, the plurality of transistors comprise at least one first type transistor and at least one second type transistor. The first type transistor comprises at least one of a top gate and a bottom gate, and the second type transistor comprises a top gate and a bottom gate. The technical scheme provided by the display substrate and the display device can reduce the difficulty of narrowing the frame of the display substrate.

The invention relates to a field effect transistor sensor based on electric field enrichment and a detection method thereof. The field effect transistor sensor sequentially comprises a substrate, a dielectric layer and a channel induction region, wherein the channel induction region is composed of a drain electrode, a source electrode and a channel region; the bottom grid electrode is located above the channel induction region and is isolated from the channel region through the dielectric layer, so that an attraction electric field is generated in the detection process, and a target object is attracted to the channel induction region; the top grid is arranged above the liquid level of the detection liquid so as to form a repulsive electric field in the detection process, and a target object is repelled away from the surface of the detection liquid, so that electric field enrichment is realized in cooperation with the bottom grid. Through the synergistic effect of the top gate and the bottom gate, the local concentration and capture efficiency of a target object in a channel sensing region can be remarkably improved, the problems of slow response, insufficient sensitivity and the like caused by the fact that a traditional field effect transistor depends on passive diffusion are effectively solved, and rapid and high-sensitivity detection of the trace target object is achieved.

The invention provides a display panel and a display device. The display panel gate drive circuit comprises a signal generation module and an output module which are electrically connected, the signal generation module comprises at least one first-type signal transistor, the output module comprises at least one output transistor, and the first-type signal transistor and the output transistor are both P-type transistors. A shading layer of the display panel comprises a first signal bottom grid electrode of a first type signal transistor and an output bottom grid electrode of an output transistor. According to the invention, the proportion of the number of the output transistors with the output bottom gates in the output module is greater than or equal to the proportion of the number of the first-type signal transistors with the first signal bottom gates in the signal generation module, so that the proportion of double gates of the P-type transistors in the signal generation module is reduced; equivalently, the area of the bottom grid electrode in the grid electrode driving circuit is reduced, so that the water vapor invasion area in the light shielding layer is reduced, and the technical problem that the light shielding metal layer of the display panel is corroded is solved.