68results about How to "Minimize Leakage Current" patented technology

A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.

Hole transport layer compositions comprising a silylated aryl amine and a polymeric component, to enhance performance of an associated electroluminescent device.

A programmable SoC (system on a chip) having optimized power domains and power islands. The SoC is an integrated circuit device including a plurality of power domains, each of the power domains having a respective voltage rail to supply power to the power domain. A plurality of power islands are included within the integrated circuit device, wherein each power domain includes at least one power island. A plurality of functional blocks are included within the integrated circuit device, wherein each power island includes at least one functional block. Each functional block is configured to provide a specific device functionality. The integrated circuit device adjusts power consumption in relation to a requested device functionality by individually turning on or turning off power to a selected one or more power domains, and for each turned on power domain, individually power gating one or more power islands.

Disclosed are embodiments of an improved multi-gated field effect transistor (MUGFET) structure and method of forming the MUGFET structure so that it exhibits a more tailored drive current. Specifically, the MUGFET incorporates multiple semiconductor fins in order to increase effective channel width of the device and, thereby, to increase the drive current of the device. Additionally, the MUGFET incorporates a gate structure having different sections with different physical dimensions relative to the semiconductor fins in order to more finely tune device drive current (i.e., to achieve a specific drive current). Optionally, the MUGFET also incorporates semiconductor fins with differing widths in order to minimize leakage current caused by increases in drive current.

A balanced charging/discharging circuit for a lithium battery set, including a plurality of serially connected lithium batteries each having a positive electrode controlled by a corresponding control signal to selectively establish connection with a positive electrode of a battery charging circuit, and a negative electrode controlled by a corresponding control signal to selectively establish connection with a negative electrode of the battery charging circuit. Voltage of the positive and negative electrodes of each of the serially connected lithium batteries is transmitted to a corresponding terminal of a control circuit respectively so that the control circuit generates a corresponding transfer signal to the battery charging circuit and supplies the control signal to establish connection of a corresponding series of lithium batteries for charging. Battery sets arranged in series or in parallel can be charged with the maximum current and the service life is extended and charging time is shortened.

One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.

Disclosed are embodiments of an improved multi-gated field effect transistor (MUGFET) structure and method of forming the MUGFET structure so that it exhibits a more tailored drive current. Specifically, the MUGFET incorporates multiple semiconductor fins in order to increase effective channel width of the device and, thereby, to increase the drive current of the device. Additionally, the MUGFET incorporates a gate structure having different sections with different physical dimensions relative to the semiconductor fins in order to more finely tune device drive current (i.e., to achieve a specific drive current). Optionally, the MUGFET also incorporates semiconductor fins with differing widths in order to minimize leakage current caused by increases in drive current.

The semiconductor integrated circuit device includes a voltage control circuit that generates a control voltage for deactivating a field effect transistor by a gate voltage. The voltage control circuit controls a voltage so as to substantially minimize the leakage current which flows when the field effect transistor is inactive with respect to a device temperature.

A NAND flash memory device, and methods of forming and operating the same are provided. The NAND flash memory device includes first and second selection gate lines sequentially disposed at one side of a plurality of cell gate lines. A first selection transistor including the first selection gate line serves as a buffer for decreasing a highly boosted channel voltage of a non-selected cell to minimize the leakage current of the NAND flash memory device.

An analog buffer includes a comparator unit for comparing an input signal to be charged on a signal line of a display panel with an output signal charged on the signal line of the display panel to output a control signal; and a current switching unit for discharging an output current from the signal line of the display panel or charging an input current on the signal line of the display panel in accordance with the control signal output by the comparator unit the comparator unit smallest and to thus minimize leakage current.

A semiconductor device including a capacitor which includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode, the dielectric layer including: a first paraelectric film formed of a material containing a first metal element and at least one kind of second metal element; a second paraelectric film disposed between the first electrode and the first paraelectric film; and a third paraelectric film disposed between the second electrode and the first paraelectric film, wherein the second paraelectric film is formed of a material containing the first metal element but substantially not containing the second metal element, and the third paraelectric film is formed of a material containing the first metal element but substantially not containing the second metal element.

The invention relates to a preparation method for a black-silicon poly-silicon PERC cell structure with a selective emitter. The preparation method is characterized by comprising the following steps of (1) forming a nanometer texturing surface on a front surface of a silicon wafer, wherein a back surface is a polishing surface; (2) performing front-surface diffusion of the silicon wafer to form anN-type layer, and removing front-surface phosphorosilicate glass and a back-surface pn junction; (3) depositing a silicon nitride anti-reflection film layer on the front surface of the silicon wafer,and depositing a passivation dielectric layer on the back surface; (4) dotting or routing the back surface of the silicon wafer, and printing a silver electrode and aluminum paste; (5) performing low-temperature sintering to form a local aluminum back field; (6) spraying a mixed solution of phosphoric acid and alcohol on the front surface of the silicon wafer, and forming a main grid line regionand a secondary grid line region after heavy doping by laser; and (7) immersing the front surface of the silicon wafer in an electroplating solution, electroplating the front surface of the silicon wafer under an illumination condition, and annealing after electroplating. By the preparation method, the defects that a high-quality fine grid line is difficult to form by silk-screen printing and thegrid line and a selective emitter cannot be enabled to be accurately aligned are overcome, and shielding and leakage current caused by an electrode are minimum.

A stator which may be employed in an electric rotating machine. The stator includes a stator winding which includes in-slot portions disposed in slots of a stator core. The in-slot portions are arrayed in each of the slots in a form of multiple layers aligned in a radial direction of the stator core. The stator winding is made up of a first winding and a second winding which are connected together through a joint. The first winding is defined by a portion of the stator winding between the joint and an end of the stator winding which is to be connected to an external. The second winding includes the in-slot portion placed within at least one of the slots as an outermost layer that is one of the layers placed most outwardly in the radial direction of the stator core. This results in a great decrease in leakage current.

An analog storage cell circuit includes a switch that minimizes subthreshold conduction and diode leakage, as well as an accumulation-mode coupling mechanism to minimize overall switch leakage to minimize accumulation-mode leakage. In one embodiment, an analog storage circuit includes a sample and hold circuit including an amplifier having first and second inputs and a switch coupled to the first input of the amplifier. The switch includes a first switching device forming a core of the switch, a second switching device coupled to the first switching device to disconnect the first switching device from a first terminal during the hold phase, and a third switching device coupled to the first switching device to connect the first switching device to a second terminal during the hold phase to minimize accumulation mode conduction in the first switching device.

Systems and methods in accordance with embodiments of the invention are disclosed that include MOSFET transistor operation by adjusting V_bs, or the voltage applied to the body terminal of the MOSFET transistor, to control the threshold voltage (V_th) in order to minimize leakage current and increase response time. One embodiment includes a n-channel metal-oxide-semiconductor field-effect transistor (NMOS), including: a gate terminal; a source terminal; a drain terminal; a body terminal; and control circuitry, where the control circuitry is configured to bias the body terminal at a first voltage when voltage applied to the gate terminal turns the transistor OFF and a second voltage when voltage applied to the gate terminal turns the transistor ON; and where the first voltage is of a lower value than the second voltage.

A method for fabricating a CMOS image sensor is disclosed, to minimize the leakage current and to improve the yield, which includes the steps of preparing a semiconductor substrate including a peripheral circuit and a pixel array, wherein the pixel array is comprised of a photodiode and a readout circuit; defining an active area and a field area in the semiconductor substrate; forming a field oxide layer in the field area of the semiconductor substrate; forming gate electrodes in the peripheral circuit and the readout circuit of the pixel array; forming a photodiode in a photodiode portion of the pixel array; forming source and drain junctions at both sides of the gate electrode in the semiconductor substrate of the active area; forming a salicide prevention layer in the semiconductor substrate of the pixel array; and forming salicide layers in the surface of the gate electrode and the source and drain junctions in the peripheral circuit by using the salicide prevention layer as a mask.