49 results about "Subthreshold conduction" patented technology

After an element isolation region is formed using a field-forming silicon nitride film, the silicon nitride film and a semiconductor substrate are patterned. Thereafter, the silicon nitride film and the semiconductor substrate are patterned, thereby forming a gate trench reaching the semiconductor substrate in an active region. Next, after a gate electrode is formed within a gate trench, the silicon nitride film is removed, thereby forming a contact hole. A contact plug is buried into this contact hole. Accordingly, a diffusion layer contact pattern becomes unnecessary, and the active region can be reduced. Because a gate electrode is buried in the gate trench, a gate length is increased, and a sub-threshold current can be reduced.

A memory system is provided that includes an array of memory cells that require periodic refresh, and a temperature-adaptive refresh controller. Data retention time of the memory cells decreases exponentially as temperature increases. The temperature-adaptive refresh controller selects the refresh period of the memory cells in response to the subthreshold current of a reference transistor. The subthreshold current of the reference transistor increases exponentially as temperature increases As a result, the refresh period is empirically tied to the data retention time. Consequently, the power required for refresh operations decreases as temperature decreases. Power is therefore conserved in applications that operate predominantly at room temperature.

A T-RAM memory cell includes a temperature compensation device to adjust the gate-to-source voltage of an access transistor for the memory cell as a function of temperature so that the sub-threshold current of the transistor is insensitive to temperature variations. As a result, the sub-threshold current can be maintained slightly above the holding current of a thyristor used in the memory cell despite substantial temperature variations. In one embodiment, the temperature compensation device includes a current source directing a fixed current through a diode-connected transistor of the type used as the memory cell access transistor. Temperature induced changes in a reference voltage generated at the junction between the current source and the transistor therefore match the temperature induced changed in the sub-threshold current of the access transistor. As a result, the sub-threshold current of the access transistor can be made insensitive to temperature variations by applying the reference voltage to the gate or source of the access transistor.

The present invention relates to an on-chip system for testing clock signal flutter and its method, in particular, it relates to test of phase-locked loop flutter. The high time analyticity, low amplitude and differential signal are not influenced by element changeability. It includes subthreshold current control one-sided delay line with N time-delay units, reference delay line and test clock delay line. Besides, it also includes a arbiter and a calibrator. Said invention also provides the concrete steps of its test method.

An invention is provided for reducing subthreshold current in memory core cells. A memory array having a plurality of memory core cells is provided. Each memory core cell in the memory array is selectable using a word line. A selected word line addressing a particular memory core cell is charged to a positive voltage. In addition, unselected wordlines of the memory array are charged to a negative voltage. In this manner, subthreshold current associated with unselected memory core cells is reduced.

Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is therefore not available at the isolation-to-active interface, but rather the channel length along that interface is substantially lengthened, reducing off-state conduction.

The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.

A manner of mitigating the self heating effect of a laser or other light source such as a laser in a network node of a communication network. A self-heating mitigation module is provided, the self-heating mitigation module includes one or both of a self-heating adjustment module to accelerate self heating at the beginning of a transmission and a sub-threshold lasing module that applies a sub-threshold current between transmissions. The self-heating adjustment module and the sub-threshold lasing module are preferable both used together and driven by a common signal, for example the burst_enable signal that facilitates transmission from the light source.

Disclosed is a current mode bandgap reference voltage source with a subthreshold current compensation function. On the basis of an existing bandgap reference core circuit, a first MOS (metal oxide semiconductor) transistor subthreshold current compensation circuit and a second MOS transistor subthreshold current compensation circuit are added, subthreshold current of an NMOS transistor and a PMOS transistor are compensated to reference current through the two subthreshold current compensation circuits, the index change relation of the subthreshold current is utilized to compensate nonlinearity of traditional reference current, output bandgap reference current is enabled to be compensated within a wide temperature range, output bandgap reference voltage and temperature variations slow down, and accordingly temperature coefficient of the reference voltage is lowered greatly.

A CMOS voltage reference circuit for a low voltage (1v), low power supply application is described. The circuit achieves a temperature coefficient of 31 ppm for a relatively large temperature range of −40 C to 125 C. A combination of subthreshold current characteristics and moderate inversion operation of MOSFET's are utilized in conjunction to achieve a fairly stable temperature independent output voltage reference (V_REF) from the circuit.

The required refresh rate of a DRAM is reduced by biasing active digit lines to a slight positive voltage to reduce the sub threshold current leakage of access transistors in memory cells that are not being accessed. The slight positive voltage is provided by a voltage regulator circuit using one or more bipolar transistors fabricated in a well that electrically isolates the bipolar transistors from the remainder of the substrate. The voltage provided by the voltage regulator is preferably coupled to the access transistors by powering each of the n-sense amplifiers in the DRAM with the voltage from the voltage regulator.

A semiconductor device that operates at high speed using a low voltage power source, in which the output of each gate in the standby state is stable, and which has a delay time that is not affected by the frequency of the input signal.TrQ1 to TrQ8, which form multiple stages of the inverters are designed to have a low threshold voltage in order to accomplish low voltage operation. When input node A is at "L" in the standby state, TrQ2, Q3, Q6, and Q8 which cut-off are connected to high threshold voltage TrQn1 and Qp1. In the standby state, power cutting TrQn1 and Qp1 cut off in accordance with chip selecting signals CS, /CS, thereby blocking the flow of sub-threshold current to TrQ1~Q8. Since TrQ1, Q4, Q5 and Q8 are not cut off at this time, the output potential of each inverter is stable. The number of transistors assigned to each power cutting transistor is determined based on the frequency of the input signal, so that only one transistor from among the transistors connected to TrQn1 and Qp1 will be ON at any given time.

A power-to-ground clamp transistor provides electrostatic discharge (ESD) protection. A filter capacitor and resistor generate a filter voltage that is buffered by three stages to drive the gate of the clamp transistor. The filter capacitor is about twenty times smaller than in a conventional clamp circuit. Feedback in the circuit keeps the clamp transistor turned on after the R-C time constant of the capacitor and resistor in the filer has elapsed, allowing for a smaller capacitor to turn on the clamp transistor longer. A sub-threshold-conducting transistor in the first stage conducts only a small sub-threshold current, which extends the discharge time of the first stage. The gate of the sub-threshold-conducting transistor is driven by feedback from the second stage. A feed-forward resistor has a high resistance value to slowly raise the voltage of the second stage from the filter voltage, and thus slowly raise the gate of the sub-threshold-conducting transistor.

A system and device for solving sparse algorithms using hardware solutions is described. The hardware solution can comprise one or more analog devices for providing fast, energy efficient solutions to small, medium, and large sparse approximation problems. The system can comprise sub-threshold current mode circuits on a Field Programmable Analog Array (FPAA) or on a custom analog chip. The system can comprise a plurality of floating gates for solving linear portions of a sparse signal. The system can also comprise one or more analog devices for solving non-linear portions of sparse signal.

An analog storage cell circuit includes a switch that minimizes subthreshold conduction and diode leakage, as well as an accumulation-mode coupling mechanism to minimize overall switch leakage to minimize accumulation-mode leakage. In one embodiment, an analog storage circuit includes a sample and hold circuit including an amplifier having first and second inputs and a switch coupled to the first input of the amplifier. The switch includes a first switching device forming a core of the switch, a second switching device coupled to the first switching device to disconnect the first switching device from a first terminal during the hold phase, and a third switching device coupled to the first switching device to connect the first switching device to a second terminal during the hold phase to minimize accumulation mode conduction in the first switching device.

Quiescent current drawn by an array of four-transistor loadless static random access memory (SRAM) cells is minimized by using a negative feedback loop to set a reference voltage, for the wordline driver, to a level which reduces the subthreshold current through the pass transistors to a level which is just barely sufficient to reliably retain data.

An amplification-type solid-state image pickup device of the present invention repeats, in every frame, a signal level readout period, a first reset period, a reset level readout period, a second reset period, and a third reset period in this order. In the first reset period and the third reset period, a MOS transistor for reset is set to execute a soft reset operation with a sub-threshold current, while in the second reset period, the MOS transistor for reset is set to execute a hard reset operation so as to fix the potential of a photon-electron conversion region to a drain potential. This makes it possible to reduce both reset noise and image retention with a simple constitution.

The invention relates to a bandgap reference voltage circuit with ultra-low power consumption under full-CMOS subthreshold work. The circuit comprises a starting circuit, a subthreshold current generation circuit, a voltage division CTAT circuit, a cascading PTAT circuit and a PTAT voltage adjustment tube. Through the starting circuit, all the circuits get rid of the null point and work at a normal work point; the subthreshold current generation circuit is used for generating subthreshold current of an MOS tube, and accordingly all the circuits work in a subthreshold state; the voltage division CTAT circuit is used for lowering the negative temperature coefficient of the circuit; the cascading PTAT circuit is used for generating PTAT voltage; the PTAT voltage can be adjusted through multi-grade segmentation, and the PTAT voltage adjustment tube 5 is used for adjusting current in the cascading PTAT circuit 4. Through the design of the full-CMOS subthreshold work, the whole working current is greatly lowered, finally the output voltage can be lower than 1 V, the temperature coefficient of the output voltage can be precisely adjusted, and accordingly the output voltage has high temperature precision.

An oscillator operates at a very low voltage yet has a duty cycle that is set by a ratio of capacitors that are charged and discharged. Sub-threshold p-channel transistors conduct sub-threshold currents below the normal threshold voltage, and drive set and reset inputs of a set-reset S-R latch. The S-R latch drives the oscillator outputs. The oscillator outputs feed back to charging p-channel transistors that charge one plate of the capacitors. During half of the cycle, the charging p-channel transistor is off, allowing one plate of the capacitors to discharge through an n-channel discharge transistor. After a period of discharge determined by the capacitance of the capacitor, the gate of a sub-threshold p-channel transistor falls enough for sub-threshold current to flow, triggering the set or reset input of the S-R latch. Since sub-threshold currents are needed to toggle the S-R latch, the oscillator begins to oscillate below the threshold voltage.