293results about "Pulse generation by bipolar transistors" patented technology

An oscillator circuit generates an output frequency that is substantially independent of power supply and temperature variations. The oscillator circuit can be implemented using conventional complementary metal-oxide-semiconductor technology. The oscillator circuit is suitable for use as an internal oscillator for generating a stable reference frequency in telecommunication receiver modules.

A microcontroller having a dual mode relax oscillator that is trimmable. In one embodiment, the present invention provides a relaxation oscillator circuit comprising two current sources for establishing a reference voltage for use in causing the relaxation oscillator circuit to operate in two power modes, and a control coupled to both current sources for switching between power modes. In one embodiment, one power mode is a low power mode for standard operation of the microcontroller and one power mode is a very low power mode for use in a sleep mode. In one embodiment, the relaxation oscillator circuit further comprises digitally trimmable components operable to control a current charging a capacitor of the relaxation oscillator circuit to account for process variation in the capacitor, wherein the current is for controlling a frequency of the microcontroller.

An electronic assembly includes one or more discrete capacitors (506, 804, 1204), which are vertically connected to a housing, such as an integrated circuit package (1704). Surface mounted capacitors (506) are vertically connected to pads (602) on a top or bottom surface of the package. Embedded capacitors (804, 1204) are vertically connected to vias (808, 816, 1210, and / or 1212) or other conductive structures within the package. Vertically connecting a surface mounted or embedded capacitor involves aligning (1604) side segments (416) of some of the capacitor's terminals with the conductive structures (e.g., pads, vias or other structures) so that the side of the capacitor upon which the side segments reside is substantially parallel with the top or bottom surface of the package. Where a capacitor includes extended terminals (1208), the capacitor can be embedded so that the extended terminals provide additional current shunts through the package.

A method and apparatus for frequency modulating a PWM involves 1) generating a high frequency carrier signal much greater in frequency than the PWM signal; 2) modulating the high frequency signal to generate a spread spectrum carrier signal; and, 3) retiming a PWM signal with this high frequency SS carrier signal so that the binary transitions of the PWM signal are aligned with the frequency varying carrier signal. In another embodiment, a PWM oscillator is driven by a second, FM oscillator having spread spectrum characteristics. In another embodiment a PWM oscillator is driven and modulated by a counter / frequency divider comprised of modules.

A free running clock circuit includes a switching circuit for switching between first and second logic states at a predetermined frequency based upon a trip voltage the switching circuit has a programmable temperature profile associated therewith. The switching circuit includes a comparator circuit that has first and second comparators. The first and second comparators have a reference input connected to receive the trip voltage, and the output of the comparators change logic states between a first logic state and a second logic state when the other input of the comparator passes the trip voltage. The first and second comparators have a programmable offset voltage enabling programming of the programmable voltage supply profile of the switching circuit. An RC timing circuit defines when the outputs of the comparators switch between the first and second logic states by providing a feedback to the other inputs of the two comparators. A temperature compensated trip voltage generator outputs a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit.

In a switching power supply device with reduced size and increased power conversion efficiency, a first resonant circuit including a series resonant inductor and a series resonant capacitor, and a second resonant circuit including a series resonant inductor and a series resonant capacitor, are caused to resonate with each other to cause sympathetic vibration of each resonant circuit, such that transmission is performed by utilizing both magnetic field coupling and electric field coupling between a primary winding and a secondary winding. Operation at a switching frequency higher than a specific resonant frequency of an overall multi-resonant circuit allows a ZVS operation to be performed, enabling a significant reduction in switching loss and high-efficiency operation.

A free running clock circuit includes a switching circuit for switching between first and second logic states at a predetermined frequency based upon a trip voltage the switching circuit has a programmable temperature profile associated therewith. The switching circuit includes a comparator circuit that has first and second comparators. The first and second comparators have a reference input connected to receive the trip voltage, and the output of the comparators change logic states between a first logic state and a second logic state when the other input of the comparator passes the trip voltage. The first and second comparators have a programmable offset voltage enabling programming of the programmable voltage supply profile of the switching circuit. An RC timing circuit defines when the outputs of the comparators switch between the first and second logic states by providing a feedback to the other inputs of the two comparators. A temperature compensated trip voltage generator outputs a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit.

A switched-current oscillator having a dc current source adapted to charge a capacitor so that the capacitor charging time is controlled based on a sequence of (pseudo)randomly selected values, each of those values defining a corresponding charging time. A discharge device is adapted to discharge the capacitor if the voltage across the capacitor reaches a threshold voltage, at which point the next value in the sequence is selected to determine the next charging time. A square-wave clock signal having spread-spectrum characteristics is generated in the oscillator by using the series of charge-discharge cycles corresponding to the sequence of randomly selected values to toggle a flip-flop operating as a delay line and zero-order hold.

An oscillator circuit (300) disclosed herein includes an improved capacitor discharge circuit. The oscillator includes at least one capacitor coupled to a charging circuit portion (202, 210) and a discharging circuit portion (208) through a switching network (204, 216, 218, 220 and 222). In the alternative, an oscillator including more than one capacitor includes respective charging and discharging circuit portions connected to respective switching networks. Each charging circuit portion (202, 210) provides sufficient charge to charge the coupled capacitor (206) to a high threshold voltage (V.sub.tH). Each discharging circuit portion (208) discharges each coupled capacitor (206) to a low threshold voltage (V.sub.tL). The switching network alternately connects each coupled capacitor (206) to the charging circuit portion (202, 210) and the discharging circuit portion (208) to thereby alternately charge and discharge for each coupled capacitor (206) alternately. A set / reset flip-flop (214) connected to the switching network (204, 216, 218, 220 and 222) enables and disenables the charging cycle and the discharge cycle of the oscillator 200.

An oscillator circuit comprising a resonant circuit which includes a negative resistor, an inductor and an oscillation frequency setting capacitor whose capacitance is varied according to a control voltage based on oscillation frequency data and which outputs a signal having an oscillation frequency based on the oscillation frequency data, a temperature detector which outputs temperature compensation data, based on the temperature, and temperature compensating capacitors which are electrically connected to the resonant circuit and which are supplied with the temperature compensation data to change capacitance values thereof based on the temperature compensation data, thereby adjusting the oscillation frequency.

The low-power relaxation oscillator comprises a first module (21) having a ramp generator formed by a reference current source (31) and a storage capacitor (32) defining a ramp voltage (Vramp1), and a voltage comparator (m1, m2) for comparing the ramp voltage with a reference voltage, a second module (22, 41, 42, Vramp2, m3, m4) similar to the first module and an asynchronous flip-flop (23) receiving the output signal of the comparator of the first module at a first input (s) and the output signal of the comparator of the second module at a second input (r). For each module a generator of said reference voltage is configured by adding a reference resistance (33, 43) between the reference current source and the storage capacitor. Thus, the generation of the reference voltage and the ramp voltage is conducted on the very same current branch. This enables the electrical power consumption of the oscillator to be reduced.

An output signal ZA of NAND 48a is given to a first input of NAND 48b and is given to a second input of the above NAND 48b, simultaneously through a delay circuit. Furthermore, an output signal ZB of the NAND 48b is given to the first input of NAND 48a and is given to the second input of NAND 48a, simultaneously through a delay circuit. The delay circuit includes a charging and discharging circuit consisting of a NMOS 42 having the conductivity controlled by a voltage VN depending on a temperature signal from a temperature-dependent current source 30 and a capacitor 44, and a NMOS 45 being turned on / off by the voltage of the above capacitor 44. By setting temperature characteristics of the voltage VN and temperature characteristics of the threshold voltage of the NMOS 45 so as to cancel each other, the oscillation frequency variation of the oscillation circuit consisting of astable multi-vibrators can be restrained.

Method and apparatus for adding jitter to an oscillator for reducing EMI are disclosed An oscillator circuit includes an oscillator configured to generate a first clock having a first frequency and a frequency jitter circuit including a charge pump configured to charge and discharge first and second capacitors repeatedly for obtaining a time-varying voltage having a second frequency. The time-varying voltage is coupled to the oscillator to vary the first frequency within a frequency range. The charge pump includes a first switch for coupling the first capacitor to a voltage source and a second switch for coupling the first capacitor to the second capacitor. A charge transfer between the first and second capacitors is configured to provide the time-varying voltage.

An oscillator circuit having a closed loop connection, including: an oscillator for generating an output signal oscillating at a frequency corresponding to a control signal; a frequency / voltage converter for generating a detection signal having a voltage corresponding to a frequency of the output signal; a difference detector for generating a difference signal indicating a difference between the detection signal and a reference signal; and an integrator for generating the control signal by integrating the difference signal.

The integrated system on a chip with LINBUS network communication capabilities includes processing circuitry for performing predefined digital processing functionalities on the chip. A free running clock circuit generates a temperature compensated clock that does not require a synch signal from external to the chip. A LINBUS network communications interface digitally communicates with off-chip LINBUS devices. Communication between said on-chip LINBUS communications interface and the off-chip LINBUS devices is affected without clock recovery. The LINBUS network communication interface has a time base derived from the temperature compensated clock which is independent of any timing information in the input data received during a receive operation. The temperature compensated clock further provides an on-chip time reference for both the processing circuitry and the LINBUS network communications interface.

A dual range oscillator provides two different ranges of oscillator frequency output based on switched current sources charging a capacitor. As several current sources are combined to charge capacitor, the interval for charging the capacitor decreases and changes the oscillator frequency output accordingly. A reference voltage supplied to a comparator checks the voltage on the capacitor to determine when to combine current sources to charge the capacitor and modify the timing interval and the corresponding oscillator frequency output. The different current sources are switched to the capacitor to provide modified charging slopes. The dual slope, dual range oscillator permits frequency switching operation in a variety of environments and applications with a simplified control and integration into a single chip.

The present invention provides a voltage controlled oscillator for changing an oscillating frequency in accordance an input control voltage, including a parallel resonant circuit, a negative resistance circuit connected in parallel to the parallel resonant circuit, a first capacitor connected in parallel to the negative resistance circuit, a first current source connected between one terminal of the first capacitor and the negative resistance circuit, and a second current source connected between the other terminal of the first capacitor and the negative resistance circuit. The capacitance value of the first capacitor is set to a value that suppresses a signal with a frequency twice the oscillating frequency at both the terminals of the first capacitor. Each of the first and the second current sources is constituted by a bipolar transistor.

A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC.

A clock oscillator system for use in providing the switching regulator duty cycle control in a fixed frequency (no cycle skipping) operation is provided. In one embodiment, the circuit according to the invention uses an analog feedback loop to extend the switch ON time of the clock cycle by controlling the oscillator charging current and, thereby, increase the duty cycle. Preferably, this circuit can achieve very high switching duty cycle and / or very low switching duty cycle in a PWM switching regulator operated in very low drop-out operation when very high duty cycle is required or in other conditions when very low duty cycle is required.

A quadrature output high-frequency RF divide-by-two circuit includes a pair of differential complementary logic latches. The latches are interconnected to form a toggle flip-flop. Each latch includes a tracking cell and a locking cell. In a first embodiment, the locking cell includes two complementary logic inverters and two transmission gates. When the locking cell is locked, the two gates are enabled such that the locked (i.e., latched) signal passes through both transmission gates and both inverters. In one advantageous aspect, the tracking cell only involves two transmission gates. Due to the circuit topology, the first embodiment is operable from a low supply voltage at a high operating frequency while consuming a low amount of supply current. In a second and third embodiment, the tracking cell involves a pair of inverters. The sources of the transistors of the inverters are, however, coupled together thereby resulting in performance advantages over conventional circuits.

The present invention provides a pulse width modulation (PWM) circuit comprising an PWM control circuit for setting an output signal to low when a logical level of a oscillation signal at a first input terminal changes from low to high, for resetting the output level to low in response to an effective input signal at a second terminal, a charge and discharge means for charging a first node (node1) when the output stays in low, for discharging the stored charge of node1 when the output stays in high, a comparator (C1) for outputting an output signal to the second terminal according to the first node signal and a first reference signal (Vref0), a discharge current controlling means for the stored charge on the first node, wherein the discharge current controlling means comprises a bias circuit 2 for controlling the discharge current based on constant current.

Precision integrated time reference circuits are disclosed. Preferred embodiments provide time reference circuits that are relatively insensitive to variations in process, supply, and temperature. A preferred embodiment of the invention is disclosed in which a relaxation oscillator according to the invention includes a reference voltage circuit configured to maintain a reference voltage in proportion to actual circuit resistance values. Aspects of the invention also include dynamic compensation for variations in temperature.

A first capacitor is arranged such that the electric potential at a first terminal is fixed. A first discharging circuit discharges the first capacitor at a timing that corresponds to a cyclic synchronization signal received from an external circuit. A first comparator compares the voltage at a second terminal of the first capacitor with a predetermined threshold voltage, and generate a judgment signal that corresponds to the comparison result. A charging circuit generates a charging current the current value of which is adjusted according to the level of the judgment signal at a timing that corresponds to the synchronization signal, and supplies the charging current thus generated to the first capacitor.

An oscillator circuit for use in integrated circuits. The oscillator circuit includes a delay generation circuit having a current mirror with at least a first current mirror branch and a second current mirror branch, a current source coupled to the first current mirror branch, a capacitive element coupled to the first current mirror branch; and a resistive element coupled to the second current mirror branch. The oscillator circuit further includes a plurality of inverting elements coupled in series with one another and a transconducting element coupled to an output of the plurality of inverting elements. The transconducting element is configured to discharge the capacitive element. A latching element is coupled to latch to an output signal of the plurality of inverting elements.

A method for producing an oscillating signal comprises: generating an oscillating signal by discharging after charging to a high trigger level and charging after discharging to a low trigger level; and turbo-charging at the initial of a change-over from charging to discharging while resuming a normal charging / discharging thereafter, and vice versa. The present invention makes use of the turbo-charging / discharging for a linear compensation, such that the produced oscillating signal has the features of concurrently eliminating phase noises and jitters as well as maintaining the modulation linearity.

An oscillator comprises a data storage unit, an oscillation unit, and a control unit. The data storage unit is adapted to store a plurality of reference condition codes and a plurality of reference control codes. The oscillation unit is adapted to output an oscillation signal having an oscillation frequency that varies according to a control code. The control unit is adapted to generate the control code with a target value based on the reference condition codes and the reference control codes and a current condition code input to the control unit. Where control code has the target value, the oscillation unit outputs the oscillation signal with the oscillation frequency substantially equal to a target oscillation frequency.