81results about "Pulse generation by differential amplifiers" patented technology

The invention discloses a nanosecond high-voltage steep pulse generator, which relates to the technical field of high-voltage pulses and comprises a microcontroller, a Marx circuit, a trigger control module, an isolation high-voltage driving module, a safety module and a power management module, the microcontroller comprises a main chip, and parameters of the output end of the Marx circuit are collected in real time through the microcontroller. The trigger control module generates a nanosecond synchronous trigger signal; the isolation high-voltage driving module converts a low-voltage signal of the microcontroller into a high-voltage driving signal; the safety module is used for monitoring the state of the system, immediately cutting off a trigger signal when a fault occurs, and protecting the Marx circuit and the microcontroller; according to the invention, the microcontroller is used for generating synchronous trigger pulses and accurately triggering charging and discharging of the capacitor of the Marx circuit, and the high-speed ADC arranged inside can accurately control and detect voltage balance, trigger signals and fault protection.

The invention provides a differential signal generator and a calibration method thereof, and the differential signal generator comprises a control processing unit which is used for obtaining a common-mode bias voltage set value and a differential-mode bias voltage set value, determining a common-mode bias voltage code word according to a first mapping relation, determining a differential-mode bias voltage code word according to a second mapping relation, and setting the common-mode bias voltage set value and the differential-mode bias voltage set value; the common-mode bias voltage code word and the differential-mode bias voltage code word are output to the output amplification unit; the waveform generation unit is connected with the output amplification unit and is used for providing a positive-end alternating-current signal and a negative-end alternating-current signal for the output amplification unit under the control of the control processing unit; the output amplification unit is used for obtaining a positive-end bias intermediate voltage and a negative-end bias intermediate voltage according to the common-mode bias voltage code word and the differential-mode bias voltage code word so as to output a positive-end output signal and a negative-end output signal; the differential signal generator solves the problem that an existing differential signal generator cannot adjust common-mode bias output voltage and differential-mode bias output voltage.

The invention provides an intermediate frequency chip and a clock generation circuit thereof, an intermediate frequency module and a broadband terminal, and the clock generation circuit comprises a phase-locked loop which is used for generating a first clock signal based on a received reference clock signal, the first clock signal is used for representing a clock signal for controlling an analog-to-digital converter to sample in a process of converting an analog signal into a digital signal by the analog-to-digital converter in the intermediate frequency chip; the first frequency divider is used for carrying out frequency division on the first clock signal to generate a second clock signal, and the second clock signal is used for representing a sampling clock signal provided by the intermediate frequency chip to the baseband chip; and the multiplexer is used for outputting a target clock signal based on the received reference clock signal and the second clock signal, and the target clock signal is at least one of the reference clock signal and the second clock signal. According to the clock generation circuit, a plurality of clock generation chips do not need to provide clock signals for the on-chip processor of the baseband chip, so that the cost and complexity of a clock scheme are reduced.

The invention provides a pulse excitation microwave generation device for a quantum limit amplifier, and relates to the technical field of superconducting quantum calculation and other weak microwave signal measurement. The pulse excitation microwave generation device for the quantum limit amplifier comprises a microwave source used for generating continuous microwave signals; the microwave signal direct generation device is used for generating a pulse microwave signal; the frequency mixer is used for carrying out frequency mixing on the continuous microwave signal and the pulse microwave signal to generate a frequency mixing signal; the band-pass filter is used for filtering the frequency mixing signal; and the power amplifier is used for amplifying the filtered frequency mixing signal and generating pulse excitation microwaves for the quantum limit amplifier, so that the implementation cost is greatly reduced, the space occupied by equipment is reduced, and the space is saved.

The present invention belongs to the technical field of integrated circuits and relates to a stable on-chip clock generation circuit. The present invention includes a charge and discharge circuit, a comparator, and a timing logic circuit. Four switches are used in the charge and discharge circuit to jointly control the charging and discharging of the charging capacitor C1 to generate a linearly rising triangular wave signal. The compensation capacitor C2 in the charge and discharge circuit is used to offset the negative voltage mutation caused by the capacitor flip, effectively stabilizing the waveform and frequency of the triangular wave at the charging node VC. The comparator compares the charging triangular wave signal VC with the reference voltage source VREF, and the output signal is supplied to the timing logic circuit. The timing logic circuit is connected to the output of the comparator and is used to generate the first clock SW and the second clock SW_B, and the two are non-overlapping clock signals. By swapping the charging and discharging of the upper and lower plates of the capacitor C1 and combining with the compensation capacitor C2, the present invention can achieve rapid discharge of the charge on the capacitor, with a stable output clock frequency, a simple circuit structure, and low power consumption.

The invention provides a waveform agility high-power microwave generation system based on time reversal and a working method. The system comprises a computer, an arbitrary waveform generator, a first broadband power amplifier, m second broadband power amplifiers, a first time reversal pulse compression cavity, m second time reversal pulse compression cavities, a power divider, a high-speed sampling oscilloscope, m phase shifters, m directional couplers and m radiation antennas. The computer is connected with the arbitrary waveform generator, the high-speed sampling oscilloscope, the phase shifter and the directional coupler; the arbitrary waveform generator is connected with the high-speed sampling oscilloscope through the first time reversal pulse compression cavity on one hand, and is connected with an input port of the power divider through the first broadband power amplifier on the other hand. And m output ports of the power divider are sequentially connected with the radiating antenna through the corresponding second broadband power amplifier, the second time reversal pulse compression cavity, the phase shifter, the directional coupler and the radiating antenna. According to the invention, high-universality broadband internal waveform agility high-power microwave pulse generation can be realized.

An oscillator includes first and second comparators, a first impedance network having a first trim element therein, and a second impedance network having a second trim element therein. The first impedance network is electrically connected to a first input terminal of the first comparator, and the second impedance network is electrically connected to a first input terminal of the second comparator. The first and second impedance networks are configured to cause an improvement in common mode variation within the first and second comparators, in response to trimming of at least one of the first and second trim elements.

In described examples, a retimer includes a reference voltage generator, first, second, third, and fourth comparators, a hit sensor, a window results comparison circuit, and a window control circuit. First inputs of the first, second, third, and fourth comparators receive samples of a data stream. First, second, third, and fourth outputs of the reference voltage generator are coupled to respective second inputs of the first, second, third, and fourth comparators. The third and fourth comparators output to, respectively, first and second inputs of the hit sensor. The hit sensor outputs to an input of the window results comparison circuit. The window results comparison circuit outputs to an input of the window control circuit. The window control circuit outputs to an input of the reference voltage generator.

This article discloses an electronic device and method for overcurrent detection. The electronic device induces a high-side offset voltage drop and converts the voltage difference between a first voltage and a first voltage drop at an input end of an upper bridge power element of a power stage into a first current, wherein the first voltage drop is a superposition of a first balanced voltage drop and a high-side offset voltage drop. The electronic device further performs the following operations: converting the voltage difference between a second voltage and a second balanced voltage drop at an output end of the upper bridge power element into a second current, comparing the first current with the second current, and when the first current is stronger than the second current, generating a high-side overcurrent protection (OCP) signal with a logic high potential for a driver of the power stage, thereby causing the driver to shut down the upper bridge power element accordingly.

Systems and methods for controlled application of hysteresis in crystal oscillator circuits are discussed. In various embodiments, an Integrated Circuit (IC) may include: an inverter comparator coupled to a crystal oscillator, where the inverter comparator is configured to: (i) receive an input of the crystal oscillator, and (ii) output a clock signal; and a hysteresis control circuit coupled to the inverter comparator, wherein the inverter comparator is configured to: (i) start up with hysteresis disabled, and (ii) enable hysteresis in response to a hysteresis enable signal provided by the hysteresis control circuit.

The invention provides a high-precision low-temperature-drift relaxation oscillation system with a symmetrical double-path architecture and a calibration method thereof. The system comprises a symmetric double-channel relaxation oscillator core framework, a fine adjustment circuit, a coarse adjustment circuit and a band-gap reference source module. The method comprises the following steps: S1, acquiring initial working parameters of a relaxation oscillator by a system, and determining an initial frequency value of the oscillator; s2, executing coarse adjustment calibration by a coarse adjustment circuit, and adjusting the frequency of the oscillator to be within a first preset range of a target frequency value; s3, the fine adjustment circuit executes fine adjustment calibration, and further adjusts the frequency of the oscillator to be within a second preset range of the target frequency value; s4, the band-gap reference source module executes temperature compensation calibration; s5, the system adjusts the proportion of the charging current and the discharging current, and duty ratio adjustment is executed; s6, the system executes frequency stability verification; and S7, generating a final calibration configuration and storing the final calibration configuration for long-term use of the oscillator. The invention is applied to the technical field of integrated circuits.

A nanosecond pulse generator based on FPGA control comprises a power supply system, a DC-DC module, a pulse forming system, an FPGA control system and a man-machine interaction system. The power supply system comprises a filtering isolation module and a program-controlled direct-current power supply; the pulse forming system comprises an energy storage capacitor and an LTD high-voltage circuit module; the output end of the FPGA control system controls the pulse forming module to respectively control charging of the energy storage capacitor and discharging of the LTD high-voltage circuit module through a photoelectric isolation circuit, and the input end of the FPGA control system is in communication connection with the program control direct-current power supply and the man-machine interaction system. The nanosecond pulse generator can output nanosecond high-voltage pulses, overhigh voltage is generated at the end of equipment, interference of an electric field in the equipment on time sequence signals can be further eliminated through power amplification and photoelectric conversion, and control is more accurate and stable.

The embodiment of the invention relates to an on-chip oscillation system, and the system comprises a bias generation circuit which processes the voltage of a power input end, and generates a first bias voltage; the starting circuit generates a first branch voltage when the enable signal is overturned to a high level; the oscillation generation circuit comprises first to third stages of reverse phase time shift circuits, the first stage of reverse phase time shift circuit performs charging, and when the first branch voltage is greater than a preset first threshold value and the current of the first stage of reverse phase time shift circuit is greater than a first bias current, the second stage of reverse phase time shift circuit starts and discharges; when the second branch voltage of the second-stage anti-phase time shift circuit is pulled down to a second threshold value, the third-stage anti-phase time shift circuit is started, and a pre-output clock signal is generated; and the clock output circuit generates a pull-up clock signal, performs pull-up shaping on the pre-output clock signal, generates a reverse-phase discharge signal, pulls down the first branch voltage to the ground potential through the reverse-phase discharge signal, inverts the first branch voltage and the pre-output clock signal, and outputs the clock signal.

The invention relates to the technical field of liquid level measurement, in particular to a pulse signal processing circuit and a magnetostrictive liquidometer, and the pulse signal processing circuit comprises an amplitude limiting module which is used for carrying out amplitude limiting processing on a first voltage signal and a second voltage signal transmitted by an induction coil of a magnetostrictive sensor, the first voltage signal is a voltage signal obtained according to an induction pulse signal, and the second voltage signal is a voltage signal obtained according to a strain pulse signal; the signal amplification module is connected with the output of the amplitude limiting module, amplifies the output and outputs the amplified output to a time-to-digital converter of the magnetostriction sensor; according to the pulse signal processing circuit, the interference of the induction pulse signal on the signal processing process of the time-to-digital converter can be well reduced.

A fluctuation oscillator (1) is provided with: an adder (11) that has an input terminal (111) into which inputted is an input signal (S1) including a main signal and an uncorrelated signal which is uncorrelated to the main signal and has a higher frequency than the main signal, and that adds a feedback signal (S5) to the input signal (S1); a threshold value discrimination unit (12) for generating a pulse signal (S3) by comparing, against a threshold value, an addition signal (S2) obtained by addition by the adder (11); a transient response unit (13) for causing transient response of the generated pulse signal (S3) and generating an output signal (S4); and a feedback loop (16) for feeding back the output signal (S4) to the adder (11) as the feedback signal (S5).

According to one implementation of the present disclosure, a circuit includes: two or more metal wires, respective XOR gates coupled to each of the two or more top metal wires, a shift register having outputs coupled to the XOR gates, an OR gate configured to receive each of the outputs of the XOR gates, and a latch configured to receive an output of the OR gate and transmit an output signal corresponding to an alarm signal.

The present application provides an edge modulation transmitter and a digital isolator, which relate to the field of digital circuit technology. The edge modulation transmitter includes a coding control circuit and a common mode noise detection circuit, the common mode noise detection circuit includes at least one multi-stage buffer, at least one current detector and a detection logic circuit, the coding control circuit includes an input logic circuit and a pulse extension circuit, the connection circuit between the detection logic circuit and the pulse extension circuit, at least one multi-stage buffer connected between the input logic circuit and the driving isolator, each current detector of at least one current detector is used to send a current detection signal of at least one multi-stage buffer to the detection logic circuit, and the pulse extension circuit is connected between the input logic circuit and the output end of the detection logic circuit. When the transmitter detects that a large common mode noise appears in the system, adaptive edge modulation is performed through the coding control circuit.

The invention discloses an ultrasonic transmitting circuit capable of adjusting frequency. The ultrasonic transmitting circuit comprises a voltage division circuit, a comparator module, a DFF trigger and a current mirror structure. The voltage division circuit performs voltage division on a power supply through a resistor R1 and a resistor R2 to generate two reference voltages; the comparator module is connected with the voltage division circuit and controls charging and discharging of a capacitor through a P-type MOS tube and an N-type MOS tube so as to generate an oscillation signal; the DFF trigger performs frequency division shaping on the oscillation signal, outputs a pulse signal, and adjusts the oscillation signal to a frequency suitable for working of the transducer; the current mirror structure provides a constant current source for charging and discharging of the capacitor. By optimizing signal generation and power management, more efficient energy utilization and more reliable signal emission are realized, and different working frequencies of the ultrasonic transducer are met.

The invention discloses a low-frequency kiloampere pulse current generator which is characterized by comprising a first working power supply, a second working power supply, a pulse generator and N isolation driver amplification units, wherein the first working power supply is respectively connected with one end of the pulse generator and a first power input end of each isolation driver amplification unit; the other end of the pulse generator is connected with the signal input end of each isolation driver amplification unit; the second working power supply is connected with the second power input end of each isolation driver amplification unit; n is a positive integer. Good test adaptability can be provided for pulse loads such as a TR assembly, and the defect that standard load equipment in the market cannot simulate the instantaneous pulse current is overcome.

The invention discloses a high-reliability pulse trigger circuit for radiation field measurement, and solves the problems that an existing pulse trigger circuit is easy to generate false trigger operation, cannot dynamically adjust and lock time parameters on the premise of not changing hardware configuration, and is weak in reliability and poor in flexibility. The circuit specifically comprises a comparison circuit, a self-locking circuit, a narrow pulse generation circuit and a switching circuit. The in-phase input end of the comparison circuit is used for being connected with external analog signal output equipment, the inverted input end of the comparison circuit is used for being connected with an external threshold voltage power supply Vth, and the output end of the comparison circuit is connected with the B input end of the self-locking circuit; the Q1 output end of the self-locking circuit is connected with the A input end of the self-locking circuit and is used for signal closed-loop feedback; the Y output end of the self-locking circuit is connected with the input end of the narrow pulse generation circuit; the narrow pulse generation circuit is used for generating a narrow pulse trigger signal according to the trigger pulse, and the output end is connected with the input end of the switching circuit; the switching circuit is used for outputting a fast pulse trigger signal.

Derivative Measurement Circuit: This description concerns a circuit (DER) for measuring a derivative. The circuit implements successive cycles, each corresponding to a succession of the first, second, and third periods of a clock signal (clk). In each first period, an input voltage (Vin) is stored on the first capacitor (C1), and the circuit provides a voltage (V3) indicating the difference between the voltage on the second capacitor and the voltage on the third capacitor. In each second period, the input voltage is stored on the second capacitor (C2), and the circuit provides a voltage (V3) indicating the difference between the voltage on the first capacitor and the voltage on the third capacitor. In each third period, the input voltage is stored on the third capacitor (C3), and the circuit provides a voltage indicating the difference between the voltage on the second capacitor and the voltage on the first capacitor.Figure for the summary: Fig. 2.

Disclosed an oscillator circuit device includes: a resistor circuit comprising a first resistor disposed between a first supply voltage level and an output node; a resistor-capacitor circuit comprising a second resistor and at least one capacitor disposed between the output node and a second supply voltage level and connected in series, and a switch capable of discharging electric charges accumulated in the at least one capacitor; and a comparator configured to compare a voltage level to be compared obtained from the resistor circuit with a predetermined reference to allow the switch to be opened and closed according to a comparison result.

The utility model relates to a pulse signal shaping circuit, a pulse signal generation system and electronic equipment. The pulse signal shaping circuit comprises a reference level generation circuit, a comparison circuit and a multiplier, the input end of the reference level generation circuit is connected with the pulse signal generator, the output end of the reference level generation circuit is connected with the first input end of the comparison circuit, the second input end of the comparison circuit is connected with the pulse signal generator, and the output end of the comparison circuit is connected with the first input end of the multiplier. The second input end of the multiplier is connected with the pulse signal generator. According to the technical scheme provided by the invention, the original pulse signal is processed, the original pulse signal is converted into the shaped pulse signal, and the trailing phenomenon of the pulse signal is eliminated.

The invention discloses a pulse circuit, and relates to the technical field of electronics, the pulse circuit comprises a boost circuit, the boost circuit comprises a boost control circuit, a first diode and a first capacitor, the first end of the boost control circuit is connected with one end of the first capacitor, and the other end of the first capacitor is connected with the negative electrode of the first diode; the anode of the first diode is connected with a first power supply; a first end of the signal amplification circuit is connected with a negative electrode of the first diode and the other end of the first capacitor; the second end of the signal amplification circuit is connected with and controls the on-off of the pull-up switch, the first end of the pull-up switch is connected with a second power supply, the first end of the pull-down switch is grounded, and the second end of the pull-up switch is connected with the second end of the pull-down switch so as to cooperate to output pulse signals; and the main control chip is respectively connected with and controls the boost control circuit, the signal amplification circuit and the pull-down switch. The diode and the capacitor are used for boosting, and the production and manufacturing cost is low.

The present application relates to a phase synchronization circuit, a transceiver circuit, and a semiconductor integrated circuit. The phase synchronization circuit has an oscillation circuit (203) including a variable current generation section (222) that generates a variable current corresponding to a control voltage and a fixed current generation section (221) that generates a fixed current corresponding to a correction code, and generates an output clock signal of a frequency corresponding to a total current amount of the variable current and the fixed current, a feedback circuit (204) that generates a feedback clock signal based on the output clock signal, a control voltage generation circuit (202) that, in a normal operation mode, generates the control voltage based on the feedback clock signal and a reference clock signal so that the frequency of the output clock signal becomes a desired frequency, and a correction code generation circuit (201) that, in a correction mode, generates the correction code based on the feedback clock signal and the reference clock signal, and the control voltage generation circuit outputs a fixed control voltage in the correction mode.

The invention provides a pulse generation method and system, electronic equipment and a storage medium, and relates to the technical field of pulse generation, through a mode of combining a digital phase-locked loop and analog delay control, the pulse generation system realizes fine pulse width regulation and control while maintaining high frequency stability, and the pulse generation efficiency is improved. And the accuracy of digital logic and the flexibility of analog regulation and control are both considered. Moreover, a high-quality differential square wave signal is generated through an amplitude limiting amplifier, and then fine phase difference regulation and control are realized in combination with a time delay module, so that a target pulse signal with narrow pulse width, fast edge and accurate pulse width is generated. The digital phase-locked loop and the delay module are controlled by the controller, so that the pulse width can be flexibly adjusted, the pulse period can be controlled, and diversified requirements of different application scenes on pulse parameters can be met. The introduction of the feedback processing module can provide real-time monitoring and correction functions for the controller, and effectively counteracts the influence caused by environment change and drift of each component in the pulse generation system.

The invention aims to provide the module for controlling three wires by using two wires and the control method, an IO expansion chip is not needed, an additional third signal is generated from the existing clock signal, three control signals are obtained from two IO ports, and the purpose of saving cost is achieved. A clock signal is connected to the positive input end of a first voltage comparator through an input resistor, the negative input end of the first voltage comparator is connected with the negative input end of a second voltage comparator, the negative input end of the first voltage comparator is connected with a node of a first divider resistor and a node of a second divider resistor, and the output end of the first voltage comparator is divided into two paths, one path is connected to the positive input end of the second voltage comparator through a charging resistor, the other path is connected to the positive input end of the second voltage comparator through a discharging resistor and a discharging diode, the positive input end of the second voltage comparator is connected with the system ground through a capacitor, and the output end of the second voltage comparator serves as a port of a third signal. The method is applied to the technical field of IO expansion.

According to the duty ratio calibration circuit and the differential clock signal generation device provided by the invention, the duty ratio of an external clock signal can be calibrated to 50% through a collaborative architecture of the common-mode feedback circuit module and the driving circuit module and by adopting a full-analog circuit. A common-mode feedback circuit module collects common-mode levels of differential signals output by a driving circuit in real time, the common-mode levels are directly compared with reference voltage vref to generate a pair of differential control voltages, and then the driving circuit module dynamically corrects input external differential clock signals according to the two signals. The whole process does not need time-consuming links such as ADC analog-to-digital conversion and digital logic operation, the delay problem of a traditional scheme is thoroughly avoided, microsecond-level and even nanosecond-level real-time calibration is finally achieved, the core requirements for rapid initialization when a high-speed system is started and coping with sudden duty ratio deviation in operation can be accurately matched, and the real-time calibration accuracy of the high-speed system is improved. And the overall response efficiency of the system is greatly improved.

Embodiments of the present application relate to a hybrid driver with low output pad capacitance. The hybrid driver receives complementary high-speed input data signals and paired low-speed input data signals, selects a pair of input data signals from the paired input data signals, and drives output data signals on a first output node and a second output node based on the selected pair of input data signals. The hybrid driver includes a first driver circuit and a second driver circuit coupled to the first output node and the second output node, respectively. Each driver circuit includes a first series transistor and a second series transistor coupled between a first supply voltage node and a reference voltage node, wherein the interconnection of the first series transistor and the second series transistor is coupled to a corresponding first output node or a second output node. Each first driver circuit and the second driver circuit include a third transistor coupled in parallel with the corresponding first transistor. In response to the corresponding low-speed input data signal, each first transistor and the third transistor couples the corresponding output node in parallel to the second supply voltage node.

The invention discloses a low-offset sub-sampling phase detector and a phase detection method. A phase detection method includes receiving a reference clock and an input clock including a first input signal and a second input signal; sampling a first input signal and a second input signal according to the reference clock to obtain a first sample and a second sample; converting the first sample and the second sample into a first current and a second current; converting the first current into a third current by using a voltage-stabilizing current mirror; using the first current guiding network to guide the second current to the fourth current or the fifth current according to a pulse signal; using a second current guiding network to guide a third current to a sixth current or a seventh current according to the pulse signal; connecting a low-pass filter to the output node to establish an output voltage and a low-pass filtered voltage; and using a unity gain buffer to equalize the standby voltage to the low-pass filtered voltage.