Clock signal producing circuit

Abstract

The invention provides a clock signal producing circuit. The clock signal producing circuit comprises a small signal amplification unit, a delay unit and a level shifting unit. The small signal amplification unit comprises a first input end for inputting a threshold voltage, a second input end for inputting an oscillation voltage, a first output end for outputting a first differential signal, and a second output end for outputting a second differential signal. The delay unit comprises a third input end connected with the first output end, a fourth input end connected with the second output end, a third output end for outputting the oscillation voltage to the second input end, and a capacitor with one end connected with the third output end. The level shifting unit comprises a fifth input end connected with the first output end, a sixth input end connected with the second output end, a fourth output end for outputting the threshold voltage to the first input end, and a fifth output end for outputting a clock signal. Through adoption of the clock signal producing circuit, the problem of excessive delay error of the clock signal producing circuit in the prior art is solved.

Description

technical field [0001] The invention relates to the field of circuits, in particular to a clock signal generating circuit. Background technique [0002] With the development of semiconductor technology, the working speed of the chip is getting higher and higher, and the requirements for the clock system are getting stricter. For high-speed and high-precision application environments, the delay error of the clock signal generation circuit has an increasingly prominent impact on clock accuracy and cannot be ignored. [0003] The on-chip clock signal generation circuit based on the comparator is widely used in actual chips because of its simple implementation and high reliability. Such as figure 1 As shown, the current clock signal generation circuit mainly includes: signal shaping circuit 102 (RS flip-flop), threshold comparison circuit 104 (comparator 41 (CMP1), comparator 42 (CMP2)), delay generation circuit 106 (constant current source I1 and I2, capacitor C1). The sign...

AI Technical Summary

Problems solved by technology

[0010] The main purpose of the present invention is to provide a clock signal generation circuit, to at least solve the problem of excessive delay error of the clock signal generation circuit in the above-mentioned prior art

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