53results about How to "Reduce delay error" patented technology

The embodiment of the present application provides a synchronization signal control method and a device, which are applied to a synchronization control terminal communicatively connected with each positioning base station. The present application generates a clock signal by controlling the isothermal crystal oscillator, and extracting a first trigger signal after a first clock cycle and a second trigger signal after a second clock cycle of the clock signal, wherein the second clock cycle is the next clock cycle of the first clock cycle, and then a time interval between the first trigger signaland the second trigger signal is calculated, and a transmission time interval of a corresponding synchronization signal transmitted to each positioning base station is adjusted based on the time interval. Therefore, by strictly controlling the interval time of each clock signal and strictly controlling the transmission time interval of the transmitted synchronization signal, the application can effectively reduce the delay error existing in the clock synchronization process between each positioning base station and the synchronization controller, achieve accurate synchronization, and make thepositioning work more stable.

The invention discloses a delay measurement method, device and system of a direct current transmission system. According to the topology of the direct current transmission system, the delay of the entire link is divided into four parts: IO interface link delay, pole control link Delay, valve control link delay, sub-module execution link delay. The delay of each part of the link can be tested independently from the time it receives the signal to the time it sends the signal to the lower system. The start and end signals of the delay test are connected to the delay measurement device to ensure the measurement consistency. Through the test of the overall and partial link delay of the DC transmission system, it plays a vital role in the optimization of the subsequent delay and the compensation of the control.

The invention relates to a system and a method for realizing multi-channel signal analysis synchronization and time delay adjustment. The system comprises a plurality of radio frequency channel units, a plurality of base band processing units, a plurality of data storage units and a precision synchronization unit, wherein the radio frequency channel units respectively correspond to channels; each radio frequency channel unit is used for converting a radio frequency input signal of the corresponding channel into an intermediate frequency signal with a fixed frequency and carrying out digital conversion; the base band processing units respectively correspond to the channels; each base band processing unit is used for carrying out digital signal demodulation, compensation of group delay and time delay error adjustment among the channels on an output signal of the corresponding radio frequency channel unit; the data storage units respectively correspond to the channels; the precision synchronization unit is used for carrying out time delay control on signals of the base band processing units. The system and the method for realizing multi-channel signal analysis synchronization and time delay adjustment, which adopt the structure, realize the requirement for synchronization of multi-channel testing on single equipment, improve the confidence level of multi-channel signal analysis, reduce hardware complexity and have a wider application range.

The invention provides a clock signal producing circuit. The clock signal producing circuit comprises a small signal amplification unit, a delay unit and a level shifting unit. The small signal amplification unit comprises a first input end for inputting a threshold voltage, a second input end for inputting an oscillation voltage, a first output end for outputting a first differential signal, and a second output end for outputting a second differential signal. The delay unit comprises a third input end connected with the first output end, a fourth input end connected with the second output end, a third output end for outputting the oscillation voltage to the second input end, and a capacitor with one end connected with the third output end. The level shifting unit comprises a fifth input end connected with the first output end, a sixth input end connected with the second output end, a fourth output end for outputting the threshold voltage to the first input end, and a fifth output end for outputting a clock signal. Through adoption of the clock signal producing circuit, the problem of excessive delay error of the clock signal producing circuit in the prior art is solved.

Optically controlled microwave beam forming networks comprise 2N single frequency DFB lasers of different wavelengths, , 2N electro-optic intensity modulators, 2N *1 passive wavelength division multiplexers, an optical fiber, 1*2N optical beam splitter, 2N fiber collimator, a time delay network module, 2N coupled lenses, 2N photoelectric detectors and 2N low noise amplifiers, wherein N is an integer larger than 2. The optically controlled microwave beam forming networks have the advantages of the high signal to noise ratio, good dynamic performance, high time delay precision, continuous adjustability, and good stability, and are easy to be extended in the system array size.

This patent discloses a system for simulating communication between nodes, including a control unit, a virtual concentrator, a hardware simulator and a virtual data collection terminal; the control unit is connected to the virtual concentrator, hardware simulator and virtual data collection terminal respectively One-to-one connection; The hardware simulator is also connected with an upper layer module for loading protocol layer and application layer software; The virtual concentrator can simulate the function that the concentrator sends operation commands and receives operation results; The hardware simulator, It can simulate the message sending and receiving function of a certain communication node of the power carrier communication network, and is controlled by the upper layer module; the virtual data acquisition terminal can simulate the function of the data acquisition terminal to generate messages and the function of message sending and receiving; The control unit is used to configure the hardware simulator, the virtual concentrator and the virtual data collection terminal; and connect the hardware simulator and the virtual data collection terminal into a simulated power carrier communication network.