5722 results about "Crystal oscillator" patented technology

Disclosed herein is a system for rapidly resolving position with centimeter-level accuracy for a mobile or stationary receiver [4]. This is achieved by estimating a set of parameters that are related to the integer cycle ambiguities which arise in tracking the carrier phase of satellite downlinks [5,6]. In the preferred embodiment, the technique involves a navigation receiver [4] simultaneously tracking transmissions [6] from Low Earth Orbit Satellites (LEOS) [2] together with transmissions [5] from GPS navigation satellites [1]. The rapid change in the line-of-sight vectors from the receiver [4] to the LEO signal sources [2], due to the orbital motion of the LEOS, enables the resolution with integrity of the integer cycle ambiguities of the GPS signals [5] as well as parameters related to the integer cycle ambiguity on the LEOS signals [6]. These parameters, once identified, enable real-time centimeter-level positioning of the receiver [4]. In order to achieve high-precision position estimates without the use of specialized electronics such as atomic clocks, the technique accounts for instabilities in the crystal oscillators driving the satellite transmitters, as well as those in the reference [3] and user [4] receivers. In addition, the algorithm accommodates as well as to LEOS that receive signals from ground-based transmitters, then re-transmit frequency-converted signals to the ground.

The present invention provides for a system for operating a communication device (20) for reception of scheduled intermittent information messages (22) with a dual mode timer (70) that extends battery life. A controller (50) schedules the timer (70) to power down all idle components of the device (20) between message receptions in a power saving sleep mode to conserve battery power. During active mode when the device is fully active in reception of messages, the timer (70) uses a reference oscillator (90) with a relatively high frequency to support digital processing by the receiver (26). During sleep mode when only the timer is powered on, a much lower frequency sleep oscillator (96) is used to maintain the lowest possible level of power consumption within the timer itself. The timer (70) has provision for automatic temperature calibration to compensate for timing inaccuracies inherent to the low-power low-frequency crystal oscillator (96) used for the sleep mode. The resultant improvement in timer accuracy during sleep mode eliminates the need for an initial reacquisition period following wake up in active mode, thereby reducing battery drain in active mode as well.

A system, apparatus, and method for determining the distance between two objects using an indirect propagation delay measurement is disclosed. A frequency hopping scheme (such as the Bluetooth.TM. technology) is used to measure the relative phase offset of the received signal between the various frequencies. For a given distance between the objects, the phase offset vs. frequency curve is a straight line with the slope dependent upon the measured distance. After the phase of the received signals is detected, the data is plotted on a curve and the slope is calculated. A wireless slave device remains phase locked with another device in a half-duplex communication mode by employing a low-drift phase locked loop employing a voltage controlled crystal oscillator. The phase locked loop further employs a mechanism that provides immunity from transitory phase slip at a time when the loop is opened.

In one embodiment, the present invention includes a test signal generator capable of producing an impedance test signal comprising of a sine wave having a known frequency. The test signal generator may include a crystal oscillator, a counter, and a lookup table. The lookup table output is applied to a digital to analog converter and is then low pass filtered using a conventional analog filter to produce a sine wave of a known frequency and voltage amplitude. The test signal flows through the electrode and combines with an electrophysiological signal to form a combined signal. A signal processor is used to isolate the combined signal into the test signal component and the electrophysiological component. The signal processor digitally low pass filters the combined signal and the output of the low pass filter is the electrophysiological signal. The signal processor then digitally bandpass filters the combined signal using a filter with a center frequency which is the same as the test frequency. The output of this filter is then used to calculate the electrode impedance.

A system for measuring and converting to an observer intelligible form an internal physiological parameter of a medical patient. The invention allows transcutaneous telemetry of the measured information intracranial pressure via a system which includes a patient implanted sensor module and a processing and display module which is external of the patient and optically coupled to the sensor module via an external coupling module. A sensor within the implanted module transduces the measured information and a near infrared (NIR) emitter transmits this telemetry information when interrogated by the complementary external coupling module. Alternately, a set of tuned inductor-crystal circuits versus inductor-crystal comprised in part of a cylindrical crystal oscillator whose resonant frequency is sensed by a dipper circuit arrangement is provided. Power for the sensor module is derived inductively through rectification of a transcutaneously-applied high-frequency alternating electromagnetic field which is generated by a power source within the external coupling module, in concept much like a conventional electrical transformer. A computer within the processing and display module calculates the parameter value from the telemetry signal and represents this data either in numerical, graphical, or analog format.

An oscillator circuit is provided that is preferably a crystal oscillator, where voltage placed across the crystal is regulated. The regulated voltage or amplitude of the cyclical signal across the crystal is monitored and maintained through a regulation circuit that measures a peak voltage across the crystal. Once the peak voltage exceeds a predetermined setpoint value, then a controller within the regulation circuit will reduce a biasing current through an amplifying transistor within the amplifier coupled across the crystal input and output nodes. By regulating the biasing current, gain from the amplifier is also regulated so that unwanted non-linearities and harmonic distortion is not induced within the crystal to cause frequency distortion and unwanted modes of oscillation within the crystal. The amplifier is preferably symmetrical in that the amplifier sources and sinks equal current to reduce unwanted peaks at the negative or positive half cycles of the sinusoidal signal.

The invention discloses a continuous Doppler US imaging system orthogonal intrinsic signal generation device, which comprise a field programmable gate array (FPGA), a crystal oscillator, a first digital-analog converter and a second digital-analog converter. The output end of the field programmable gate array (FPGA) is connected with the input ends of the first digital-analog converter and the second digital-analog converter; the crystal oscillator is respectively connected with the field programmable gate array (FPGA), the first digital-analog converter and the second digital-analog converter; the crystal oscillator is used for supplying synchronizing clock signals to the field programmable gate array (FPGA), the first digital-analog converter and the second digital-analog converter; the field programmable gate array (FPGA) is used for outputting the sine value corresponding to the phase value to the first digital-analog converter according to the input phase value and outputting the cosine value corresponding to the phase value to the second digital-analog converter; the first digital-analog converter is used for converting the sine value into the corresponding analog signals; the second digital-analog converter is used for converting the cosine value into the corresponding analog signals.

A temperature compensated crystal oscillation circuit adapted to be contained within a small device package and providing an output frequency accuracy of approximately + / -2 ppm over a temperature range or less than 2 minutes per year over the temperature range. The device includes crystal and a single integrated circuit wherein the integrated circuit has a temperature sensing circuit with a digital output, control circuitry, a memory circuit and a switched capacitor array for compensating the oscillation of the crystal oscillator over temperature.

A crystal oscillator comprises a rectangular circuit substrate for mounting circuit devices and its metal cover, said circuit substrate has grooves on each long side and on each short side and said metal cover has projections at each aperture end corresponding to the grooves, and which has a swelling from external to internal in each of the projections, wherein both the grooves provided on each short side and the projection of said metal cover are provided at one end of each long side or each short side.

An RFID reader accessible thorough a personal computer and includes a PC card interface and a controller both operating according to clock signals from a crystal oscillator. The RFID reader further includes a linearized power amplifier modulator in a transmit path, a receive chain capable of demodulating EPCglobal Class_1 and Class_0 signals from RFID tags, and an integrated switching device for selecting one of a plurality of antenna for transmitting or receiving RF signals.

Frequency modification circuitry may be employed as part of a crystal oscillator circuit to generate a reference signal with adjustable frequency. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may adjust the frequency of the reference signal in response to one or more frequency control signals. In one example, the frequency modification circuitry may include variable capacitors such as one or more continuously variable and / or discretely variable capacitors for providing coarse and / or fine adjustment of the reference signal frequency.

An apparatus and method for calibrating a non-crystal oscillator in a transceiver unit using a crystal-oscillator includes the step of establishing a time base based upon oscillations of the crystal oscillator. A comparison of the number of oscillations for the non-crystal oscillator and the crystal oscillator is made during a known time period is made. An adjustment is determined based upon the established time base and the compared number of oscillations. The transceiving of the transceiver unit is then controlled based upon this adjustment.

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.

The invention discloses a communication baud rate self-adaptive method, a device and a host computer thereof. The method comprises the following steps: after a slave computer receives a baud rate calibration code sent by the host computer, a built-in timer of the slave computer starts counting from a level falling edge caused by the baud rate calibration code at a preset frequency and stops counting at a level rising edge, and obtains a count value; and the slave computer obtains a baud rate generation register constant according to the count value, and the slave computer sets the baud rate generation register according to the baud rate generation register constant. By adopting the technical proposal, the self-adaptive adjustment of the communication baud rate is realized without adding any hardware, the hardware manufacturing cost is reduced, the method can be applicable to application occasions of any communication baud rates, and is especially applicable to the application occasion that a slave computer crystal oscillator is unstable.

The invention discloses a low power consumption and rapid oscillation starting crystal oscillator module with a transposable start oscillation condition, which consists of an inverting amplifier, an inverting reshaper chain, an automatic gain control loop (AGC), a feedback resistor, a power limitation resistor, and an external passive crystal oscillator and an external load capacitor. The inverting amplifier is provided with a transposable feedback resistor R1, and the transposable start oscillation condition of the crystal oscillator is realized; and the automatic gain control loop (AGC) is inserted between an input end and a bias end of the inverting amplifier, and the contradiction between the oscillation starting time and power consumption is solved. The invention also provides a highresistor realizing IC (integrated circuit) by adopting a transconductance amplifier of micro current source, and a transposable feedback resistor R1 for the oscillator amplifier branch circuit and a high resistor in a pi-shaped filter. The resistance value of the high resistance can be controlled by programming, the start oscillation condition of the oscillator can be adjusted through adjusting the feedback resistance R1, and reliable and quick start oscillation of the oscillator can be realized; and lower phase noise can be realized through adjusting the high resistor in the pi-shaped filter. The crystal oscillator circuit has the characteristics of low power consumption and rapid start oscillation, and can be used for the digital integrated circuit, such as a base band of various of satellite navigation allocation receptors, real time clocks (RTC).

A crystal oscillator emulator integrated circuit comprises a first temperature sensor that senses a first temperature of the integrated circuit. Memory stores calibration parameters and selects at least one of the calibration parameters based on the first temperature. A semiconductor oscillator generates an output signal having a frequency that is based on the calibration parameters. A heater adjusts the first temperature to a predetermined temperature. A disabling circuit disables the heater after the calibration parameters are stored in the memory.

A crystal oscillator emulator integrated circuit comprises a first temperature sensor that senses a first temperature of the integrated circuit. Memory stores calibration parameters and selects at least one of the calibration parameters based on the first temperature. A semiconductor oscillator generates an output signal having a frequency, which is based on the calibration parameters, and an amplitude. An amplitude adjustment module compares the amplitude to a predetermined amplitude and generates a control signal that adjusts the amplitude based on the comparison.

A temperature compensated crystal oscillation circuit adapted to be contained within a small device package and providing an output frequency accuracy of approximately + / -2 ppm over a temperature range or less than 2 minutes per year over the temperature range. The device includes crystal and a single integrated circuit wherein the integrated circuit has a temperature sensing circuit with a digital output, control circuitry, a memory circuit and a switched capacitor array for compensating the oscillation of the crystal oscillator over temperature.

The invention provides an adder-based backup clock calibrated by a GPS. The adder-based backup clock comprises a GPS receiver, a singlechip, a crystal oscillator, a programmable logic device and a time-digital converter (TDC) which are connected in sequence. The frequency of the crystal oscillator is divided into second pulse output by an adder-based clock circuit realized in the programmable logic device, wherein the frequency dividing ratio of the clock circuit can be finely adjusted. By utilizing the characteristic that 1PPS second pulse signals output by the GPS receiver has a random jitter error but no accumulation error while a second pulse generated after the frequency division of the high-stability crystal oscillator has good temporary stability but the accumulation error, the time-digital converter (TDC) is adopted to measure a phase difference between the two second pulses and filter measurement results of multiple times so as to calculate an accuracy error value of the frequency of the crystal oscillator, the error value is converted into a clock step fine-adjusting value and the frequency dividing ratio of the circuit is adjusted to compensate an accuracy error of the crystal oscillator generated by aging so as to realize high-precision backup. The backup clock has the advantages of full digitalization, simple structure, convenient integration and the like.

The present invention relates to a timing system including an integrated circuit having an oscillator that provides both high and low frequency clock signals from a single high frequency crystal without the necessity of a tuning fork crystal. The low frequency signal is available for time-keeping applications, with low power consumption during “idle” periods. The high performance high frequency signal is available on demand for clock and frequency reference use. The oscillator of the present invention provides improved time-keeping accuracy, whilst size, cost and component count is reduced. Furthermore, phase noise and other critical parameters of the high frequency oscillator are not compromised. Shock vulnerability, a known problem for tuning fork crystals, is reduced.

Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and / or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry. Automatic frequency control (AFC) circuitry may be integrated with other components of RF circuitry and may generate frequency control signals for the frequency modification circuitry based on, for example, a signal received from a temperature sensor. Digital-to-analog converter (DAC) circuitry may be integrated with other components of RF circuitry to enable all-digital frequency control communications from baseband processor circuitry to RF circuitry.

A temperature compensated crystal oscillator using an AT cut crystal produces a reference frequency. The temperature compensated crystal oscillator is located inside a temperature controlled oven. The temperature controlled oven provides a stable temperature to the temperature compensated crystal oscillator such that deviations from the reference frequency are reduced.