13results about "Switched capacitor networks" patented technology

A switchable reactance unit includes an RF terminal configured to connect to a transmission line for transmitting a signal at a frequency in a range of 1-200 MHz, and a switching arrangement comprising a plurality of switching elements used in parallel. Each switching element has a control terminal, and is connected to the RF terminal via at least one individual reactance assigned to the switching element and connected in series with the switching element. The switching elements are controllable or controlled via their control terminals in such a way that they switch simultaneously.

In a method of filtering a signal, the signal is sampled to obtain a series of signal values SV0 to SVn. The signal values are stored in form of charges in a series of capacitors C0 to Cn, said series of capacitors corresponding to said series of signal values SV0 to SVn. The charges on each capacitor are then diffused over neighboring capacitors of said series by connecting a resistor for at least partial charge equalization between each pair of consecutive capacitors Ci, Ci+1 (i=0 to n-1) in said series of capacitors for a time interval selected dependent on a desired filtering result. The remaining voltages across the capacitors of the series after said diffusion step represent filtered signal values corresponding to a filtered signal. With this method a Gaussian filtering with an analog circuit is realized in which the band width of the filtering can be easily adapted.

The present disclosure relates to a switched capacitor equalizer. The switched capacitor equalizer according to some embodiments of the present disclosure may include a first integrating amplifier that integrates input voltage in response to an odd clock period and outputs first output voltage, a second integrating amplifier that integrates the input voltage in response to an even clock period and outputs second output voltage, a coupling capacitor that delivers the first output voltage to the second integrating amplifier in response to the odd clock period and delivers the second output voltage to the first integrating amplifier in response to the even clock period, and a first transistor that outputs an odd data signal in response to the odd clock period, and a second transistor that outputs an even data signal in response to the even clock period.

Various embodiments of the disclosure disclose a method and apparatus, comprising: a communication processor; a radio frequency integrated circuit (RFIC) connected to the communication processor and outputting at least one of a first radio frequency signal, a second radio frequency signal, a third radio frequency signal, and a fourth radio frequency signal; a first circuit connected to the RFIC and including a first filter; a first radio frequency front end (RFFE) connected to the first circuit and including a first amplifier configured to amplify the first radio frequency signal and / or the third radio frequency signal; and a second RFFE including a second amplifier configured to amplify the second radio frequency signal and / or the fourth radio frequency signal output from the RFIC, wherein the communication processor is configured to control the first circuit to remove the fourth radio frequency signal induced to the first circuit through the first filter.

The present disclosure relates to a switched capacitor equalizer. The switched capacitor equalizer according to some embodiments of the present disclosure may include a first integrating amplifier that integrates input voltage in response to an odd clock period and outputs first output voltage, a second integrating amplifier that integrates the input voltage in response to an even clock period and outputs second output voltage, a coupling capacitor that delivers the first output voltage to the second integrating amplifier in response to the odd clock period and delivers the second output voltage to the first integrating amplifier in response to the even clock period, and a first transistor that outputs an odd data signal in response to the odd clock period, and a second transistor that outputs an even data signal in response to the even clock period.

SOLUTION: To disclose a pulse width modulation (PWM) generation device having a phase shift element and a wave form combiner, in which the phase shift element contains: a pair of IQ modulators that is constructed so as to receive a reference signal synchronized by the PWM wave form; a digital-analog converter (DAC) that includes first and second outputs coupled to an I / Q input of one IQ modulator of the pair of IQ modulators, and third and fourth outputs and inputs that are coupled to the I / Q input of the other IQ modulator of the pair of IQ modulators; and a micro controller that is coupled to the reference signal by controlling the DAC so as to control a phase shift of a signal IQ1 and a signal IQ2 of each output of the pair of IQ modulators. A wave form combiner includes: a first input coupled to the output of the one of IQ modulator; and a second input coupled to the output of the other IQ modulator.SELECTED DRAWING: Figure 33

The application discloses an indefinite frequency sampling low-pass filter, and relates to the field of filters.The indefinite frequency sampling low-pass filter comprises a switched capacitor sampling filter circuit and an indefinite frequency signal generating circuit; the output end of the indefinite frequency signal generating circuit is connected with the switched capacitor sampling filter circuit; and the indefinite frequency signal generating circuit is used for providing an indefinite frequency control clock signal for the switched capacitor sampling filter circuit.The application can reduce the capacitor area, save the chip cost, and avoid generating a dislocation voltage.

An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and selectively coupling at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.

Various embodiments are described for controlling the resonant frequency of a resonator. The system includes at least one resonant circuit and an active variable reactance circuit that controls the resonant frequency of the at least one resonant circuit. The active variable reactance circuit includes an electrically controllable switching element and a switch controller subcircuit configured to switch the electrically controllable switching element at a frequency of a radio frequency (RF) current or voltage passing through or across the device such that the RF current flowing from a first terminal to a second terminal is substantially sinusoidal.

An apparatus, including: a switched capacitor filter; and an analog-to-digital converter including an input coupled to the switched capacitor filter. A method, includes: operating a switched capacitor filter to filter an input analog signal to generate an output analog signal; and converting the output analog signal into a digital signal.

Analog FIR filter. An FIR filter (15) includes an input terminal for receiving an input signal, a first filter circuit including: a first transconductance device (30a) configured to generate a first current signal (i1) proportional to the input signal; a first analog switch (41a) commutated in n by a first digital gate signal (φ1) and configured to block the current signal when the first digital gate signal has a first value and to transmit the current signal to a first integrating capacitor (45a) when the first digital gate signal has a second value; characterized in that the first digital gate signal (φ1) includes a periodic series of pulses, wherein the pulses have a width proportional to the filter coefficients.

A tracker module is provided that includes a module laminate, an IC chip disposed at the module laminate, and a filter circuit including a plurality of inductors. The IC chip includes at least one switch included in a switched-capacitor circuit and at least one switch included in a supply modulator. The plurality of inductors include a first inductor and a second inductor that are disposed at the module laminate. The first inductor and the second inductor are adjacent to each other. A magnetic flux direction of the first inductor and a magnetic flux direction of the second inductor are perpendicular to each other.

This invention provides a switched-capacitor equalizer that can simultaneously compensate for interference between noise and signals generated in a channel. [Solution] The switched-capacitor equalizer 1210 includes a first integrating amplifier 1211 that integrates the input voltage in accordance with odd clock periods and outputs a first output voltage V_ODD, a second integrating amplifier 1212 that integrates the input voltage in accordance with even clock periods and outputs a second output voltage V_EVEN, a coupling capacitor 1213 that transmits the first output voltage to the second integrating amplifier in accordance with odd clock periods and transmits the second output voltage to the first integrating amplifier in accordance with even clock periods, a first transistor T1 that outputs an odd data signal in accordance with odd clock periods, and a second transistor T2 that outputs an even data signal in accordance with even clock periods.