37results about "Switched capacitor networks" patented technology

A switchable reactance unit includes an RF terminal configured to connect to a transmission line for transmitting a signal at a frequency in a range of 1-200 MHz, and a switching arrangement comprising a plurality of switching elements used in parallel. Each switching element has a control terminal, and is connected to the RF terminal via at least one individual reactance assigned to the switching element and connected in series with the switching element. The switching elements are controllable or controlled via their control terminals in such a way that they switch simultaneously.

The integrator circuit includes an operational amplifier, a first capacitor coupled to an input of the operational amplifier, a second capacitor, and a second switch configured to electrically couple a first terminal of the second capacitor to a second terminal of the first capacitor coupled in parallel with the first capacitor such that a first terminal of the first capacitor is configured to be electrically coupled to a first terminal of the second capacitor by the first switch.

A band pass filter circuit includes an amplifier circuit having a first input terminal to receive a first analog signal; a second input terminal to receive a second analog signal; first and second output terminals; capacitors; and switches. In a first switching mode, the switches are controlled so that the amplifier circuit and a first group of the capacitors connected between the input and output terminals operate as a first band pass filter filtering the first and second analog signals in a differential mode. In a second switching mode, the switches are controlled so that the amplifier circuit and second and third groups of the capacitors form second band pass filters filtering each of the first and second analog signals in a single-ended mode.

In a method of filtering a signal, the signal is sampled to obtain a series of signal values SV0 to SVn. The signal values are stored in form of charges in a series of capacitors C0 to Cn, said series of capacitors corresponding to said series of signal values SV0 to SVn. The charges on each capacitor are then diffused over neighboring capacitors of said series by connecting a resistor for at least partial charge equalization between each pair of consecutive capacitors Ci, Ci+1 (i=0 to n-1) in said series of capacitors for a time interval selected dependent on a desired filtering result. The remaining voltages across the capacitors of the series after said diffusion step represent filtered signal values corresponding to a filtered signal. With this method a Gaussian filtering with an analog circuit is realized in which the band width of the filtering can be easily adapted.

An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and selectively coupling at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.

The present disclosure relates to a switched capacitor equalizer. The switched capacitor equalizer according to some embodiments of the present disclosure may include a first integrating amplifier that integrates input voltage in response to an odd clock period and outputs first output voltage, a second integrating amplifier that integrates the input voltage in response to an even clock period and outputs second output voltage, a coupling capacitor that delivers the first output voltage to the second integrating amplifier in response to the odd clock period and delivers the second output voltage to the first integrating amplifier in response to the even clock period, and a first transistor that outputs an odd data signal in response to the odd clock period, and a second transistor that outputs an even data signal in response to the even clock period.

Described are concepts, systems, circuits and techniques directed toward methods and apparatus for generating one or more pulse width modulated (PWM) waveforms with the ability to dynamically control pulse width and phase with respect to a reference signal.

Circuit for processing an input signal voltage, comprising: an input capacitance (45) coupled between an input node (43) of the circuit and a sampling node (51) of a comparator (55); and a reference capacitance (30) coupled to the sampling node (51) of the comparator (55); a common-mode switch (54) coupled between the sampling node (51) and a reference node (52) of the comparator (55), wherein the circuit is configured such that the input node (43) is set to the input signal voltage while the common mode switch (54) is open.

The present invention discloses a programmable gain amplifier having mode-switching mechanism. An operational amplifier includes a first input terminal, a second input terminal and an output terminal. The second input terminal is coupled to a ground terminal. The output terminal generates an output signal. A variable resistor and a first switch are coupled in series between a first terminal and a second terminal that coupled to the first input terminal. A first variable capacitor and a second switch are coupled in series between the first terminal and the second terminal. A second variable capacitor and a third switch are coupled in series between the first terminal and the ground terminal. A low-pass resistor and a low-pass capacitor are coupled in parallel between the first input terminal and the output terminal. An input resistor is coupled between a signal input terminal and the first terminal to receive an input signal from the signal input terminal. The first, the second and the third switches receive a set of mode-switching signals to switch to form a path or an open-circuit.

Embodiments of this application relate to the field of communication technologies, and provide a discrete-time filter, a receiver, a transmitter, and a communication device, to resolve a problem that extra power consumption and inconvenient adjustment are caused when a feedback coefficient of an existing discrete-time filter is adjusted. The discrete-time filter includes a transconductance circuit, a switched-capacitor filter circuit, a first sampling capacitor, a second sampling capacitor, and a switch, where an output end of the transconductance circuit is connected to a first node through the switched-capacitor filter circuit; both a first end of the first sampling capacitor and a first terminal of the switch are connected to the first node; and both a second terminal of the switch and a second end of the first sampling capacitor are grounded. The second sampling capacitor is connected to the switch, so that sampling is implemented and negative feedback is provided by switching connection ends of the switch, to adjust a feedback coefficient.

The system (105) includes a voltage rail (115), a switched capacitor circuit (110) coupled to the voltage rail, and a ripple cancellation circuit (310). The ripple cancellation circuit includes a current mirror (420) having a first branch (422, 430, 424) and a second branch (426, 435, 228), where the second branch of the current mirror is coupled to the voltage rail (314, 428), a switching circuit (414) having a first terminal (414), a second terminal (416), and a third terminal (418), where the first terminal (414) of the switching circuit is coupled to the first branch (424) of the current mirror and the third terminal (418) is coupled to ground or a reference voltage, and a first capacitor (440) coupled to the second terminal (416) of the switching circuit.

Various embodiments of the disclosure disclose a method and apparatus, comprising: a communication processor; a radio frequency integrated circuit (RFIC) connected to the communication processor and outputting at least one of a first radio frequency signal, a second radio frequency signal, a third radio frequency signal, and a fourth radio frequency signal; a first circuit connected to the RFIC and including a first filter; a first radio frequency front end (RFFE) connected to the first circuit and including a first amplifier configured to amplify the first radio frequency signal and / or the third radio frequency signal; and a second RFFE including a second amplifier configured to amplify the second radio frequency signal and / or the fourth radio frequency signal output from the RFIC, wherein the communication processor is configured to control the first circuit to remove the fourth radio frequency signal induced to the first circuit through the first filter.

The present disclosure relates to a switched capacitor equalizer. The switched capacitor equalizer according to some embodiments of the present disclosure may include a first integrating amplifier that integrates input voltage in response to an odd clock period and outputs first output voltage, a second integrating amplifier that integrates the input voltage in response to an even clock period and outputs second output voltage, a coupling capacitor that delivers the first output voltage to the second integrating amplifier in response to the odd clock period and delivers the second output voltage to the first integrating amplifier in response to the even clock period, and a first transistor that outputs an odd data signal in response to the odd clock period, and a second transistor that outputs an even data signal in response to the even clock period.

SOLUTION: To disclose a pulse width modulation (PWM) generation device having a phase shift element and a wave form combiner, in which the phase shift element contains: a pair of IQ modulators that is constructed so as to receive a reference signal synchronized by the PWM wave form; a digital-analog converter (DAC) that includes first and second outputs coupled to an I / Q input of one IQ modulator of the pair of IQ modulators, and third and fourth outputs and inputs that are coupled to the I / Q input of the other IQ modulator of the pair of IQ modulators; and a micro controller that is coupled to the reference signal by controlling the DAC so as to control a phase shift of a signal IQ1 and a signal IQ2 of each output of the pair of IQ modulators. A wave form combiner includes: a first input coupled to the output of the one of IQ modulator; and a second input coupled to the output of the other IQ modulator.SELECTED DRAWING: Figure 33

The present invention concerns an artificial neuron (20) of a neuronal network (1). The artificial neuron (20) comprises a plurality of input terminals (LINi), each of which is adapted to receive an analog input signal, a plurality of capacitors (Ci,j), each of which is programmable to exhibit a respective desired capacitance, and an operating element (OAj) adapted to combine a plurality of voltage values according to a predetermined mathematical function. Each of these voltage values is proportional to the electric charge accumulated in a respective capacitor (Ci,j) of the plurality of capacitors. Furthermore, the artificial neuron comprises a plurality of switches (ϕk1 - ϕk5) configured to switch the artificial neuron (20) between a first phase, in which the plurality of capacitors (Ci,j) is charged by the corresponding analog input signal, and a second phase in which the plurality of capacitors (Ci,j) is connected in parallel to the operating element (OAj, CFj) which combines the plurality of voltage values proportional to the plurality of electric charges accumulated in the plurality of capacitors (Ci,j). Advantageously, a first terminal of each programmable capacitor (Ci,j) can be selectively connected to a reference terminal, by means of a first switch (ϕk3) of the plurality of switches (ϕk1 - ϕk5) or to an input terminal of the operating element (OAj, CFj) by means of a second switch (ϕk5) of the plurality of switches (ϕk1 - ϕk5). Similarly, a second terminal of each programmable capacitor (Ci,j) can be selectively connected to the input terminal of the operating element (OAj, CFj), by means of a third switch (ϕk4) of the plurality of switches (ϕk1 - ϕk 5), or to the reference terminal by means of a fourth switch (ϕk2) of the plurality of switches (ϕk1 - ϕk5). Furthermore, during the second phase, at least one programmable capacitor (Ci,j) has the first terminal connected to the reference terminal by the first switch (ϕk3) and the second terminal connected to the input terminal of the operating element (OAj, CFj) by the third switch (c|)k4) to deliver a first voltage value to the operating element (OAj, CFj). Alternatively, the at least one programmable capacitor (Ci,j) has the first terminal connected to the input terminal of the operating element (OAj, CFj) by the second switch (ϕk5) and the second terminal connected the reference terminal by the fourth switch (ϕk2) to deliver a second voltage value to the operating element (OAj, CFj), the second voltage value being opposite to the first voltage value.

The application discloses an indefinite frequency sampling low-pass filter, and relates to the field of filters.The indefinite frequency sampling low-pass filter comprises a switched capacitor sampling filter circuit and an indefinite frequency signal generating circuit; the output end of the indefinite frequency signal generating circuit is connected with the switched capacitor sampling filter circuit; and the indefinite frequency signal generating circuit is used for providing an indefinite frequency control clock signal for the switched capacitor sampling filter circuit.The application can reduce the capacitor area, save the chip cost, and avoid generating a dislocation voltage.

A method includes receiving (506) a radio frequency (RF) input signal (108) using at least one non-reciprocal circulator (102, 402). The method also includes generating (510) an RF output signal (110) using at least one of multiple reflective filter elements (104a-104n, 404a-404b). Each reflective filter element is configured to receive an RF signal from the at least one non-reciprocal circulator and to provide a filtered RF signal to the at least one non-reciprocal circulator. The reflective filter elements include amplitude change reflectors configured to modify amplitudes of the RF signal at different frequencies. The RF output signal represents the RF input signal as modified (508) by the at least one of the reflective filter elements.

The signal processing circuit includes: a first sampling capacitor and a second sampling capacitor connected to the input signal path of an analog signal; and a signal processing unit that performs prescribed processing on the analog signal sampled by the first sampling capacitor and the analog signal sampled by the second sampling capacitor. The signal processing circuit performs sampling of the analog signal of one of the first sampling capacitor and the second sampling capacitor, and performing prescribed processing on the analog signal sampled by the other of the first sampling capacitor and the second sampling capacitor based on the signal processing unit in parallel.

This bandpass filter comprises: an input terminal (1) that receives an RF signal as an input; a multi-phase distributor (3) that divides the RF signal input to the input terminal into n RF signals having phases differing by 360 deg / n, where n is a natural number greater than or equal to 1; n signal paths (17-20) that are connected to the multi-phase distributor and each have a sample-and-hold element with two switches, each of the n signal paths sampling and holding one of the n RF signals with phases differing by 360 deg / n from the multi-phase distributor and outputting the held signal; a multi-phase synthesizer (4) that is connected to the n signal paths and synthesizes n signals output from the n signal paths; an output terminal (2) that outputs a signal obtained by the synthesizing by the multi-phase synthesizer; and a clock signal source (21) that outputs a clock signal (S1) that drives all the switches.

An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and selectively coupling at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.

Various embodiments are described for controlling the resonant frequency of a resonator. The system includes at least one resonant circuit and an active variable reactance circuit that controls the resonant frequency of the at least one resonant circuit. The active variable reactance circuit includes an electrically controllable switching element and a switch controller subcircuit configured to switch the electrically controllable switching element at a frequency of a radio frequency (RF) current or voltage passing through or across the device such that the RF current flowing from a first terminal to a second terminal is substantially sinusoidal.

An apparatus, including: a switched capacitor filter; and an analog-to-digital converter including an input coupled to the switched capacitor filter. A method, includes: operating a switched capacitor filter to filter an input analog signal to generate an output analog signal; and converting the output analog signal into a digital signal.

A programmable alias delay device providing output in a desired frequency band and a maximum delay of >5 ns over a broad bandwidth and at a high frequency is disclosed. The device includes an input bandpass filter and an input stage with M sampling switched capacitor elements, reducing the sampling rate by M. The device includes a programmable delay stage with M programmable switched capacitor banks, each bank having N delay switched capacitor storage elements, reducing the sampling rate by M×N. This reduced sampling rate permits smaller sampling switches, with reduced leakage current and longer programmable delay times. The device includes an output reconstruction stage that reconstructs a delayed version of the input signal by combining signals from the programmable delay stage. Using a subsequent output alias filter, an alias band in the desired frequency band is selected and output.

An N-path filter including a plurality of capacitors, wherein each capacitor of the plurality of capacitors is connected to a switch of a plurality of switches, a plurality of gates, wherein each switch of the plurality of switches is coupled to a gate of the plurality of gates, and wherein a CLK signal is applied to each gate of the plurality of gates, and a negative feedback circuit configured for sensing a drain source voltage (VDS) variation of each switch of the plurality of switches, and adjusting a gate source voltage (VGS) based on the VDS.

Analog FIR filter. An FIR filter (15) includes an input terminal for receiving an input signal, a first filter circuit including: a first transconductance device (30a) configured to generate a first current signal (i1) proportional to the input signal; a first analog switch (41a) commutated in n by a first digital gate signal (φ1) and configured to block the current signal when the first digital gate signal has a first value and to transmit the current signal to a first integrating capacitor (45a) when the first digital gate signal has a second value; characterized in that the first digital gate signal (φ1) includes a periodic series of pulses, wherein the pulses have a width proportional to the filter coefficients.

A tracker module is provided that includes a module laminate, an IC chip disposed at the module laminate, and a filter circuit including a plurality of inductors. The IC chip includes at least one switch included in a switched-capacitor circuit and at least one switch included in a supply modulator. The plurality of inductors include a first inductor and a second inductor that are disposed at the module laminate. The first inductor and the second inductor are adjacent to each other. A magnetic flux direction of the first inductor and a magnetic flux direction of the second inductor are perpendicular to each other.

The present invention discloses a switched capacitor circuit and a capacitive digital-to-analog converter. The switched capacitor circuit includes an output capacitor, a first transmission switch, a first reference voltage generator, a second transmission switch, a second reference voltage generator, and a charge compensation circuit. A first terminal of the output capacitor is coupled to an output terminal of the switched capacitor circuit; a second terminal of the output capacitor is coupled to a reference node. The first transmission switch is coupled to the reference node. The first reference voltage generator is coupled to the first transmission switch. The second transmission switch is coupled to the reference node. The second reference voltage generator is coupled to the second transmission switch. The charge compensation circuit is coupled to the reference node.

An integrator circuit includes: an operational amplifier; a first capacitor coupled to an input of the operational amplifier; a second capacitor coupled in parallel to the first capacitor so that a first terminal of the first capacitor is configured to be electrically coupled to a first terminal of the second capacitor by a first switch; and a second switch configured to electrically couple the first terminal of the second capacitor to a second terminal of the first capacitor.

The variable capacitor bank includes a conductive housing and a port extending through the housing. An electrical bus is disposed within the conductive housing and is coupled to the port. The variable capacitor bank further includes a capacitor module disposed within the housing. Each capacitor module includes a module input electrically coupled to the electrical bus and a switched capacitor leg electrically coupled to the module input, the switched capacitor leg including a capacitor and a switching element in series with the capacitor. In some embodiments, one or more of the capacitor modules may include at least one second switched capacitor leg. The capacitor module may further include a switchless or'bottom 'capacitor that provides a minimum capacitance or other known capacitance of the capacitor module. Each capacitor module may be further grounded by being electrically coupled to the conductive housing.